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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/linkage.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24#include <linux/smp.h>
25#include <linux/mm.h>
26#include <linux/slab.h>
27#include <linux/kernel_stat.h>
28
29#include <asm/errno.h>
30#include <asm/signal.h>
31#include <asm/system.h>
32#include <asm/ptrace.h>
33#include <asm/io.h>
34
35#include <asm/sibyte/sb1250_regs.h>
36#include <asm/sibyte/sb1250_int.h>
37#include <asm/sibyte/sb1250_uart.h>
38#include <asm/sibyte/sb1250_scd.h>
39#include <asm/sibyte/sb1250.h>
40
41/*
42 * These are the routines that handle all the low level interrupt stuff.
43 * Actions handled here are: initialization of the interrupt map, requesting of
44 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
45 * for interrupt lines
46 */
47
48
49#define shutdown_sb1250_irq disable_sb1250_irq
50static void end_sb1250_irq(unsigned int irq);
51static void enable_sb1250_irq(unsigned int irq);
52static void disable_sb1250_irq(unsigned int irq);
53static unsigned int startup_sb1250_irq(unsigned int irq);
54static void ack_sb1250_irq(unsigned int irq);
55#ifdef CONFIG_SMP
Andrew Isaacson942d0422005-06-22 16:01:09 -070056static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#endif
58
59#ifdef CONFIG_SIBYTE_HAS_LDT
60extern unsigned long ldt_eoi_space;
61#endif
62
63#ifdef CONFIG_KGDB
64static int kgdb_irq;
65
66/* Default to UART1 */
67int kgdb_port = 1;
68#ifdef CONFIG_SIBYTE_SB1250_DUART
69extern char sb1250_duart_present[];
70#endif
71#endif
72
73static struct hw_interrupt_type sb1250_irq_type = {
Ralf Baechle8ab00b92005-02-28 13:39:57 +000074 .typename = "SB1250-IMR",
75 .startup = startup_sb1250_irq,
76 .shutdown = shutdown_sb1250_irq,
77 .enable = enable_sb1250_irq,
78 .disable = disable_sb1250_irq,
79 .ack = ack_sb1250_irq,
80 .end = end_sb1250_irq,
Linus Torvalds1da177e2005-04-16 15:20:36 -070081#ifdef CONFIG_SMP
Ralf Baechle8ab00b92005-02-28 13:39:57 +000082 .set_affinity = sb1250_set_affinity
Linus Torvalds1da177e2005-04-16 15:20:36 -070083#endif
84};
85
86/* Store the CPU id (not the logical number) */
87int sb1250_irq_owner[SB1250_NR_IRQS];
88
89DEFINE_SPINLOCK(sb1250_imr_lock);
90
91void sb1250_mask_irq(int cpu, int irq)
92{
93 unsigned long flags;
94 u64 cur_ints;
95
96 spin_lock_irqsave(&sb1250_imr_lock, flags);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +000097 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
98 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 cur_ints |= (((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000100 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
101 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
103}
104
105void sb1250_unmask_irq(int cpu, int irq)
106{
107 unsigned long flags;
108 u64 cur_ints;
109
110 spin_lock_irqsave(&sb1250_imr_lock, flags);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000111 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
112 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 cur_ints &= ~(((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000114 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
115 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 spin_unlock_irqrestore(&sb1250_imr_lock, flags);
117}
118
119#ifdef CONFIG_SMP
Andrew Isaacson942d0422005-06-22 16:01:09 -0700120static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121{
122 int i = 0, old_cpu, cpu, int_on;
123 u64 cur_ints;
124 irq_desc_t *desc = irq_desc + irq;
125 unsigned long flags;
126
Andrew Isaacson942d0422005-06-22 16:01:09 -0700127 i = first_cpu(mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
Andrew Isaacson942d0422005-06-22 16:01:09 -0700129 if (cpus_weight(mask) > 1) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
131 return;
132 }
133
134 /* Convert logical CPU to physical CPU */
135 cpu = cpu_logical_map(i);
136
137 /* Protect against other affinity changers and IMR manipulation */
138 spin_lock_irqsave(&desc->lock, flags);
139 spin_lock(&sb1250_imr_lock);
140
141 /* Swizzle each CPU's IMR (but leave the IP selection alone) */
142 old_cpu = sb1250_irq_owner[irq];
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000143 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
144 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 int_on = !(cur_ints & (((u64) 1) << irq));
146 if (int_on) {
147 /* If it was on, mask it */
148 cur_ints |= (((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000149 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
150 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 }
152 sb1250_irq_owner[irq] = cpu;
153 if (int_on) {
154 /* unmask for the new CPU */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000155 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
156 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 cur_ints &= ~(((u64) 1) << irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000158 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
159 R_IMR_INTERRUPT_MASK));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160 }
161 spin_unlock(&sb1250_imr_lock);
162 spin_unlock_irqrestore(&desc->lock, flags);
163}
164#endif
165
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166/*****************************************************************************/
167
168static unsigned int startup_sb1250_irq(unsigned int irq)
169{
170 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
171
172 return 0; /* never anything pending */
173}
174
175
176static void disable_sb1250_irq(unsigned int irq)
177{
178 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
179}
180
181static void enable_sb1250_irq(unsigned int irq)
182{
183 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
184}
185
186
187static void ack_sb1250_irq(unsigned int irq)
188{
189#ifdef CONFIG_SIBYTE_HAS_LDT
190 u64 pending;
191
192 /*
193 * If the interrupt was an HT interrupt, now is the time to
194 * clear it. NOTE: we assume the HT bridge was set up to
195 * deliver the interrupts to all CPUs (which makes affinity
196 * changing easier for us)
197 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000198 pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
199 R_IMR_LDT_INTERRUPT)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700200 pending &= ((u64)1 << (irq));
201 if (pending) {
202 int i;
203 for (i=0; i<NR_CPUS; i++) {
204 int cpu;
205#ifdef CONFIG_SMP
206 cpu = cpu_logical_map(i);
207#else
208 cpu = i;
209#endif
210 /*
211 * Clear for all CPUs so an affinity switch
212 * doesn't find an old status
213 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000214 __raw_writeq(pending,
215 IOADDR(A_IMR_REGISTER(cpu,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216 R_IMR_LDT_INTERRUPT_CLR)));
217 }
218
219 /*
220 * Generate EOI. For Pass 1 parts, EOI is a nop. For
221 * Pass 2, the LDT world may be edge-triggered, but
222 * this EOI shouldn't hurt. If they are
223 * level-sensitive, the EOI is required.
224 */
225 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
226 }
227#endif
228 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
229}
230
231
232static void end_sb1250_irq(unsigned int irq)
233{
234 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
235 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
236 }
237}
238
239
240void __init init_sb1250_irqs(void)
241{
242 int i;
243
244 for (i = 0; i < NR_IRQS; i++) {
245 irq_desc[i].status = IRQ_DISABLED;
246 irq_desc[i].action = 0;
247 irq_desc[i].depth = 1;
248 if (i < SB1250_NR_IRQS) {
249 irq_desc[i].handler = &sb1250_irq_type;
250 sb1250_irq_owner[i] = 0;
251 } else {
252 irq_desc[i].handler = &no_irq_type;
253 }
254 }
255}
256
257
258static irqreturn_t sb1250_dummy_handler(int irq, void *dev_id,
259 struct pt_regs *regs)
260{
261 return IRQ_NONE;
262}
263
264static struct irqaction sb1250_dummy_action = {
265 .handler = sb1250_dummy_handler,
266 .flags = 0,
267 .mask = CPU_MASK_NONE,
268 .name = "sb1250-private",
269 .next = NULL,
270 .dev_id = 0
271};
272
273int sb1250_steal_irq(int irq)
274{
275 irq_desc_t *desc = irq_desc + irq;
276 unsigned long flags;
277 int retval = 0;
278
279 if (irq >= SB1250_NR_IRQS)
280 return -EINVAL;
281
282 spin_lock_irqsave(&desc->lock,flags);
283 /* Don't allow sharing at all for these */
284 if (desc->action != NULL)
285 retval = -EBUSY;
286 else {
287 desc->action = &sb1250_dummy_action;
288 desc->depth = 0;
289 }
290 spin_unlock_irqrestore(&desc->lock,flags);
291 return 0;
292}
293
294/*
295 * arch_init_irq is called early in the boot sequence from init/main.c via
296 * init_IRQ. It is responsible for setting up the interrupt mapper and
297 * installing the handler that will be responsible for dispatching interrupts
298 * to the "right" place.
299 */
300/*
301 * For now, map all interrupts to IP[2]. We could save
302 * some cycles by parceling out system interrupts to different
303 * IP lines, but keep it simple for bringup. We'll also direct
304 * all interrupts to a single CPU; we should probably route
305 * PCI and LDT to one cpu and everything else to the other
306 * to balance the load a bit.
307 *
308 * On the second cpu, everything is set to IP5, which is
309 * ignored, EXCEPT the mailbox interrupt. That one is
310 * set to IP[2] so it is handled. This is needed so we
311 * can do cross-cpu function calls, as requred by SMP
312 */
313
314#define IMR_IP2_VAL K_INT_MAP_I0
315#define IMR_IP3_VAL K_INT_MAP_I1
316#define IMR_IP4_VAL K_INT_MAP_I2
317#define IMR_IP5_VAL K_INT_MAP_I3
318#define IMR_IP6_VAL K_INT_MAP_I4
319
320void __init arch_init_irq(void)
321{
322
323 unsigned int i;
324 u64 tmp;
325 unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
326 STATUSF_IP1 | STATUSF_IP0;
327
328 /* Default everything to IP2 */
329 for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000330 __raw_writeq(IMR_IP2_VAL,
331 IOADDR(A_IMR_REGISTER(0,
332 R_IMR_INTERRUPT_MAP_BASE) +
333 (i << 3)));
334 __raw_writeq(IMR_IP2_VAL,
335 IOADDR(A_IMR_REGISTER(1,
336 R_IMR_INTERRUPT_MAP_BASE) +
337 (i << 3)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700338 }
339
340 init_sb1250_irqs();
341
342 /*
343 * Map the high 16 bits of the mailbox registers to IP[3], for
344 * inter-cpu messages
345 */
346 /* Was I1 */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000347 __raw_writeq(IMR_IP3_VAL,
348 IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
349 (K_INT_MBOX_0 << 3)));
350 __raw_writeq(IMR_IP3_VAL,
351 IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
352 (K_INT_MBOX_0 << 3)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700353
354 /* Clear the mailboxes. The firmware may leave them dirty */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000355 __raw_writeq(0xffffffffffffffffULL,
356 IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
357 __raw_writeq(0xffffffffffffffffULL,
358 IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700359
360 /* Mask everything except the mailbox registers for both cpus */
361 tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000362 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
363 __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700364
365 sb1250_steal_irq(K_INT_MBOX_0);
366
367 /*
368 * Note that the timer interrupts are also mapped, but this is
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700369 * done in sb1250_time_init(). Also, the profiling driver
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 * does its own management of IP7.
371 */
372
373#ifdef CONFIG_KGDB
374 imask |= STATUSF_IP6;
375#endif
376 /* Enable necessary IPs, disable the rest */
377 change_c0_status(ST0_IM, imask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379#ifdef CONFIG_KGDB
380 if (kgdb_flag) {
381 kgdb_irq = K_INT_UART_0 + kgdb_port;
382
Ralf Baechle42a3b4f2005-09-03 15:56:17 -0700383#ifdef CONFIG_SIBYTE_SB1250_DUART
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 sb1250_duart_present[kgdb_port] = 0;
385#endif
386 /* Setup uart 1 settings, mapper */
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000387 __raw_writeq(M_DUART_IMR_BRK,
388 IOADDR(A_DUART_IMRREG(kgdb_port)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
390 sb1250_steal_irq(kgdb_irq);
Maciej W. Rozycki65bda1a2005-02-22 21:51:30 +0000391 __raw_writeq(IMR_IP6_VAL,
392 IOADDR(A_IMR_REGISTER(0,
393 R_IMR_INTERRUPT_MAP_BASE) +
394 (kgdb_irq << 3)));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 sb1250_unmask_irq(0, kgdb_irq);
396 }
397#endif
398}
399
400#ifdef CONFIG_KGDB
401
402#include <linux/delay.h>
403
404#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
405#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
406
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100407static void sb1250_kgdb_interrupt(struct pt_regs *regs)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408{
409 /*
410 * Clear break-change status (allow some time for the remote
411 * host to stop the break, since we would see another
412 * interrupt on the end-of-break too)
413 */
414 kstat_this_cpu.irqs[kgdb_irq]++;
415 mdelay(500);
416 duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
417 M_DUART_RX_EN | M_DUART_TX_EN);
418 set_async_breakpoint(&regs->cp0_epc);
419}
420
421#endif /* CONFIG_KGDB */
Ralf Baechlee4ac58a2006-04-03 17:56:36 +0100422
423static inline int dclz(unsigned long long x)
424{
425 int lz;
426
427 __asm__ (
428 " .set push \n"
429 " .set mips64 \n"
430 " dclz %0, %1 \n"
431 " .set pop \n"
432 : "=r" (lz)
433 : "r" (x));
434
435 return lz;
436}
437
438asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
439{
440 unsigned int pending;
441
442#ifdef CONFIG_SIBYTE_SB1250_PROF
443 /* Set compare to count to silence count/compare timer interrupts */
444 write_c0_count(read_c0_count());
445#endif
446
447 /*
448 * What a pain. We have to be really careful saving the upper 32 bits
449 * of any * register across function calls if we don't want them
450 * trashed--since were running in -o32, the calling routing never saves
451 * the full 64 bits of a register across a function call. Being the
452 * interrupt handler, we're guaranteed that interrupts are disabled
453 * during this code so we don't have to worry about random interrupts
454 * blasting the high 32 bits.
455 */
456
457 pending = read_c0_cause();
458
459#ifdef CONFIG_SIBYTE_SB1250_PROF
460 if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */
461 sbprof_cpu_intr(exception_epc(regs));
462 }
463#endif
464
465 if (pending & CAUSEF_IP4)
466 sb1250_timer_interrupt(regs);
467
468#ifdef CONFIG_SMP
469 if (pending & CAUSEF_IP3)
470 sb1250_mailbox_interrupt(regs);
471#endif
472
473#ifdef CONFIG_KGDB
474 if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
475 sb1250_kgdb_interrupt(regs);
476#endif
477
478 if (pending & CAUSEF_IP2) {
479 unsigned long long mask;
480
481 /*
482 * Default...we've hit an IP[2] interrupt, which means we've
483 * got to check the 1250 interrupt registers to figure out what
484 * to do. Need to detect which CPU we're on, now that
485 ~ smp_affinity is supported.
486 */
487 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
488 R_IMR_INTERRUPT_STATUS_BASE)));
489 if (mask)
490 do_IRQ(63 - dclz(mask), regs);
491 }
492}