Rajendra Nayak | d92b0df | 2011-12-14 17:25:45 +0530 | [diff] [blame] | 1 | OMAP UART controller |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : should be "ti,omap2-uart" for OMAP2 controllers |
| 5 | - compatible : should be "ti,omap3-uart" for OMAP3 controllers |
| 6 | - compatible : should be "ti,omap4-uart" for OMAP4 controllers |
Matt Porter | 5c8a521 | 2015-02-26 10:38:45 -0500 | [diff] [blame] | 7 | - reg : address and length of the register space |
| 8 | - interrupts or interrupts-extended : Should contain the uart interrupt |
| 9 | specifier or both the interrupt |
| 10 | controller phandle and interrupt |
| 11 | specifier. |
Rajendra Nayak | d92b0df | 2011-12-14 17:25:45 +0530 | [diff] [blame] | 12 | - ti,hwmods : Must be "uart<n>", n being the instance number (1-based) |
| 13 | |
| 14 | Optional properties: |
| 15 | - clock-frequency : frequency of the clock input to the UART |
Matt Porter | 5c8a521 | 2015-02-26 10:38:45 -0500 | [diff] [blame] | 16 | - dmas : DMA specifier, consisting of a phandle to the DMA controller |
| 17 | node and a DMA channel number. |
| 18 | - dma-names : "rx" for receive channel, "tx" for transmit channel. |
| 19 | |
| 20 | Example: |
| 21 | |
| 22 | uart4: serial@49042000 { |
| 23 | compatible = "ti,omap3-uart"; |
| 24 | reg = <0x49042000 0x400>; |
| 25 | interrupts = <80>; |
| 26 | dmas = <&sdma 81 &sdma 82>; |
| 27 | dma-names = "tx", "rx"; |
| 28 | ti,hwmods = "uart4"; |
| 29 | clock-frequency = <48000000>; |
| 30 | }; |