blob: 60120e55da41190d9a1d5a776a7d14e09019229e [file] [log] [blame]
Alexandr Smirnov22b619e2008-03-06 18:17:16 +03001/*
2 * Board setup routines for the Emerson KSI8560
3 *
4 * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
5 *
6 * Based on mpc85xx_ads.c maintained by Kumar Gala
7 *
8 * 2008 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 *
13 */
14
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/kdev_t.h>
19#include <linux/delay.h>
20#include <linux/seq_file.h>
21#include <linux/of_platform.h>
22
23#include <asm/system.h>
24#include <asm/time.h>
25#include <asm/machdep.h>
26#include <asm/pci-bridge.h>
27#include <asm/mpic.h>
28#include <mm/mmu_decl.h>
29#include <asm/udbg.h>
30#include <asm/prom.h>
31
32#include <sysdev/fsl_soc.h>
33#include <sysdev/fsl_pci.h>
34
35#include <asm/cpm2.h>
36#include <sysdev/cpm2_pic.h>
37
Dmitry Eremin-Solenikov543a07b2011-11-17 21:56:16 +040038#include "mpc85xx.h"
Alexandr Smirnov22b619e2008-03-06 18:17:16 +030039
40#define KSI8560_CPLD_HVR 0x04 /* Hardware Version Register */
41#define KSI8560_CPLD_PVR 0x08 /* PLD Version Register */
42#define KSI8560_CPLD_RCR1 0x30 /* Reset Command Register 1 */
43
44#define KSI8560_CPLD_RCR1_CPUHR 0x80 /* CPU Hard Reset */
45
46static void __iomem *cpld_base = NULL;
47
48static void machine_restart(char *cmd)
49{
50 if (cpld_base)
51 out_8(cpld_base + KSI8560_CPLD_RCR1, KSI8560_CPLD_RCR1_CPUHR);
52 else
53 printk(KERN_ERR "Can't find CPLD base, hang forever\n");
54
55 for (;;);
56}
57
Alexandr Smirnov22b619e2008-03-06 18:17:16 +030058static void __init ksi8560_pic_init(void)
59{
Kyle Moffette55d7f72011-12-22 10:19:14 +000060 struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
Alexandr Smirnov22b619e2008-03-06 18:17:16 +030061 0, 256, " OpenPIC ");
62 BUG_ON(mpic == NULL);
Alexandr Smirnov22b619e2008-03-06 18:17:16 +030063 mpic_init(mpic);
64
Dmitry Eremin-Solenikov543a07b2011-11-17 21:56:16 +040065 mpc85xx_cpm2_pic_init();
Alexandr Smirnov22b619e2008-03-06 18:17:16 +030066}
67
68#ifdef CONFIG_CPM2
69/*
70 * Setup I/O ports
71 */
72struct cpm_pin {
73 int port, pin, flags;
74};
75
76static struct cpm_pin __initdata ksi8560_pins[] = {
77 /* SCC1 */
78 {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
79 {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
80 {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
81
82 /* SCC2 */
83 {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
84 {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
85 {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
86
87 /* FCC1 */
88 {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
89 {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
90 {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
91 {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
92 {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
93 {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
94 {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
95 {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
96 {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
97 {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
98 {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
99 {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
100 {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
101 {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
102 {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK9 */
103 {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK10 */
104
105};
106
107static void __init init_ioports(void)
108{
109 int i;
110
111 for (i = 0; i < ARRAY_SIZE(ksi8560_pins); i++) {
112 struct cpm_pin *pin = &ksi8560_pins[i];
113 cpm2_set_pin(pin->port, pin->pin, pin->flags);
114 }
115
116 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
117 cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
118 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
119 cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
120 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_RX);
121 cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
122}
123#endif
124
125/*
126 * Setup the architecture
127 */
128static void __init ksi8560_setup_arch(void)
129{
130 struct device_node *cpld;
131
132 cpld = of_find_compatible_node(NULL, NULL, "emerson,KSI8560-cpld");
133 if (cpld)
134 cpld_base = of_iomap(cpld, 0);
135 else
136 printk(KERN_ERR "Can't find CPLD in device tree\n");
137
138 if (ppc_md.progress)
139 ppc_md.progress("ksi8560_setup_arch()", 0);
140
141#ifdef CONFIG_CPM2
142 cpm2_reset();
143 init_ioports();
144#endif
145}
146
147static void ksi8560_show_cpuinfo(struct seq_file *m)
148{
149 uint pvid, svid, phid1;
Alexandr Smirnov22b619e2008-03-06 18:17:16 +0300150
151 pvid = mfspr(SPRN_PVR);
152 svid = mfspr(SPRN_SVR);
153
154 seq_printf(m, "Vendor\t\t: Emerson Network Power\n");
155 seq_printf(m, "Board\t\t: KSI8560\n");
156
157 if (cpld_base) {
158 seq_printf(m, "Hardware rev\t: %d\n",
159 in_8(cpld_base + KSI8560_CPLD_HVR));
160 seq_printf(m, "CPLD rev\t: %d\n",
161 in_8(cpld_base + KSI8560_CPLD_PVR));
162 } else
163 seq_printf(m, "Unknown Hardware and CPLD revs\n");
164
165 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
166 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
167
168 /* Display cpu Pll setting */
169 phid1 = mfspr(SPRN_HID1);
170 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
Alexandr Smirnov22b619e2008-03-06 18:17:16 +0300171}
172
Dmitry Eremin-Solenikov46d026a2011-11-17 21:56:17 +0400173machine_device_initcall(ksi8560, mpc85xx_common_publish_devices);
Alexandr Smirnov22b619e2008-03-06 18:17:16 +0300174
175/*
176 * Called very early, device-tree isn't unflattened
177 */
178static int __init ksi8560_probe(void)
179{
180 unsigned long root = of_get_flat_dt_root();
181
182 return of_flat_dt_is_compatible(root, "emerson,KSI8560");
183}
184
185define_machine(ksi8560) {
186 .name = "KSI8560",
187 .probe = ksi8560_probe,
188 .setup_arch = ksi8560_setup_arch,
189 .init_IRQ = ksi8560_pic_init,
190 .show_cpuinfo = ksi8560_show_cpuinfo,
191 .get_irq = mpic_get_irq,
192 .restart = machine_restart,
193 .calibrate_decr = generic_calibrate_decr,
194};