blob: 0a9f34a2c3aae9e09cf7a3e939ec5737e030be0b [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +02001/dts-v1/;
2
3/include/ "tegra30.dtsi"
4
5/ {
6 model = "NVIDIA Tegra30 Cardhu evaluation board";
7 compatible = "nvidia,cardhu", "nvidia,tegra30";
8
9 memory {
10 reg = < 0x80000000 0x40000000 >;
11 };
12
Stephen Warrene5cbeef2012-03-13 13:28:02 -060013 pinmux@70000000 {
14 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 sdmmc1_clk_pz0 {
19 nvidia,pins = "sdmmc1_clk_pz0";
20 nvidia,function = "sdmmc1";
21 nvidia,pull = <0>;
22 nvidia,tristate = <0>;
23 };
24 sdmmc1_cmd_pz1 {
25 nvidia,pins = "sdmmc1_cmd_pz1",
26 "sdmmc1_dat0_py7",
27 "sdmmc1_dat1_py6",
28 "sdmmc1_dat2_py5",
29 "sdmmc1_dat3_py4";
30 nvidia,function = "sdmmc1";
31 nvidia,pull = <2>;
32 nvidia,tristate = <0>;
33 };
34 sdmmc4_clk_pcc4 {
35 nvidia,pins = "sdmmc4_clk_pcc4",
36 "sdmmc4_rst_n_pcc3";
37 nvidia,function = "sdmmc4";
38 nvidia,pull = <0>;
39 nvidia,tristate = <0>;
40 };
41 sdmmc4_dat0_paa0 {
42 nvidia,pins = "sdmmc4_dat0_paa0",
43 "sdmmc4_dat1_paa1",
44 "sdmmc4_dat2_paa2",
45 "sdmmc4_dat3_paa3",
46 "sdmmc4_dat4_paa4",
47 "sdmmc4_dat5_paa5",
48 "sdmmc4_dat6_paa6",
49 "sdmmc4_dat7_paa7";
50 nvidia,function = "sdmmc4";
51 nvidia,pull = <2>;
52 nvidia,tristate = <0>;
53 };
54 };
55 };
56
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020057 serial@70006000 {
58 clock-frequency = < 408000000 >;
59 };
60
Stephen Warren8c690fd2012-02-02 12:24:19 -070061 serial@70006040 {
62 status = "disable";
63 };
64
65 serial@70006200 {
66 status = "disable";
67 };
68
69 serial@70006300 {
70 status = "disable";
71 };
72
73 serial@70006400 {
74 status = "disable";
75 };
76
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +020077 i2c@7000c000 {
78 clock-frequency = <100000>;
79 };
80
81 i2c@7000c400 {
82 clock-frequency = <100000>;
83 };
84
85 i2c@7000c500 {
86 clock-frequency = <100000>;
87 };
88
89 i2c@7000c700 {
90 clock-frequency = <100000>;
91 };
92
93 i2c@7000d000 {
94 clock-frequency = <100000>;
95 };
Stephen Warren850c4c82012-02-01 16:29:57 -070096
97 sdhci@78000000 {
98 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
99 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
100 power-gpios = <&gpio 31 0>; /* gpio PD7 */
101 };
102
103 sdhci@78000200 {
104 status = "disable";
105 };
106
107 sdhci@78000400 {
108 status = "disable";
109 };
110
111 sdhci@78000400 {
112 support-8bit;
113 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200114};