blob: 3a1189d94a9a793852767a23ddbf34d08d510c4e [file] [log] [blame]
Eric Anholt673a3942008-07-30 12:06:12 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include <linux/swap.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080033#include <linux/pci.h>
Eric Anholt673a3942008-07-30 12:06:12 -070034
Eric Anholt28dfe522008-11-13 15:00:55 -080035#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
36
Eric Anholte47c68e2008-11-14 13:35:19 -080037static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
38static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
Eric Anholte47c68e2008-11-14 13:35:19 -080040static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
41 int write);
42static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
43 uint64_t offset,
44 uint64_t size);
45static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
Eric Anholt673a3942008-07-30 12:06:12 -070046static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -080047static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
48 unsigned alignment);
Jesse Barnes0f973f22009-01-26 17:10:45 -080049static int i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write);
Jesse Barnesde151cf2008-11-12 10:03:55 -080050static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
51static int i915_gem_evict_something(struct drm_device *dev);
Dave Airlie71acb5e2008-12-30 20:31:46 +100052static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -070055
Jesse Barnes79e53942008-11-07 14:24:08 -080056int i915_gem_do_init(struct drm_device *dev, unsigned long start,
57 unsigned long end)
58{
59 drm_i915_private_t *dev_priv = dev->dev_private;
60
61 if (start >= end ||
62 (start & (PAGE_SIZE - 1)) != 0 ||
63 (end & (PAGE_SIZE - 1)) != 0) {
64 return -EINVAL;
65 }
66
67 drm_mm_init(&dev_priv->mm.gtt_space, start,
68 end - start);
69
70 dev->gtt_total = (uint32_t) (end - start);
71
72 return 0;
73}
Keith Packard6dbe2772008-10-14 21:41:13 -070074
Eric Anholt673a3942008-07-30 12:06:12 -070075int
76i915_gem_init_ioctl(struct drm_device *dev, void *data,
77 struct drm_file *file_priv)
78{
Eric Anholt673a3942008-07-30 12:06:12 -070079 struct drm_i915_gem_init *args = data;
Jesse Barnes79e53942008-11-07 14:24:08 -080080 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -070081
82 mutex_lock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -080083 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
Eric Anholt673a3942008-07-30 12:06:12 -070084 mutex_unlock(&dev->struct_mutex);
85
Jesse Barnes79e53942008-11-07 14:24:08 -080086 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -070087}
88
Eric Anholt5a125c32008-10-22 21:40:13 -070089int
90i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
91 struct drm_file *file_priv)
92{
Eric Anholt5a125c32008-10-22 21:40:13 -070093 struct drm_i915_gem_get_aperture *args = data;
Eric Anholt5a125c32008-10-22 21:40:13 -070094
95 if (!(dev->driver->driver_features & DRIVER_GEM))
96 return -ENODEV;
97
98 args->aper_size = dev->gtt_total;
Keith Packard2678d9d2008-11-20 22:54:54 -080099 args->aper_available_size = (args->aper_size -
100 atomic_read(&dev->pin_memory));
Eric Anholt5a125c32008-10-22 21:40:13 -0700101
102 return 0;
103}
104
Eric Anholt673a3942008-07-30 12:06:12 -0700105
106/**
107 * Creates a new mm object and returns a handle to it.
108 */
109int
110i915_gem_create_ioctl(struct drm_device *dev, void *data,
111 struct drm_file *file_priv)
112{
113 struct drm_i915_gem_create *args = data;
114 struct drm_gem_object *obj;
115 int handle, ret;
116
117 args->size = roundup(args->size, PAGE_SIZE);
118
119 /* Allocate the new object */
120 obj = drm_gem_object_alloc(dev, args->size);
121 if (obj == NULL)
122 return -ENOMEM;
123
124 ret = drm_gem_handle_create(file_priv, obj, &handle);
125 mutex_lock(&dev->struct_mutex);
126 drm_gem_object_handle_unreference(obj);
127 mutex_unlock(&dev->struct_mutex);
128
129 if (ret)
130 return ret;
131
132 args->handle = handle;
133
134 return 0;
135}
136
Eric Anholt40123c12009-03-09 13:42:30 -0700137static inline int
Eric Anholteb014592009-03-10 11:44:52 -0700138fast_shmem_read(struct page **pages,
139 loff_t page_base, int page_offset,
140 char __user *data,
141 int length)
142{
143 char __iomem *vaddr;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200144 int unwritten;
Eric Anholteb014592009-03-10 11:44:52 -0700145
146 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
147 if (vaddr == NULL)
148 return -ENOMEM;
Florian Mickler2bc43b52009-04-06 22:55:41 +0200149 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
Eric Anholteb014592009-03-10 11:44:52 -0700150 kunmap_atomic(vaddr, KM_USER0);
151
Florian Mickler2bc43b52009-04-06 22:55:41 +0200152 if (unwritten)
153 return -EFAULT;
154
155 return 0;
Eric Anholteb014592009-03-10 11:44:52 -0700156}
157
158static inline int
Eric Anholt40123c12009-03-09 13:42:30 -0700159slow_shmem_copy(struct page *dst_page,
160 int dst_offset,
161 struct page *src_page,
162 int src_offset,
163 int length)
164{
165 char *dst_vaddr, *src_vaddr;
166
167 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
168 if (dst_vaddr == NULL)
169 return -ENOMEM;
170
171 src_vaddr = kmap_atomic(src_page, KM_USER1);
172 if (src_vaddr == NULL) {
173 kunmap_atomic(dst_vaddr, KM_USER0);
174 return -ENOMEM;
175 }
176
177 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
178
179 kunmap_atomic(src_vaddr, KM_USER1);
180 kunmap_atomic(dst_vaddr, KM_USER0);
181
182 return 0;
183}
184
Eric Anholt673a3942008-07-30 12:06:12 -0700185/**
Eric Anholteb014592009-03-10 11:44:52 -0700186 * This is the fast shmem pread path, which attempts to copy_from_user directly
187 * from the backing pages of the object to the user's address space. On a
188 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
189 */
190static int
191i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
192 struct drm_i915_gem_pread *args,
193 struct drm_file *file_priv)
194{
195 struct drm_i915_gem_object *obj_priv = obj->driver_private;
196 ssize_t remain;
197 loff_t offset, page_base;
198 char __user *user_data;
199 int page_offset, page_length;
200 int ret;
201
202 user_data = (char __user *) (uintptr_t) args->data_ptr;
203 remain = args->size;
204
205 mutex_lock(&dev->struct_mutex);
206
207 ret = i915_gem_object_get_pages(obj);
208 if (ret != 0)
209 goto fail_unlock;
210
211 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
212 args->size);
213 if (ret != 0)
214 goto fail_put_pages;
215
216 obj_priv = obj->driver_private;
217 offset = args->offset;
218
219 while (remain > 0) {
220 /* Operation in this page
221 *
222 * page_base = page offset within aperture
223 * page_offset = offset within page
224 * page_length = bytes to copy for this page
225 */
226 page_base = (offset & ~(PAGE_SIZE-1));
227 page_offset = offset & (PAGE_SIZE-1);
228 page_length = remain;
229 if ((page_offset + remain) > PAGE_SIZE)
230 page_length = PAGE_SIZE - page_offset;
231
232 ret = fast_shmem_read(obj_priv->pages,
233 page_base, page_offset,
234 user_data, page_length);
235 if (ret)
236 goto fail_put_pages;
237
238 remain -= page_length;
239 user_data += page_length;
240 offset += page_length;
241 }
242
243fail_put_pages:
244 i915_gem_object_put_pages(obj);
245fail_unlock:
246 mutex_unlock(&dev->struct_mutex);
247
248 return ret;
249}
250
251/**
252 * This is the fallback shmem pread path, which allocates temporary storage
253 * in kernel space to copy_to_user into outside of the struct_mutex, so we
254 * can copy out of the object's backing pages while holding the struct mutex
255 * and not take page faults.
256 */
257static int
258i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
259 struct drm_i915_gem_pread *args,
260 struct drm_file *file_priv)
261{
262 struct drm_i915_gem_object *obj_priv = obj->driver_private;
263 struct mm_struct *mm = current->mm;
264 struct page **user_pages;
265 ssize_t remain;
266 loff_t offset, pinned_pages, i;
267 loff_t first_data_page, last_data_page, num_pages;
268 int shmem_page_index, shmem_page_offset;
269 int data_page_index, data_page_offset;
270 int page_length;
271 int ret;
272 uint64_t data_ptr = args->data_ptr;
273
274 remain = args->size;
275
276 /* Pin the user pages containing the data. We can't fault while
277 * holding the struct mutex, yet we want to hold it while
278 * dereferencing the user data.
279 */
280 first_data_page = data_ptr / PAGE_SIZE;
281 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
282 num_pages = last_data_page - first_data_page + 1;
283
284 user_pages = kcalloc(num_pages, sizeof(struct page *), GFP_KERNEL);
285 if (user_pages == NULL)
286 return -ENOMEM;
287
288 down_read(&mm->mmap_sem);
289 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
Eric Anholte5e9ecd2009-04-07 16:01:22 -0700290 num_pages, 1, 0, user_pages, NULL);
Eric Anholteb014592009-03-10 11:44:52 -0700291 up_read(&mm->mmap_sem);
292 if (pinned_pages < num_pages) {
293 ret = -EFAULT;
294 goto fail_put_user_pages;
295 }
296
297 mutex_lock(&dev->struct_mutex);
298
299 ret = i915_gem_object_get_pages(obj);
300 if (ret != 0)
301 goto fail_unlock;
302
303 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
304 args->size);
305 if (ret != 0)
306 goto fail_put_pages;
307
308 obj_priv = obj->driver_private;
309 offset = args->offset;
310
311 while (remain > 0) {
312 /* Operation in this page
313 *
314 * shmem_page_index = page number within shmem file
315 * shmem_page_offset = offset within page in shmem file
316 * data_page_index = page number in get_user_pages return
317 * data_page_offset = offset with data_page_index page.
318 * page_length = bytes to copy for this page
319 */
320 shmem_page_index = offset / PAGE_SIZE;
321 shmem_page_offset = offset & ~PAGE_MASK;
322 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
323 data_page_offset = data_ptr & ~PAGE_MASK;
324
325 page_length = remain;
326 if ((shmem_page_offset + page_length) > PAGE_SIZE)
327 page_length = PAGE_SIZE - shmem_page_offset;
328 if ((data_page_offset + page_length) > PAGE_SIZE)
329 page_length = PAGE_SIZE - data_page_offset;
330
331 ret = slow_shmem_copy(user_pages[data_page_index],
332 data_page_offset,
333 obj_priv->pages[shmem_page_index],
334 shmem_page_offset,
335 page_length);
336 if (ret)
337 goto fail_put_pages;
338
339 remain -= page_length;
340 data_ptr += page_length;
341 offset += page_length;
342 }
343
344fail_put_pages:
345 i915_gem_object_put_pages(obj);
346fail_unlock:
347 mutex_unlock(&dev->struct_mutex);
348fail_put_user_pages:
349 for (i = 0; i < pinned_pages; i++) {
350 SetPageDirty(user_pages[i]);
351 page_cache_release(user_pages[i]);
352 }
353 kfree(user_pages);
354
355 return ret;
356}
357
Eric Anholt673a3942008-07-30 12:06:12 -0700358/**
359 * Reads data from the object referenced by handle.
360 *
361 * On error, the contents of *data are undefined.
362 */
363int
364i915_gem_pread_ioctl(struct drm_device *dev, void *data,
365 struct drm_file *file_priv)
366{
367 struct drm_i915_gem_pread *args = data;
368 struct drm_gem_object *obj;
369 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -0700370 int ret;
371
372 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
373 if (obj == NULL)
374 return -EBADF;
375 obj_priv = obj->driver_private;
376
377 /* Bounds check source.
378 *
379 * XXX: This could use review for overflow issues...
380 */
381 if (args->offset > obj->size || args->size > obj->size ||
382 args->offset + args->size > obj->size) {
383 drm_gem_object_unreference(obj);
384 return -EINVAL;
385 }
386
Eric Anholteb014592009-03-10 11:44:52 -0700387 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
388 if (ret != 0)
389 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
Eric Anholt673a3942008-07-30 12:06:12 -0700390
391 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -0700392
Eric Anholteb014592009-03-10 11:44:52 -0700393 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700394}
395
Keith Packard0839ccb2008-10-30 19:38:48 -0700396/* This is the fast write path which cannot handle
397 * page faults in the source data
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700398 */
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700399
Keith Packard0839ccb2008-10-30 19:38:48 -0700400static inline int
401fast_user_write(struct io_mapping *mapping,
402 loff_t page_base, int page_offset,
403 char __user *user_data,
404 int length)
405{
406 char *vaddr_atomic;
407 unsigned long unwritten;
408
409 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
410 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
411 user_data, length);
412 io_mapping_unmap_atomic(vaddr_atomic);
413 if (unwritten)
414 return -EFAULT;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700415 return 0;
Keith Packard0839ccb2008-10-30 19:38:48 -0700416}
417
418/* Here's the write path which can sleep for
419 * page faults
420 */
421
422static inline int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700423slow_kernel_write(struct io_mapping *mapping,
424 loff_t gtt_base, int gtt_offset,
425 struct page *user_page, int user_offset,
426 int length)
Keith Packard0839ccb2008-10-30 19:38:48 -0700427{
Eric Anholt3de09aa2009-03-09 09:42:23 -0700428 char *src_vaddr, *dst_vaddr;
Keith Packard0839ccb2008-10-30 19:38:48 -0700429 unsigned long unwritten;
430
Eric Anholt3de09aa2009-03-09 09:42:23 -0700431 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
432 src_vaddr = kmap_atomic(user_page, KM_USER1);
433 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
434 src_vaddr + user_offset,
435 length);
436 kunmap_atomic(src_vaddr, KM_USER1);
437 io_mapping_unmap_atomic(dst_vaddr);
Keith Packard0839ccb2008-10-30 19:38:48 -0700438 if (unwritten)
439 return -EFAULT;
440 return 0;
Linus Torvalds9b7530cc2008-10-20 14:16:43 -0700441}
442
Eric Anholt40123c12009-03-09 13:42:30 -0700443static inline int
444fast_shmem_write(struct page **pages,
445 loff_t page_base, int page_offset,
446 char __user *data,
447 int length)
448{
449 char __iomem *vaddr;
Dave Airlied0088772009-03-28 20:29:48 -0400450 unsigned long unwritten;
Eric Anholt40123c12009-03-09 13:42:30 -0700451
452 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
453 if (vaddr == NULL)
454 return -ENOMEM;
Dave Airlied0088772009-03-28 20:29:48 -0400455 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
Eric Anholt40123c12009-03-09 13:42:30 -0700456 kunmap_atomic(vaddr, KM_USER0);
457
Dave Airlied0088772009-03-28 20:29:48 -0400458 if (unwritten)
459 return -EFAULT;
Eric Anholt40123c12009-03-09 13:42:30 -0700460 return 0;
461}
462
Eric Anholt3de09aa2009-03-09 09:42:23 -0700463/**
464 * This is the fast pwrite path, where we copy the data directly from the
465 * user into the GTT, uncached.
466 */
Eric Anholt673a3942008-07-30 12:06:12 -0700467static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700468i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
469 struct drm_i915_gem_pwrite *args,
470 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700471{
472 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Keith Packard0839ccb2008-10-30 19:38:48 -0700473 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700474 ssize_t remain;
Keith Packard0839ccb2008-10-30 19:38:48 -0700475 loff_t offset, page_base;
Eric Anholt673a3942008-07-30 12:06:12 -0700476 char __user *user_data;
Keith Packard0839ccb2008-10-30 19:38:48 -0700477 int page_offset, page_length;
478 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700479
480 user_data = (char __user *) (uintptr_t) args->data_ptr;
481 remain = args->size;
482 if (!access_ok(VERIFY_READ, user_data, remain))
483 return -EFAULT;
484
485
486 mutex_lock(&dev->struct_mutex);
487 ret = i915_gem_object_pin(obj, 0);
488 if (ret) {
489 mutex_unlock(&dev->struct_mutex);
490 return ret;
491 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800492 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -0700493 if (ret)
494 goto fail;
495
496 obj_priv = obj->driver_private;
497 offset = obj_priv->gtt_offset + args->offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700498
499 while (remain > 0) {
500 /* Operation in this page
501 *
Keith Packard0839ccb2008-10-30 19:38:48 -0700502 * page_base = page offset within aperture
503 * page_offset = offset within page
504 * page_length = bytes to copy for this page
Eric Anholt673a3942008-07-30 12:06:12 -0700505 */
Keith Packard0839ccb2008-10-30 19:38:48 -0700506 page_base = (offset & ~(PAGE_SIZE-1));
507 page_offset = offset & (PAGE_SIZE-1);
508 page_length = remain;
509 if ((page_offset + remain) > PAGE_SIZE)
510 page_length = PAGE_SIZE - page_offset;
Eric Anholt673a3942008-07-30 12:06:12 -0700511
Keith Packard0839ccb2008-10-30 19:38:48 -0700512 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
513 page_offset, user_data, page_length);
Eric Anholt673a3942008-07-30 12:06:12 -0700514
Keith Packard0839ccb2008-10-30 19:38:48 -0700515 /* If we get a fault while copying data, then (presumably) our
Eric Anholt3de09aa2009-03-09 09:42:23 -0700516 * source page isn't available. Return the error and we'll
517 * retry in the slow path.
Keith Packard0839ccb2008-10-30 19:38:48 -0700518 */
Eric Anholt3de09aa2009-03-09 09:42:23 -0700519 if (ret)
520 goto fail;
Eric Anholt673a3942008-07-30 12:06:12 -0700521
Keith Packard0839ccb2008-10-30 19:38:48 -0700522 remain -= page_length;
523 user_data += page_length;
524 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700525 }
Eric Anholt673a3942008-07-30 12:06:12 -0700526
527fail:
528 i915_gem_object_unpin(obj);
529 mutex_unlock(&dev->struct_mutex);
530
531 return ret;
532}
533
Eric Anholt3de09aa2009-03-09 09:42:23 -0700534/**
535 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
536 * the memory and maps it using kmap_atomic for copying.
537 *
538 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
539 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
540 */
Eric Anholt3043c602008-10-02 12:24:47 -0700541static int
Eric Anholt3de09aa2009-03-09 09:42:23 -0700542i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
543 struct drm_i915_gem_pwrite *args,
544 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700545{
Eric Anholt3de09aa2009-03-09 09:42:23 -0700546 struct drm_i915_gem_object *obj_priv = obj->driver_private;
547 drm_i915_private_t *dev_priv = dev->dev_private;
548 ssize_t remain;
549 loff_t gtt_page_base, offset;
550 loff_t first_data_page, last_data_page, num_pages;
551 loff_t pinned_pages, i;
552 struct page **user_pages;
553 struct mm_struct *mm = current->mm;
554 int gtt_page_offset, data_page_offset, data_page_index, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700555 int ret;
Eric Anholt3de09aa2009-03-09 09:42:23 -0700556 uint64_t data_ptr = args->data_ptr;
557
558 remain = args->size;
559
560 /* Pin the user pages containing the data. We can't fault while
561 * holding the struct mutex, and all of the pwrite implementations
562 * want to hold it while dereferencing the user data.
563 */
564 first_data_page = data_ptr / PAGE_SIZE;
565 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
566 num_pages = last_data_page - first_data_page + 1;
567
568 user_pages = kcalloc(num_pages, sizeof(struct page *), GFP_KERNEL);
569 if (user_pages == NULL)
570 return -ENOMEM;
571
572 down_read(&mm->mmap_sem);
573 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
574 num_pages, 0, 0, user_pages, NULL);
575 up_read(&mm->mmap_sem);
576 if (pinned_pages < num_pages) {
577 ret = -EFAULT;
578 goto out_unpin_pages;
579 }
580
581 mutex_lock(&dev->struct_mutex);
582 ret = i915_gem_object_pin(obj, 0);
583 if (ret)
584 goto out_unlock;
585
586 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
587 if (ret)
588 goto out_unpin_object;
589
590 obj_priv = obj->driver_private;
591 offset = obj_priv->gtt_offset + args->offset;
592
593 while (remain > 0) {
594 /* Operation in this page
595 *
596 * gtt_page_base = page offset within aperture
597 * gtt_page_offset = offset within page in aperture
598 * data_page_index = page number in get_user_pages return
599 * data_page_offset = offset with data_page_index page.
600 * page_length = bytes to copy for this page
601 */
602 gtt_page_base = offset & PAGE_MASK;
603 gtt_page_offset = offset & ~PAGE_MASK;
604 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
605 data_page_offset = data_ptr & ~PAGE_MASK;
606
607 page_length = remain;
608 if ((gtt_page_offset + page_length) > PAGE_SIZE)
609 page_length = PAGE_SIZE - gtt_page_offset;
610 if ((data_page_offset + page_length) > PAGE_SIZE)
611 page_length = PAGE_SIZE - data_page_offset;
612
613 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
614 gtt_page_base, gtt_page_offset,
615 user_pages[data_page_index],
616 data_page_offset,
617 page_length);
618
619 /* If we get a fault while copying data, then (presumably) our
620 * source page isn't available. Return the error and we'll
621 * retry in the slow path.
622 */
623 if (ret)
624 goto out_unpin_object;
625
626 remain -= page_length;
627 offset += page_length;
628 data_ptr += page_length;
629 }
630
631out_unpin_object:
632 i915_gem_object_unpin(obj);
633out_unlock:
634 mutex_unlock(&dev->struct_mutex);
635out_unpin_pages:
636 for (i = 0; i < pinned_pages; i++)
637 page_cache_release(user_pages[i]);
638 kfree(user_pages);
639
640 return ret;
641}
642
Eric Anholt40123c12009-03-09 13:42:30 -0700643/**
644 * This is the fast shmem pwrite path, which attempts to directly
645 * copy_from_user into the kmapped pages backing the object.
646 */
Eric Anholt673a3942008-07-30 12:06:12 -0700647static int
Eric Anholt40123c12009-03-09 13:42:30 -0700648i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
649 struct drm_i915_gem_pwrite *args,
650 struct drm_file *file_priv)
Eric Anholt673a3942008-07-30 12:06:12 -0700651{
Eric Anholt40123c12009-03-09 13:42:30 -0700652 struct drm_i915_gem_object *obj_priv = obj->driver_private;
653 ssize_t remain;
654 loff_t offset, page_base;
655 char __user *user_data;
656 int page_offset, page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700657 int ret;
Eric Anholt40123c12009-03-09 13:42:30 -0700658
659 user_data = (char __user *) (uintptr_t) args->data_ptr;
660 remain = args->size;
Eric Anholt673a3942008-07-30 12:06:12 -0700661
662 mutex_lock(&dev->struct_mutex);
663
Eric Anholt40123c12009-03-09 13:42:30 -0700664 ret = i915_gem_object_get_pages(obj);
665 if (ret != 0)
666 goto fail_unlock;
667
Eric Anholte47c68e2008-11-14 13:35:19 -0800668 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt40123c12009-03-09 13:42:30 -0700669 if (ret != 0)
670 goto fail_put_pages;
Eric Anholt673a3942008-07-30 12:06:12 -0700671
Eric Anholt40123c12009-03-09 13:42:30 -0700672 obj_priv = obj->driver_private;
Eric Anholt673a3942008-07-30 12:06:12 -0700673 offset = args->offset;
Eric Anholt40123c12009-03-09 13:42:30 -0700674 obj_priv->dirty = 1;
Eric Anholt673a3942008-07-30 12:06:12 -0700675
Eric Anholt40123c12009-03-09 13:42:30 -0700676 while (remain > 0) {
677 /* Operation in this page
678 *
679 * page_base = page offset within aperture
680 * page_offset = offset within page
681 * page_length = bytes to copy for this page
682 */
683 page_base = (offset & ~(PAGE_SIZE-1));
684 page_offset = offset & (PAGE_SIZE-1);
685 page_length = remain;
686 if ((page_offset + remain) > PAGE_SIZE)
687 page_length = PAGE_SIZE - page_offset;
688
689 ret = fast_shmem_write(obj_priv->pages,
690 page_base, page_offset,
691 user_data, page_length);
692 if (ret)
693 goto fail_put_pages;
694
695 remain -= page_length;
696 user_data += page_length;
697 offset += page_length;
Eric Anholt673a3942008-07-30 12:06:12 -0700698 }
699
Eric Anholt40123c12009-03-09 13:42:30 -0700700fail_put_pages:
701 i915_gem_object_put_pages(obj);
702fail_unlock:
Eric Anholt673a3942008-07-30 12:06:12 -0700703 mutex_unlock(&dev->struct_mutex);
704
Eric Anholt40123c12009-03-09 13:42:30 -0700705 return ret;
706}
707
708/**
709 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
710 * the memory and maps it using kmap_atomic for copying.
711 *
712 * This avoids taking mmap_sem for faulting on the user's address while the
713 * struct_mutex is held.
714 */
715static int
716i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
717 struct drm_i915_gem_pwrite *args,
718 struct drm_file *file_priv)
719{
720 struct drm_i915_gem_object *obj_priv = obj->driver_private;
721 struct mm_struct *mm = current->mm;
722 struct page **user_pages;
723 ssize_t remain;
724 loff_t offset, pinned_pages, i;
725 loff_t first_data_page, last_data_page, num_pages;
726 int shmem_page_index, shmem_page_offset;
727 int data_page_index, data_page_offset;
728 int page_length;
729 int ret;
730 uint64_t data_ptr = args->data_ptr;
731
732 remain = args->size;
733
734 /* Pin the user pages containing the data. We can't fault while
735 * holding the struct mutex, and all of the pwrite implementations
736 * want to hold it while dereferencing the user data.
737 */
738 first_data_page = data_ptr / PAGE_SIZE;
739 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
740 num_pages = last_data_page - first_data_page + 1;
741
742 user_pages = kcalloc(num_pages, sizeof(struct page *), GFP_KERNEL);
743 if (user_pages == NULL)
744 return -ENOMEM;
745
746 down_read(&mm->mmap_sem);
747 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
748 num_pages, 0, 0, user_pages, NULL);
749 up_read(&mm->mmap_sem);
750 if (pinned_pages < num_pages) {
751 ret = -EFAULT;
752 goto fail_put_user_pages;
753 }
754
755 mutex_lock(&dev->struct_mutex);
756
757 ret = i915_gem_object_get_pages(obj);
758 if (ret != 0)
759 goto fail_unlock;
760
761 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
762 if (ret != 0)
763 goto fail_put_pages;
764
765 obj_priv = obj->driver_private;
766 offset = args->offset;
767 obj_priv->dirty = 1;
768
769 while (remain > 0) {
770 /* Operation in this page
771 *
772 * shmem_page_index = page number within shmem file
773 * shmem_page_offset = offset within page in shmem file
774 * data_page_index = page number in get_user_pages return
775 * data_page_offset = offset with data_page_index page.
776 * page_length = bytes to copy for this page
777 */
778 shmem_page_index = offset / PAGE_SIZE;
779 shmem_page_offset = offset & ~PAGE_MASK;
780 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
781 data_page_offset = data_ptr & ~PAGE_MASK;
782
783 page_length = remain;
784 if ((shmem_page_offset + page_length) > PAGE_SIZE)
785 page_length = PAGE_SIZE - shmem_page_offset;
786 if ((data_page_offset + page_length) > PAGE_SIZE)
787 page_length = PAGE_SIZE - data_page_offset;
788
789 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
790 shmem_page_offset,
791 user_pages[data_page_index],
792 data_page_offset,
793 page_length);
794 if (ret)
795 goto fail_put_pages;
796
797 remain -= page_length;
798 data_ptr += page_length;
799 offset += page_length;
800 }
801
802fail_put_pages:
803 i915_gem_object_put_pages(obj);
804fail_unlock:
805 mutex_unlock(&dev->struct_mutex);
806fail_put_user_pages:
807 for (i = 0; i < pinned_pages; i++)
808 page_cache_release(user_pages[i]);
809 kfree(user_pages);
810
811 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -0700812}
813
814/**
815 * Writes data to the object referenced by handle.
816 *
817 * On error, the contents of the buffer that were to be modified are undefined.
818 */
819int
820i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
821 struct drm_file *file_priv)
822{
823 struct drm_i915_gem_pwrite *args = data;
824 struct drm_gem_object *obj;
825 struct drm_i915_gem_object *obj_priv;
826 int ret = 0;
827
828 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
829 if (obj == NULL)
830 return -EBADF;
831 obj_priv = obj->driver_private;
832
833 /* Bounds check destination.
834 *
835 * XXX: This could use review for overflow issues...
836 */
837 if (args->offset > obj->size || args->size > obj->size ||
838 args->offset + args->size > obj->size) {
839 drm_gem_object_unreference(obj);
840 return -EINVAL;
841 }
842
843 /* We can only do the GTT pwrite on untiled buffers, as otherwise
844 * it would end up going through the fenced access, and we'll get
845 * different detiling behavior between reading and writing.
846 * pread/pwrite currently are reading and writing from the CPU
847 * perspective, requiring manual detiling by the client.
848 */
Dave Airlie71acb5e2008-12-30 20:31:46 +1000849 if (obj_priv->phys_obj)
850 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
851 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
Eric Anholt3de09aa2009-03-09 09:42:23 -0700852 dev->gtt_total != 0) {
853 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
854 if (ret == -EFAULT) {
855 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
856 file_priv);
857 }
Eric Anholt40123c12009-03-09 13:42:30 -0700858 } else {
859 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
860 if (ret == -EFAULT) {
861 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
862 file_priv);
863 }
864 }
Eric Anholt673a3942008-07-30 12:06:12 -0700865
866#if WATCH_PWRITE
867 if (ret)
868 DRM_INFO("pwrite failed %d\n", ret);
869#endif
870
871 drm_gem_object_unreference(obj);
872
873 return ret;
874}
875
876/**
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800877 * Called when user space prepares to use an object with the CPU, either
878 * through the mmap ioctl's mapping or a GTT mapping.
Eric Anholt673a3942008-07-30 12:06:12 -0700879 */
880int
881i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
882 struct drm_file *file_priv)
883{
884 struct drm_i915_gem_set_domain *args = data;
885 struct drm_gem_object *obj;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800886 uint32_t read_domains = args->read_domains;
887 uint32_t write_domain = args->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -0700888 int ret;
889
890 if (!(dev->driver->driver_features & DRIVER_GEM))
891 return -ENODEV;
892
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800893 /* Only handle setting domains to types used by the CPU. */
894 if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
895 return -EINVAL;
896
897 if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
898 return -EINVAL;
899
900 /* Having something in the write domain implies it's in the read
901 * domain, and only that read domain. Enforce that in the request.
902 */
903 if (write_domain != 0 && read_domains != write_domain)
904 return -EINVAL;
905
Eric Anholt673a3942008-07-30 12:06:12 -0700906 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
907 if (obj == NULL)
908 return -EBADF;
909
910 mutex_lock(&dev->struct_mutex);
911#if WATCH_BUF
912 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800913 obj, obj->size, read_domains, write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -0700914#endif
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800915 if (read_domains & I915_GEM_DOMAIN_GTT) {
916 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
Eric Anholt02354392008-11-26 13:58:13 -0800917
918 /* Silently promote "you're not bound, there was nothing to do"
919 * to success, since the client was just asking us to
920 * make sure everything was done.
921 */
922 if (ret == -EINVAL)
923 ret = 0;
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800924 } else {
Eric Anholte47c68e2008-11-14 13:35:19 -0800925 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
Eric Anholt2ef7eea2008-11-10 10:53:25 -0800926 }
927
Eric Anholt673a3942008-07-30 12:06:12 -0700928 drm_gem_object_unreference(obj);
929 mutex_unlock(&dev->struct_mutex);
930 return ret;
931}
932
933/**
934 * Called when user space has done writes to this buffer
935 */
936int
937i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
938 struct drm_file *file_priv)
939{
940 struct drm_i915_gem_sw_finish *args = data;
941 struct drm_gem_object *obj;
942 struct drm_i915_gem_object *obj_priv;
943 int ret = 0;
944
945 if (!(dev->driver->driver_features & DRIVER_GEM))
946 return -ENODEV;
947
948 mutex_lock(&dev->struct_mutex);
949 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
950 if (obj == NULL) {
951 mutex_unlock(&dev->struct_mutex);
952 return -EBADF;
953 }
954
955#if WATCH_BUF
956 DRM_INFO("%s: sw_finish %d (%p %d)\n",
957 __func__, args->handle, obj, obj->size);
958#endif
959 obj_priv = obj->driver_private;
960
961 /* Pinned buffers may be scanout, so flush the cache */
Eric Anholte47c68e2008-11-14 13:35:19 -0800962 if (obj_priv->pin_count)
963 i915_gem_object_flush_cpu_write_domain(obj);
964
Eric Anholt673a3942008-07-30 12:06:12 -0700965 drm_gem_object_unreference(obj);
966 mutex_unlock(&dev->struct_mutex);
967 return ret;
968}
969
970/**
971 * Maps the contents of an object, returning the address it is mapped
972 * into.
973 *
974 * While the mapping holds a reference on the contents of the object, it doesn't
975 * imply a ref on the object itself.
976 */
977int
978i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv)
980{
981 struct drm_i915_gem_mmap *args = data;
982 struct drm_gem_object *obj;
983 loff_t offset;
984 unsigned long addr;
985
986 if (!(dev->driver->driver_features & DRIVER_GEM))
987 return -ENODEV;
988
989 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
990 if (obj == NULL)
991 return -EBADF;
992
993 offset = args->offset;
994
995 down_write(&current->mm->mmap_sem);
996 addr = do_mmap(obj->filp, 0, args->size,
997 PROT_READ | PROT_WRITE, MAP_SHARED,
998 args->offset);
999 up_write(&current->mm->mmap_sem);
1000 mutex_lock(&dev->struct_mutex);
1001 drm_gem_object_unreference(obj);
1002 mutex_unlock(&dev->struct_mutex);
1003 if (IS_ERR((void *)addr))
1004 return addr;
1005
1006 args->addr_ptr = (uint64_t) addr;
1007
1008 return 0;
1009}
1010
Jesse Barnesde151cf2008-11-12 10:03:55 -08001011/**
1012 * i915_gem_fault - fault a page into the GTT
1013 * vma: VMA in question
1014 * vmf: fault info
1015 *
1016 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1017 * from userspace. The fault handler takes care of binding the object to
1018 * the GTT (if needed), allocating and programming a fence register (again,
1019 * only if needed based on whether the old reg is still valid or the object
1020 * is tiled) and inserting a new PTE into the faulting process.
1021 *
1022 * Note that the faulting process may involve evicting existing objects
1023 * from the GTT and/or fence registers to make room. So performance may
1024 * suffer if the GTT working set is large or there are few fence registers
1025 * left.
1026 */
1027int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1028{
1029 struct drm_gem_object *obj = vma->vm_private_data;
1030 struct drm_device *dev = obj->dev;
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1033 pgoff_t page_offset;
1034 unsigned long pfn;
1035 int ret = 0;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001036 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001037
1038 /* We don't use vmf->pgoff since that has the fake offset */
1039 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1040 PAGE_SHIFT;
1041
1042 /* Now bind it into the GTT if needed */
1043 mutex_lock(&dev->struct_mutex);
1044 if (!obj_priv->gtt_space) {
1045 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1046 if (ret) {
1047 mutex_unlock(&dev->struct_mutex);
1048 return VM_FAULT_SIGBUS;
1049 }
1050 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
1051 }
1052
1053 /* Need a new fence register? */
1054 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001055 obj_priv->tiling_mode != I915_TILING_NONE) {
Jesse Barnes0f973f22009-01-26 17:10:45 -08001056 ret = i915_gem_object_get_fence_reg(obj, write);
Chris Wilson7d8d58b2009-02-04 14:15:10 +00001057 if (ret) {
1058 mutex_unlock(&dev->struct_mutex);
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001059 return VM_FAULT_SIGBUS;
Chris Wilson7d8d58b2009-02-04 14:15:10 +00001060 }
Eric Anholtd9ddcb92009-01-27 10:33:49 -08001061 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001062
1063 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1064 page_offset;
1065
1066 /* Finally, remap it using the new GTT offset */
1067 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1068
1069 mutex_unlock(&dev->struct_mutex);
1070
1071 switch (ret) {
1072 case -ENOMEM:
1073 case -EAGAIN:
1074 return VM_FAULT_OOM;
1075 case -EFAULT:
Jesse Barnes959b8872009-03-20 14:16:33 -07001076 case -EINVAL:
Jesse Barnesde151cf2008-11-12 10:03:55 -08001077 return VM_FAULT_SIGBUS;
1078 default:
1079 return VM_FAULT_NOPAGE;
1080 }
1081}
1082
1083/**
1084 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1085 * @obj: obj in question
1086 *
1087 * GEM memory mapping works by handing back to userspace a fake mmap offset
1088 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1089 * up the object based on the offset and sets up the various memory mapping
1090 * structures.
1091 *
1092 * This routine allocates and attaches a fake offset for @obj.
1093 */
1094static int
1095i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1096{
1097 struct drm_device *dev = obj->dev;
1098 struct drm_gem_mm *mm = dev->mm_private;
1099 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1100 struct drm_map_list *list;
Benjamin Herrenschmidtf77d3902009-02-02 16:55:46 +11001101 struct drm_local_map *map;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001102 int ret = 0;
1103
1104 /* Set the object up for mmap'ing */
1105 list = &obj->map_list;
1106 list->map = drm_calloc(1, sizeof(struct drm_map_list),
1107 DRM_MEM_DRIVER);
1108 if (!list->map)
1109 return -ENOMEM;
1110
1111 map = list->map;
1112 map->type = _DRM_GEM;
1113 map->size = obj->size;
1114 map->handle = obj;
1115
1116 /* Get a DRM GEM mmap offset allocated... */
1117 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1118 obj->size / PAGE_SIZE, 0, 0);
1119 if (!list->file_offset_node) {
1120 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1121 ret = -ENOMEM;
1122 goto out_free_list;
1123 }
1124
1125 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1126 obj->size / PAGE_SIZE, 0);
1127 if (!list->file_offset_node) {
1128 ret = -ENOMEM;
1129 goto out_free_list;
1130 }
1131
1132 list->hash.key = list->file_offset_node->start;
1133 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1134 DRM_ERROR("failed to add to map hash\n");
1135 goto out_free_mm;
1136 }
1137
1138 /* By now we should be all set, any drm_mmap request on the offset
1139 * below will get to our mmap & fault handler */
1140 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1141
1142 return 0;
1143
1144out_free_mm:
1145 drm_mm_put_block(list->file_offset_node);
1146out_free_list:
1147 drm_free(list->map, sizeof(struct drm_map_list), DRM_MEM_DRIVER);
1148
1149 return ret;
1150}
1151
Jesse Barnesab00b3e2009-02-11 14:01:46 -08001152static void
1153i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1154{
1155 struct drm_device *dev = obj->dev;
1156 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1157 struct drm_gem_mm *mm = dev->mm_private;
1158 struct drm_map_list *list;
1159
1160 list = &obj->map_list;
1161 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1162
1163 if (list->file_offset_node) {
1164 drm_mm_put_block(list->file_offset_node);
1165 list->file_offset_node = NULL;
1166 }
1167
1168 if (list->map) {
1169 drm_free(list->map, sizeof(struct drm_map), DRM_MEM_DRIVER);
1170 list->map = NULL;
1171 }
1172
1173 obj_priv->mmap_offset = 0;
1174}
1175
Jesse Barnesde151cf2008-11-12 10:03:55 -08001176/**
1177 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1178 * @obj: object to check
1179 *
1180 * Return the required GTT alignment for an object, taking into account
1181 * potential fence register mapping if needed.
1182 */
1183static uint32_t
1184i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1185{
1186 struct drm_device *dev = obj->dev;
1187 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1188 int start, i;
1189
1190 /*
1191 * Minimum alignment is 4k (GTT page size), but might be greater
1192 * if a fence register is needed for the object.
1193 */
1194 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1195 return 4096;
1196
1197 /*
1198 * Previous chips need to be aligned to the size of the smallest
1199 * fence register that can contain the object.
1200 */
1201 if (IS_I9XX(dev))
1202 start = 1024*1024;
1203 else
1204 start = 512*1024;
1205
1206 for (i = start; i < obj->size; i <<= 1)
1207 ;
1208
1209 return i;
1210}
1211
1212/**
1213 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1214 * @dev: DRM device
1215 * @data: GTT mapping ioctl data
1216 * @file_priv: GEM object info
1217 *
1218 * Simply returns the fake offset to userspace so it can mmap it.
1219 * The mmap call will end up in drm_gem_mmap(), which will set things
1220 * up so we can get faults in the handler above.
1221 *
1222 * The fault handler will take care of binding the object into the GTT
1223 * (since it may have been evicted to make room for something), allocating
1224 * a fence register, and mapping the appropriate aperture address into
1225 * userspace.
1226 */
1227int
1228i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1229 struct drm_file *file_priv)
1230{
1231 struct drm_i915_gem_mmap_gtt *args = data;
1232 struct drm_i915_private *dev_priv = dev->dev_private;
1233 struct drm_gem_object *obj;
1234 struct drm_i915_gem_object *obj_priv;
1235 int ret;
1236
1237 if (!(dev->driver->driver_features & DRIVER_GEM))
1238 return -ENODEV;
1239
1240 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1241 if (obj == NULL)
1242 return -EBADF;
1243
1244 mutex_lock(&dev->struct_mutex);
1245
1246 obj_priv = obj->driver_private;
1247
1248 if (!obj_priv->mmap_offset) {
1249 ret = i915_gem_create_mmap_offset(obj);
Chris Wilson13af1062009-02-11 14:26:31 +00001250 if (ret) {
1251 drm_gem_object_unreference(obj);
1252 mutex_unlock(&dev->struct_mutex);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001253 return ret;
Chris Wilson13af1062009-02-11 14:26:31 +00001254 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08001255 }
1256
1257 args->offset = obj_priv->mmap_offset;
1258
1259 obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj);
1260
1261 /* Make sure the alignment is correct for fence regs etc */
1262 if (obj_priv->agp_mem &&
1263 (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) {
1264 drm_gem_object_unreference(obj);
1265 mutex_unlock(&dev->struct_mutex);
1266 return -EINVAL;
1267 }
1268
1269 /*
1270 * Pull it into the GTT so that we have a page list (makes the
1271 * initial fault faster and any subsequent flushing possible).
1272 */
1273 if (!obj_priv->agp_mem) {
1274 ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment);
1275 if (ret) {
1276 drm_gem_object_unreference(obj);
1277 mutex_unlock(&dev->struct_mutex);
1278 return ret;
1279 }
1280 list_add(&obj_priv->list, &dev_priv->mm.inactive_list);
1281 }
1282
1283 drm_gem_object_unreference(obj);
1284 mutex_unlock(&dev->struct_mutex);
1285
1286 return 0;
1287}
1288
Ben Gamari6911a9b2009-04-02 11:24:54 -07001289void
Eric Anholt856fa192009-03-19 14:10:50 -07001290i915_gem_object_put_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001291{
1292 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1293 int page_count = obj->size / PAGE_SIZE;
1294 int i;
1295
Eric Anholt856fa192009-03-19 14:10:50 -07001296 BUG_ON(obj_priv->pages_refcount == 0);
1297
1298 if (--obj_priv->pages_refcount != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001299 return;
1300
Eric Anholt673a3942008-07-30 12:06:12 -07001301 for (i = 0; i < page_count; i++)
Eric Anholt856fa192009-03-19 14:10:50 -07001302 if (obj_priv->pages[i] != NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07001303 if (obj_priv->dirty)
Eric Anholt856fa192009-03-19 14:10:50 -07001304 set_page_dirty(obj_priv->pages[i]);
1305 mark_page_accessed(obj_priv->pages[i]);
1306 page_cache_release(obj_priv->pages[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07001307 }
1308 obj_priv->dirty = 0;
1309
Eric Anholt856fa192009-03-19 14:10:50 -07001310 drm_free(obj_priv->pages,
Eric Anholt673a3942008-07-30 12:06:12 -07001311 page_count * sizeof(struct page *),
1312 DRM_MEM_DRIVER);
Eric Anholt856fa192009-03-19 14:10:50 -07001313 obj_priv->pages = NULL;
Eric Anholt673a3942008-07-30 12:06:12 -07001314}
1315
1316static void
Eric Anholtce44b0e2008-11-06 16:00:31 -08001317i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
Eric Anholt673a3942008-07-30 12:06:12 -07001318{
1319 struct drm_device *dev = obj->dev;
1320 drm_i915_private_t *dev_priv = dev->dev_private;
1321 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1322
1323 /* Add a reference if we're newly entering the active list. */
1324 if (!obj_priv->active) {
1325 drm_gem_object_reference(obj);
1326 obj_priv->active = 1;
1327 }
1328 /* Move from whatever list we were on to the tail of execution. */
Carl Worth5e118f42009-03-20 11:54:25 -07001329 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001330 list_move_tail(&obj_priv->list,
1331 &dev_priv->mm.active_list);
Carl Worth5e118f42009-03-20 11:54:25 -07001332 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholtce44b0e2008-11-06 16:00:31 -08001333 obj_priv->last_rendering_seqno = seqno;
Eric Anholt673a3942008-07-30 12:06:12 -07001334}
1335
Eric Anholtce44b0e2008-11-06 16:00:31 -08001336static void
1337i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1338{
1339 struct drm_device *dev = obj->dev;
1340 drm_i915_private_t *dev_priv = dev->dev_private;
1341 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1342
1343 BUG_ON(!obj_priv->active);
1344 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1345 obj_priv->last_rendering_seqno = 0;
1346}
Eric Anholt673a3942008-07-30 12:06:12 -07001347
1348static void
1349i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1350{
1351 struct drm_device *dev = obj->dev;
1352 drm_i915_private_t *dev_priv = dev->dev_private;
1353 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1354
1355 i915_verify_inactive(dev, __FILE__, __LINE__);
1356 if (obj_priv->pin_count != 0)
1357 list_del_init(&obj_priv->list);
1358 else
1359 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1360
Eric Anholtce44b0e2008-11-06 16:00:31 -08001361 obj_priv->last_rendering_seqno = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07001362 if (obj_priv->active) {
1363 obj_priv->active = 0;
1364 drm_gem_object_unreference(obj);
1365 }
1366 i915_verify_inactive(dev, __FILE__, __LINE__);
1367}
1368
1369/**
1370 * Creates a new sequence number, emitting a write of it to the status page
1371 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1372 *
1373 * Must be called with struct_lock held.
1374 *
1375 * Returned sequence numbers are nonzero on success.
1376 */
1377static uint32_t
1378i915_add_request(struct drm_device *dev, uint32_t flush_domains)
1379{
1380 drm_i915_private_t *dev_priv = dev->dev_private;
1381 struct drm_i915_gem_request *request;
1382 uint32_t seqno;
1383 int was_empty;
1384 RING_LOCALS;
1385
1386 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
1387 if (request == NULL)
1388 return 0;
1389
1390 /* Grab the seqno we're going to make this request be, and bump the
1391 * next (skipping 0 so it can be the reserved no-seqno value).
1392 */
1393 seqno = dev_priv->mm.next_gem_seqno;
1394 dev_priv->mm.next_gem_seqno++;
1395 if (dev_priv->mm.next_gem_seqno == 0)
1396 dev_priv->mm.next_gem_seqno++;
1397
1398 BEGIN_LP_RING(4);
1399 OUT_RING(MI_STORE_DWORD_INDEX);
1400 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1401 OUT_RING(seqno);
1402
1403 OUT_RING(MI_USER_INTERRUPT);
1404 ADVANCE_LP_RING();
1405
1406 DRM_DEBUG("%d\n", seqno);
1407
1408 request->seqno = seqno;
1409 request->emitted_jiffies = jiffies;
Eric Anholt673a3942008-07-30 12:06:12 -07001410 was_empty = list_empty(&dev_priv->mm.request_list);
1411 list_add_tail(&request->list, &dev_priv->mm.request_list);
1412
Eric Anholtce44b0e2008-11-06 16:00:31 -08001413 /* Associate any objects on the flushing list matching the write
1414 * domain we're flushing with our flush.
1415 */
1416 if (flush_domains != 0) {
1417 struct drm_i915_gem_object *obj_priv, *next;
1418
1419 list_for_each_entry_safe(obj_priv, next,
1420 &dev_priv->mm.flushing_list, list) {
1421 struct drm_gem_object *obj = obj_priv->obj;
1422
1423 if ((obj->write_domain & flush_domains) ==
1424 obj->write_domain) {
1425 obj->write_domain = 0;
1426 i915_gem_object_move_to_active(obj, seqno);
1427 }
1428 }
1429
1430 }
1431
Keith Packard6dbe2772008-10-14 21:41:13 -07001432 if (was_empty && !dev_priv->mm.suspended)
Eric Anholt673a3942008-07-30 12:06:12 -07001433 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1434 return seqno;
1435}
1436
1437/**
1438 * Command execution barrier
1439 *
1440 * Ensures that all commands in the ring are finished
1441 * before signalling the CPU
1442 */
Eric Anholt3043c602008-10-02 12:24:47 -07001443static uint32_t
Eric Anholt673a3942008-07-30 12:06:12 -07001444i915_retire_commands(struct drm_device *dev)
1445{
1446 drm_i915_private_t *dev_priv = dev->dev_private;
1447 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1448 uint32_t flush_domains = 0;
1449 RING_LOCALS;
1450
1451 /* The sampler always gets flushed on i965 (sigh) */
1452 if (IS_I965G(dev))
1453 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1454 BEGIN_LP_RING(2);
1455 OUT_RING(cmd);
1456 OUT_RING(0); /* noop */
1457 ADVANCE_LP_RING();
1458 return flush_domains;
1459}
1460
1461/**
1462 * Moves buffers associated only with the given active seqno from the active
1463 * to inactive list, potentially freeing them.
1464 */
1465static void
1466i915_gem_retire_request(struct drm_device *dev,
1467 struct drm_i915_gem_request *request)
1468{
1469 drm_i915_private_t *dev_priv = dev->dev_private;
1470
1471 /* Move any buffers on the active list that are no longer referenced
1472 * by the ringbuffer to the flushing/inactive lists as appropriate.
1473 */
Carl Worth5e118f42009-03-20 11:54:25 -07001474 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001475 while (!list_empty(&dev_priv->mm.active_list)) {
1476 struct drm_gem_object *obj;
1477 struct drm_i915_gem_object *obj_priv;
1478
1479 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1480 struct drm_i915_gem_object,
1481 list);
1482 obj = obj_priv->obj;
1483
1484 /* If the seqno being retired doesn't match the oldest in the
1485 * list, then the oldest in the list must still be newer than
1486 * this seqno.
1487 */
1488 if (obj_priv->last_rendering_seqno != request->seqno)
Carl Worth5e118f42009-03-20 11:54:25 -07001489 goto out;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001490
Eric Anholt673a3942008-07-30 12:06:12 -07001491#if WATCH_LRU
1492 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1493 __func__, request->seqno, obj);
1494#endif
1495
Eric Anholtce44b0e2008-11-06 16:00:31 -08001496 if (obj->write_domain != 0)
1497 i915_gem_object_move_to_flushing(obj);
1498 else
Eric Anholt673a3942008-07-30 12:06:12 -07001499 i915_gem_object_move_to_inactive(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001500 }
Carl Worth5e118f42009-03-20 11:54:25 -07001501out:
1502 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07001503}
1504
1505/**
1506 * Returns true if seq1 is later than seq2.
1507 */
1508static int
1509i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1510{
1511 return (int32_t)(seq1 - seq2) >= 0;
1512}
1513
1514uint32_t
1515i915_get_gem_seqno(struct drm_device *dev)
1516{
1517 drm_i915_private_t *dev_priv = dev->dev_private;
1518
1519 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1520}
1521
1522/**
1523 * This function clears the request list as sequence numbers are passed.
1524 */
1525void
1526i915_gem_retire_requests(struct drm_device *dev)
1527{
1528 drm_i915_private_t *dev_priv = dev->dev_private;
1529 uint32_t seqno;
1530
Karsten Wiese6c0594a2009-02-23 15:07:57 +01001531 if (!dev_priv->hw_status_page)
1532 return;
1533
Eric Anholt673a3942008-07-30 12:06:12 -07001534 seqno = i915_get_gem_seqno(dev);
1535
1536 while (!list_empty(&dev_priv->mm.request_list)) {
1537 struct drm_i915_gem_request *request;
1538 uint32_t retiring_seqno;
1539
1540 request = list_first_entry(&dev_priv->mm.request_list,
1541 struct drm_i915_gem_request,
1542 list);
1543 retiring_seqno = request->seqno;
1544
1545 if (i915_seqno_passed(seqno, retiring_seqno) ||
1546 dev_priv->mm.wedged) {
1547 i915_gem_retire_request(dev, request);
1548
1549 list_del(&request->list);
1550 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
1551 } else
1552 break;
1553 }
1554}
1555
1556void
1557i915_gem_retire_work_handler(struct work_struct *work)
1558{
1559 drm_i915_private_t *dev_priv;
1560 struct drm_device *dev;
1561
1562 dev_priv = container_of(work, drm_i915_private_t,
1563 mm.retire_work.work);
1564 dev = dev_priv->dev;
1565
1566 mutex_lock(&dev->struct_mutex);
1567 i915_gem_retire_requests(dev);
Keith Packard6dbe2772008-10-14 21:41:13 -07001568 if (!dev_priv->mm.suspended &&
1569 !list_empty(&dev_priv->mm.request_list))
Eric Anholt673a3942008-07-30 12:06:12 -07001570 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
1571 mutex_unlock(&dev->struct_mutex);
1572}
1573
1574/**
1575 * Waits for a sequence number to be signaled, and cleans up the
1576 * request and object lists appropriately for that event.
1577 */
Eric Anholt3043c602008-10-02 12:24:47 -07001578static int
Eric Anholt673a3942008-07-30 12:06:12 -07001579i915_wait_request(struct drm_device *dev, uint32_t seqno)
1580{
1581 drm_i915_private_t *dev_priv = dev->dev_private;
1582 int ret = 0;
1583
1584 BUG_ON(seqno == 0);
1585
1586 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
1587 dev_priv->mm.waiting_gem_seqno = seqno;
1588 i915_user_irq_get(dev);
1589 ret = wait_event_interruptible(dev_priv->irq_queue,
1590 i915_seqno_passed(i915_get_gem_seqno(dev),
1591 seqno) ||
1592 dev_priv->mm.wedged);
1593 i915_user_irq_put(dev);
1594 dev_priv->mm.waiting_gem_seqno = 0;
1595 }
1596 if (dev_priv->mm.wedged)
1597 ret = -EIO;
1598
1599 if (ret && ret != -ERESTARTSYS)
1600 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1601 __func__, ret, seqno, i915_get_gem_seqno(dev));
1602
1603 /* Directly dispatch request retiring. While we have the work queue
1604 * to handle this, the waiter on a request often wants an associated
1605 * buffer to have made it to the inactive list, and we would need
1606 * a separate wait queue to handle that.
1607 */
1608 if (ret == 0)
1609 i915_gem_retire_requests(dev);
1610
1611 return ret;
1612}
1613
1614static void
1615i915_gem_flush(struct drm_device *dev,
1616 uint32_t invalidate_domains,
1617 uint32_t flush_domains)
1618{
1619 drm_i915_private_t *dev_priv = dev->dev_private;
1620 uint32_t cmd;
1621 RING_LOCALS;
1622
1623#if WATCH_EXEC
1624 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1625 invalidate_domains, flush_domains);
1626#endif
1627
1628 if (flush_domains & I915_GEM_DOMAIN_CPU)
1629 drm_agp_chipset_flush(dev);
1630
1631 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
1632 I915_GEM_DOMAIN_GTT)) {
1633 /*
1634 * read/write caches:
1635 *
1636 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1637 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1638 * also flushed at 2d versus 3d pipeline switches.
1639 *
1640 * read-only caches:
1641 *
1642 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1643 * MI_READ_FLUSH is set, and is always flushed on 965.
1644 *
1645 * I915_GEM_DOMAIN_COMMAND may not exist?
1646 *
1647 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1648 * invalidated when MI_EXE_FLUSH is set.
1649 *
1650 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1651 * invalidated with every MI_FLUSH.
1652 *
1653 * TLBs:
1654 *
1655 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1656 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1657 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1658 * are flushed at any MI_FLUSH.
1659 */
1660
1661 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1662 if ((invalidate_domains|flush_domains) &
1663 I915_GEM_DOMAIN_RENDER)
1664 cmd &= ~MI_NO_WRITE_FLUSH;
1665 if (!IS_I965G(dev)) {
1666 /*
1667 * On the 965, the sampler cache always gets flushed
1668 * and this bit is reserved.
1669 */
1670 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1671 cmd |= MI_READ_FLUSH;
1672 }
1673 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1674 cmd |= MI_EXE_FLUSH;
1675
1676#if WATCH_EXEC
1677 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1678#endif
1679 BEGIN_LP_RING(2);
1680 OUT_RING(cmd);
1681 OUT_RING(0); /* noop */
1682 ADVANCE_LP_RING();
1683 }
1684}
1685
1686/**
1687 * Ensures that all rendering to the object has completed and the object is
1688 * safe to unbind from the GTT or access from the CPU.
1689 */
1690static int
1691i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1692{
1693 struct drm_device *dev = obj->dev;
1694 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1695 int ret;
1696
Eric Anholte47c68e2008-11-14 13:35:19 -08001697 /* This function only exists to support waiting for existing rendering,
1698 * not for emitting required flushes.
Eric Anholt673a3942008-07-30 12:06:12 -07001699 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001700 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
Eric Anholt673a3942008-07-30 12:06:12 -07001701
1702 /* If there is rendering queued on the buffer being evicted, wait for
1703 * it.
1704 */
1705 if (obj_priv->active) {
1706#if WATCH_BUF
1707 DRM_INFO("%s: object %p wait for seqno %08x\n",
1708 __func__, obj, obj_priv->last_rendering_seqno);
1709#endif
1710 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1711 if (ret != 0)
1712 return ret;
1713 }
1714
1715 return 0;
1716}
1717
1718/**
1719 * Unbinds an object from the GTT aperture.
1720 */
Jesse Barnes0f973f22009-01-26 17:10:45 -08001721int
Eric Anholt673a3942008-07-30 12:06:12 -07001722i915_gem_object_unbind(struct drm_gem_object *obj)
1723{
1724 struct drm_device *dev = obj->dev;
1725 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001726 loff_t offset;
Eric Anholt673a3942008-07-30 12:06:12 -07001727 int ret = 0;
1728
1729#if WATCH_BUF
1730 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1731 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1732#endif
1733 if (obj_priv->gtt_space == NULL)
1734 return 0;
1735
1736 if (obj_priv->pin_count != 0) {
1737 DRM_ERROR("Attempting to unbind pinned buffer\n");
1738 return -EINVAL;
1739 }
1740
Eric Anholt673a3942008-07-30 12:06:12 -07001741 /* Move the object to the CPU domain to ensure that
1742 * any possible CPU writes while it's not in the GTT
1743 * are flushed when we go to remap it. This will
1744 * also ensure that all pending GPU writes are finished
1745 * before we unbind.
1746 */
Eric Anholte47c68e2008-11-14 13:35:19 -08001747 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07001748 if (ret) {
Eric Anholte47c68e2008-11-14 13:35:19 -08001749 if (ret != -ERESTARTSYS)
1750 DRM_ERROR("set_domain failed: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07001751 return ret;
1752 }
1753
1754 if (obj_priv->agp_mem != NULL) {
1755 drm_unbind_agp(obj_priv->agp_mem);
1756 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1757 obj_priv->agp_mem = NULL;
1758 }
1759
1760 BUG_ON(obj_priv->active);
1761
Jesse Barnesde151cf2008-11-12 10:03:55 -08001762 /* blow away mappings if mapped through GTT */
1763 offset = ((loff_t) obj->map_list.hash.key) << PAGE_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08001764 if (dev->dev_mapping)
1765 unmap_mapping_range(dev->dev_mapping, offset, obj->size, 1);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001766
1767 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1768 i915_gem_clear_fence_reg(obj);
1769
Eric Anholt856fa192009-03-19 14:10:50 -07001770 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001771
1772 if (obj_priv->gtt_space) {
1773 atomic_dec(&dev->gtt_count);
1774 atomic_sub(obj->size, &dev->gtt_memory);
1775
1776 drm_mm_put_block(obj_priv->gtt_space);
1777 obj_priv->gtt_space = NULL;
1778 }
1779
1780 /* Remove ourselves from the LRU list if present. */
1781 if (!list_empty(&obj_priv->list))
1782 list_del_init(&obj_priv->list);
1783
1784 return 0;
1785}
1786
1787static int
1788i915_gem_evict_something(struct drm_device *dev)
1789{
1790 drm_i915_private_t *dev_priv = dev->dev_private;
1791 struct drm_gem_object *obj;
1792 struct drm_i915_gem_object *obj_priv;
1793 int ret = 0;
1794
1795 for (;;) {
1796 /* If there's an inactive buffer available now, grab it
1797 * and be done.
1798 */
1799 if (!list_empty(&dev_priv->mm.inactive_list)) {
1800 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1801 struct drm_i915_gem_object,
1802 list);
1803 obj = obj_priv->obj;
1804 BUG_ON(obj_priv->pin_count != 0);
1805#if WATCH_LRU
1806 DRM_INFO("%s: evicting %p\n", __func__, obj);
1807#endif
1808 BUG_ON(obj_priv->active);
1809
1810 /* Wait on the rendering and unbind the buffer. */
1811 ret = i915_gem_object_unbind(obj);
1812 break;
1813 }
1814
1815 /* If we didn't get anything, but the ring is still processing
1816 * things, wait for one of those things to finish and hopefully
1817 * leave us a buffer to evict.
1818 */
1819 if (!list_empty(&dev_priv->mm.request_list)) {
1820 struct drm_i915_gem_request *request;
1821
1822 request = list_first_entry(&dev_priv->mm.request_list,
1823 struct drm_i915_gem_request,
1824 list);
1825
1826 ret = i915_wait_request(dev, request->seqno);
1827 if (ret)
1828 break;
1829
1830 /* if waiting caused an object to become inactive,
1831 * then loop around and wait for it. Otherwise, we
1832 * assume that waiting freed and unbound something,
1833 * so there should now be some space in the GTT
1834 */
1835 if (!list_empty(&dev_priv->mm.inactive_list))
1836 continue;
1837 break;
1838 }
1839
1840 /* If we didn't have anything on the request list but there
1841 * are buffers awaiting a flush, emit one and try again.
1842 * When we wait on it, those buffers waiting for that flush
1843 * will get moved to inactive.
1844 */
1845 if (!list_empty(&dev_priv->mm.flushing_list)) {
1846 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1847 struct drm_i915_gem_object,
1848 list);
1849 obj = obj_priv->obj;
1850
1851 i915_gem_flush(dev,
1852 obj->write_domain,
1853 obj->write_domain);
1854 i915_add_request(dev, obj->write_domain);
1855
1856 obj = NULL;
1857 continue;
1858 }
1859
1860 DRM_ERROR("inactive empty %d request empty %d "
1861 "flushing empty %d\n",
1862 list_empty(&dev_priv->mm.inactive_list),
1863 list_empty(&dev_priv->mm.request_list),
1864 list_empty(&dev_priv->mm.flushing_list));
1865 /* If we didn't do any of the above, there's nothing to be done
1866 * and we just can't fit it in.
1867 */
1868 return -ENOMEM;
1869 }
1870 return ret;
1871}
1872
1873static int
Keith Packardac94a962008-11-20 23:30:27 -08001874i915_gem_evict_everything(struct drm_device *dev)
1875{
1876 int ret;
1877
1878 for (;;) {
1879 ret = i915_gem_evict_something(dev);
1880 if (ret != 0)
1881 break;
1882 }
Owain Ainsworth15c35332008-12-06 20:42:20 -08001883 if (ret == -ENOMEM)
1884 return 0;
Keith Packardac94a962008-11-20 23:30:27 -08001885 return ret;
1886}
1887
Ben Gamari6911a9b2009-04-02 11:24:54 -07001888int
Eric Anholt856fa192009-03-19 14:10:50 -07001889i915_gem_object_get_pages(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07001890{
1891 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1892 int page_count, i;
1893 struct address_space *mapping;
1894 struct inode *inode;
1895 struct page *page;
1896 int ret;
1897
Eric Anholt856fa192009-03-19 14:10:50 -07001898 if (obj_priv->pages_refcount++ != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07001899 return 0;
1900
1901 /* Get the list of pages out of our struct file. They'll be pinned
1902 * at this point until we release them.
1903 */
1904 page_count = obj->size / PAGE_SIZE;
Eric Anholt856fa192009-03-19 14:10:50 -07001905 BUG_ON(obj_priv->pages != NULL);
1906 obj_priv->pages = drm_calloc(page_count, sizeof(struct page *),
1907 DRM_MEM_DRIVER);
1908 if (obj_priv->pages == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07001909 DRM_ERROR("Faled to allocate page list\n");
Eric Anholt856fa192009-03-19 14:10:50 -07001910 obj_priv->pages_refcount--;
Eric Anholt673a3942008-07-30 12:06:12 -07001911 return -ENOMEM;
1912 }
1913
1914 inode = obj->filp->f_path.dentry->d_inode;
1915 mapping = inode->i_mapping;
1916 for (i = 0; i < page_count; i++) {
1917 page = read_mapping_page(mapping, i, NULL);
1918 if (IS_ERR(page)) {
1919 ret = PTR_ERR(page);
1920 DRM_ERROR("read_mapping_page failed: %d\n", ret);
Eric Anholt856fa192009-03-19 14:10:50 -07001921 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07001922 return ret;
1923 }
Eric Anholt856fa192009-03-19 14:10:50 -07001924 obj_priv->pages[i] = page;
Eric Anholt673a3942008-07-30 12:06:12 -07001925 }
1926 return 0;
1927}
1928
Jesse Barnesde151cf2008-11-12 10:03:55 -08001929static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
1930{
1931 struct drm_gem_object *obj = reg->obj;
1932 struct drm_device *dev = obj->dev;
1933 drm_i915_private_t *dev_priv = dev->dev_private;
1934 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1935 int regnum = obj_priv->fence_reg;
1936 uint64_t val;
1937
1938 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
1939 0xfffff000) << 32;
1940 val |= obj_priv->gtt_offset & 0xfffff000;
1941 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
1942 if (obj_priv->tiling_mode == I915_TILING_Y)
1943 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
1944 val |= I965_FENCE_REG_VALID;
1945
1946 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
1947}
1948
1949static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
1950{
1951 struct drm_gem_object *obj = reg->obj;
1952 struct drm_device *dev = obj->dev;
1953 drm_i915_private_t *dev_priv = dev->dev_private;
1954 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1955 int regnum = obj_priv->fence_reg;
Jesse Barnes0f973f22009-01-26 17:10:45 -08001956 int tile_width;
Eric Anholtdc529a42009-03-10 22:34:49 -07001957 uint32_t fence_reg, val;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001958 uint32_t pitch_val;
1959
1960 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
1961 (obj_priv->gtt_offset & (obj->size - 1))) {
Linus Torvaldsf06da262009-02-09 08:57:29 -08001962 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08001963 __func__, obj_priv->gtt_offset, obj->size);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001964 return;
1965 }
1966
Jesse Barnes0f973f22009-01-26 17:10:45 -08001967 if (obj_priv->tiling_mode == I915_TILING_Y &&
1968 HAS_128_BYTE_Y_TILING(dev))
1969 tile_width = 128;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001970 else
Jesse Barnes0f973f22009-01-26 17:10:45 -08001971 tile_width = 512;
1972
1973 /* Note: pitch better be a power of two tile widths */
1974 pitch_val = obj_priv->stride / tile_width;
1975 pitch_val = ffs(pitch_val) - 1;
Jesse Barnesde151cf2008-11-12 10:03:55 -08001976
1977 val = obj_priv->gtt_offset;
1978 if (obj_priv->tiling_mode == I915_TILING_Y)
1979 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
1980 val |= I915_FENCE_SIZE_BITS(obj->size);
1981 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
1982 val |= I830_FENCE_REG_VALID;
1983
Eric Anholtdc529a42009-03-10 22:34:49 -07001984 if (regnum < 8)
1985 fence_reg = FENCE_REG_830_0 + (regnum * 4);
1986 else
1987 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
1988 I915_WRITE(fence_reg, val);
Jesse Barnesde151cf2008-11-12 10:03:55 -08001989}
1990
1991static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
1992{
1993 struct drm_gem_object *obj = reg->obj;
1994 struct drm_device *dev = obj->dev;
1995 drm_i915_private_t *dev_priv = dev->dev_private;
1996 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1997 int regnum = obj_priv->fence_reg;
1998 uint32_t val;
1999 uint32_t pitch_val;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002000 uint32_t fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002001
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002002 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
Jesse Barnesde151cf2008-11-12 10:03:55 -08002003 (obj_priv->gtt_offset & (obj->size - 1))) {
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002004 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
Jesse Barnes0f973f22009-01-26 17:10:45 -08002005 __func__, obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002006 return;
2007 }
2008
2009 pitch_val = (obj_priv->stride / 128) - 1;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002010 WARN_ON(pitch_val & ~0x0000000f);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002011 val = obj_priv->gtt_offset;
2012 if (obj_priv->tiling_mode == I915_TILING_Y)
2013 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002014 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2015 WARN_ON(fence_size_bits & ~0x00000f00);
2016 val |= fence_size_bits;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002017 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2018 val |= I830_FENCE_REG_VALID;
2019
2020 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2021
2022}
2023
2024/**
2025 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2026 * @obj: object to map through a fence reg
Jesse Barnes0f973f22009-01-26 17:10:45 -08002027 * @write: object is about to be written
Jesse Barnesde151cf2008-11-12 10:03:55 -08002028 *
2029 * When mapping objects through the GTT, userspace wants to be able to write
2030 * to them without having to worry about swizzling if the object is tiled.
2031 *
2032 * This function walks the fence regs looking for a free one for @obj,
2033 * stealing one if it can't find any.
2034 *
2035 * It then sets up the reg based on the object's properties: address, pitch
2036 * and tiling format.
2037 */
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002038static int
Jesse Barnes0f973f22009-01-26 17:10:45 -08002039i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002040{
2041 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002042 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002043 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2044 struct drm_i915_fence_reg *reg = NULL;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002045 struct drm_i915_gem_object *old_obj_priv = NULL;
2046 int i, ret, avail;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002047
2048 switch (obj_priv->tiling_mode) {
2049 case I915_TILING_NONE:
2050 WARN(1, "allocating a fence for non-tiled object?\n");
2051 break;
2052 case I915_TILING_X:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002053 if (!obj_priv->stride)
2054 return -EINVAL;
2055 WARN((obj_priv->stride & (512 - 1)),
2056 "object 0x%08x is X tiled but has non-512B pitch\n",
2057 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002058 break;
2059 case I915_TILING_Y:
Jesse Barnes0f973f22009-01-26 17:10:45 -08002060 if (!obj_priv->stride)
2061 return -EINVAL;
2062 WARN((obj_priv->stride & (128 - 1)),
2063 "object 0x%08x is Y tiled but has non-128B pitch\n",
2064 obj_priv->gtt_offset);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002065 break;
2066 }
2067
2068 /* First try to find a free reg */
Chris Wilson9b2412f2009-02-11 14:26:44 +00002069try_again:
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002070 avail = 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002071 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2072 reg = &dev_priv->fence_regs[i];
2073 if (!reg->obj)
2074 break;
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002075
2076 old_obj_priv = reg->obj->driver_private;
2077 if (!old_obj_priv->pin_count)
2078 avail++;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002079 }
2080
2081 /* None available, try to steal one or wait for a user to finish */
2082 if (i == dev_priv->num_fence_regs) {
Chris Wilsond7619c42009-02-11 14:26:47 +00002083 uint32_t seqno = dev_priv->mm.next_gem_seqno;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002084 loff_t offset;
2085
Chris Wilsonfc7170b2009-02-11 14:26:46 +00002086 if (avail == 0)
2087 return -ENOMEM;
2088
Jesse Barnesde151cf2008-11-12 10:03:55 -08002089 for (i = dev_priv->fence_reg_start;
2090 i < dev_priv->num_fence_regs; i++) {
Chris Wilsond7619c42009-02-11 14:26:47 +00002091 uint32_t this_seqno;
2092
Jesse Barnesde151cf2008-11-12 10:03:55 -08002093 reg = &dev_priv->fence_regs[i];
2094 old_obj_priv = reg->obj->driver_private;
Chris Wilsond7619c42009-02-11 14:26:47 +00002095
2096 if (old_obj_priv->pin_count)
2097 continue;
2098
2099 /* i915 uses fences for GPU access to tiled buffers */
2100 if (IS_I965G(dev) || !old_obj_priv->active)
Jesse Barnesde151cf2008-11-12 10:03:55 -08002101 break;
Chris Wilsond7619c42009-02-11 14:26:47 +00002102
2103 /* find the seqno of the first available fence */
2104 this_seqno = old_obj_priv->last_rendering_seqno;
2105 if (this_seqno != 0 &&
2106 reg->obj->write_domain == 0 &&
2107 i915_seqno_passed(seqno, this_seqno))
2108 seqno = this_seqno;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002109 }
2110
2111 /*
2112 * Now things get ugly... we have to wait for one of the
2113 * objects to finish before trying again.
2114 */
2115 if (i == dev_priv->num_fence_regs) {
Chris Wilsond7619c42009-02-11 14:26:47 +00002116 if (seqno == dev_priv->mm.next_gem_seqno) {
2117 i915_gem_flush(dev,
2118 I915_GEM_GPU_DOMAINS,
2119 I915_GEM_GPU_DOMAINS);
2120 seqno = i915_add_request(dev,
2121 I915_GEM_GPU_DOMAINS);
2122 if (seqno == 0)
2123 return -ENOMEM;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002124 }
Chris Wilsond7619c42009-02-11 14:26:47 +00002125
2126 ret = i915_wait_request(dev, seqno);
2127 if (ret)
2128 return ret;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002129 goto try_again;
2130 }
2131
Chris Wilsond7619c42009-02-11 14:26:47 +00002132 BUG_ON(old_obj_priv->active ||
2133 (reg->obj->write_domain & I915_GEM_GPU_DOMAINS));
2134
Jesse Barnesde151cf2008-11-12 10:03:55 -08002135 /*
2136 * Zap this virtual mapping so we can set up a fence again
2137 * for this object next time we need it.
2138 */
2139 offset = ((loff_t) reg->obj->map_list.hash.key) << PAGE_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08002140 if (dev->dev_mapping)
2141 unmap_mapping_range(dev->dev_mapping, offset,
2142 reg->obj->size, 1);
Jesse Barnesde151cf2008-11-12 10:03:55 -08002143 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
2144 }
2145
2146 obj_priv->fence_reg = i;
2147 reg->obj = obj;
2148
2149 if (IS_I965G(dev))
2150 i965_write_fence_reg(reg);
2151 else if (IS_I9XX(dev))
2152 i915_write_fence_reg(reg);
2153 else
2154 i830_write_fence_reg(reg);
Eric Anholtd9ddcb92009-01-27 10:33:49 -08002155
2156 return 0;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002157}
2158
2159/**
2160 * i915_gem_clear_fence_reg - clear out fence register info
2161 * @obj: object to clear
2162 *
2163 * Zeroes out the fence register itself and clears out the associated
2164 * data structures in dev_priv and obj_priv.
2165 */
2166static void
2167i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2168{
2169 struct drm_device *dev = obj->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08002170 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnesde151cf2008-11-12 10:03:55 -08002171 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2172
2173 if (IS_I965G(dev))
2174 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
Eric Anholtdc529a42009-03-10 22:34:49 -07002175 else {
2176 uint32_t fence_reg;
2177
2178 if (obj_priv->fence_reg < 8)
2179 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2180 else
2181 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2182 8) * 4;
2183
2184 I915_WRITE(fence_reg, 0);
2185 }
Jesse Barnesde151cf2008-11-12 10:03:55 -08002186
2187 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2188 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2189}
2190
Eric Anholt673a3942008-07-30 12:06:12 -07002191/**
2192 * Finds free space in the GTT aperture and binds the object there.
2193 */
2194static int
2195i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2196{
2197 struct drm_device *dev = obj->dev;
2198 drm_i915_private_t *dev_priv = dev->dev_private;
2199 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2200 struct drm_mm_node *free_space;
2201 int page_count, ret;
2202
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08002203 if (dev_priv->mm.suspended)
2204 return -EBUSY;
Eric Anholt673a3942008-07-30 12:06:12 -07002205 if (alignment == 0)
Jesse Barnes0f973f22009-01-26 17:10:45 -08002206 alignment = i915_gem_get_gtt_alignment(obj);
Daniel Vetter8d7773a2009-03-29 14:09:41 +02002207 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
Eric Anholt673a3942008-07-30 12:06:12 -07002208 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2209 return -EINVAL;
2210 }
2211
2212 search_free:
2213 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2214 obj->size, alignment, 0);
2215 if (free_space != NULL) {
2216 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2217 alignment);
2218 if (obj_priv->gtt_space != NULL) {
2219 obj_priv->gtt_space->private = obj;
2220 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2221 }
2222 }
2223 if (obj_priv->gtt_space == NULL) {
Carl Worth5e118f42009-03-20 11:54:25 -07002224 bool lists_empty;
2225
Eric Anholt673a3942008-07-30 12:06:12 -07002226 /* If the gtt is empty and we're still having trouble
2227 * fitting our object in, we're out of memory.
2228 */
2229#if WATCH_LRU
2230 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2231#endif
Carl Worth5e118f42009-03-20 11:54:25 -07002232 spin_lock(&dev_priv->mm.active_list_lock);
2233 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2234 list_empty(&dev_priv->mm.flushing_list) &&
2235 list_empty(&dev_priv->mm.active_list));
2236 spin_unlock(&dev_priv->mm.active_list_lock);
2237 if (lists_empty) {
Eric Anholt673a3942008-07-30 12:06:12 -07002238 DRM_ERROR("GTT full, but LRU list empty\n");
2239 return -ENOMEM;
2240 }
2241
2242 ret = i915_gem_evict_something(dev);
2243 if (ret != 0) {
Keith Packardac94a962008-11-20 23:30:27 -08002244 if (ret != -ERESTARTSYS)
2245 DRM_ERROR("Failed to evict a buffer %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07002246 return ret;
2247 }
2248 goto search_free;
2249 }
2250
2251#if WATCH_BUF
2252 DRM_INFO("Binding object of size %d at 0x%08x\n",
2253 obj->size, obj_priv->gtt_offset);
2254#endif
Eric Anholt856fa192009-03-19 14:10:50 -07002255 ret = i915_gem_object_get_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002256 if (ret) {
2257 drm_mm_put_block(obj_priv->gtt_space);
2258 obj_priv->gtt_space = NULL;
2259 return ret;
2260 }
2261
2262 page_count = obj->size / PAGE_SIZE;
2263 /* Create an AGP memory structure pointing at our pages, and bind it
2264 * into the GTT.
2265 */
2266 obj_priv->agp_mem = drm_agp_bind_pages(dev,
Eric Anholt856fa192009-03-19 14:10:50 -07002267 obj_priv->pages,
Eric Anholt673a3942008-07-30 12:06:12 -07002268 page_count,
Keith Packardba1eb1d2008-10-14 19:55:10 -07002269 obj_priv->gtt_offset,
2270 obj_priv->agp_type);
Eric Anholt673a3942008-07-30 12:06:12 -07002271 if (obj_priv->agp_mem == NULL) {
Eric Anholt856fa192009-03-19 14:10:50 -07002272 i915_gem_object_put_pages(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07002273 drm_mm_put_block(obj_priv->gtt_space);
2274 obj_priv->gtt_space = NULL;
2275 return -ENOMEM;
2276 }
2277 atomic_inc(&dev->gtt_count);
2278 atomic_add(obj->size, &dev->gtt_memory);
2279
2280 /* Assert that the object is not currently in any GPU domain. As it
2281 * wasn't in the GTT, there shouldn't be any way it could have been in
2282 * a GPU cache
2283 */
2284 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2285 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2286
2287 return 0;
2288}
2289
2290void
2291i915_gem_clflush_object(struct drm_gem_object *obj)
2292{
2293 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2294
2295 /* If we don't have a page list set up, then we're not pinned
2296 * to GPU, and we can ignore the cache flush because it'll happen
2297 * again at bind time.
2298 */
Eric Anholt856fa192009-03-19 14:10:50 -07002299 if (obj_priv->pages == NULL)
Eric Anholt673a3942008-07-30 12:06:12 -07002300 return;
2301
Eric Anholt856fa192009-03-19 14:10:50 -07002302 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002303}
2304
Eric Anholte47c68e2008-11-14 13:35:19 -08002305/** Flushes any GPU write domain for the object if it's dirty. */
2306static void
2307i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2308{
2309 struct drm_device *dev = obj->dev;
2310 uint32_t seqno;
2311
2312 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2313 return;
2314
2315 /* Queue the GPU write cache flushing we need. */
2316 i915_gem_flush(dev, 0, obj->write_domain);
2317 seqno = i915_add_request(dev, obj->write_domain);
2318 obj->write_domain = 0;
2319 i915_gem_object_move_to_active(obj, seqno);
2320}
2321
2322/** Flushes the GTT write domain for the object if it's dirty. */
2323static void
2324i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2325{
2326 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2327 return;
2328
2329 /* No actual flushing is required for the GTT write domain. Writes
2330 * to it immediately go to main memory as far as we know, so there's
2331 * no chipset flush. It also doesn't land in render cache.
2332 */
2333 obj->write_domain = 0;
2334}
2335
2336/** Flushes the CPU write domain for the object if it's dirty. */
2337static void
2338i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2339{
2340 struct drm_device *dev = obj->dev;
2341
2342 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2343 return;
2344
2345 i915_gem_clflush_object(obj);
2346 drm_agp_chipset_flush(dev);
2347 obj->write_domain = 0;
2348}
2349
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002350/**
2351 * Moves a single object to the GTT read, and possibly write domain.
2352 *
2353 * This function returns when the move is complete, including waiting on
2354 * flushes to occur.
2355 */
Jesse Barnes79e53942008-11-07 14:24:08 -08002356int
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002357i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2358{
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002359 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Eric Anholte47c68e2008-11-14 13:35:19 -08002360 int ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002361
Eric Anholt02354392008-11-26 13:58:13 -08002362 /* Not valid to be called on unbound objects. */
2363 if (obj_priv->gtt_space == NULL)
2364 return -EINVAL;
2365
Eric Anholte47c68e2008-11-14 13:35:19 -08002366 i915_gem_object_flush_gpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002367 /* Wait on any GPU rendering and flushing to occur. */
Eric Anholte47c68e2008-11-14 13:35:19 -08002368 ret = i915_gem_object_wait_rendering(obj);
2369 if (ret != 0)
2370 return ret;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002371
2372 /* If we're writing through the GTT domain, then CPU and GPU caches
2373 * will need to be invalidated at next use.
2374 */
2375 if (write)
Eric Anholte47c68e2008-11-14 13:35:19 -08002376 obj->read_domains &= I915_GEM_DOMAIN_GTT;
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002377
Eric Anholte47c68e2008-11-14 13:35:19 -08002378 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002379
2380 /* It should now be out of any other write domains, and we can update
2381 * the domain values for our changes.
2382 */
2383 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2384 obj->read_domains |= I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002385 if (write) {
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002386 obj->write_domain = I915_GEM_DOMAIN_GTT;
Eric Anholte47c68e2008-11-14 13:35:19 -08002387 obj_priv->dirty = 1;
2388 }
2389
2390 return 0;
2391}
2392
2393/**
2394 * Moves a single object to the CPU read, and possibly write domain.
2395 *
2396 * This function returns when the move is complete, including waiting on
2397 * flushes to occur.
2398 */
2399static int
2400i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2401{
Eric Anholte47c68e2008-11-14 13:35:19 -08002402 int ret;
2403
2404 i915_gem_object_flush_gpu_write_domain(obj);
2405 /* Wait on any GPU rendering and flushing to occur. */
2406 ret = i915_gem_object_wait_rendering(obj);
2407 if (ret != 0)
2408 return ret;
2409
2410 i915_gem_object_flush_gtt_write_domain(obj);
2411
2412 /* If we have a partially-valid cache of the object in the CPU,
2413 * finish invalidating it and free the per-page flags.
2414 */
2415 i915_gem_object_set_to_full_cpu_read_domain(obj);
2416
2417 /* Flush the CPU cache if it's still invalid. */
2418 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2419 i915_gem_clflush_object(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002420
2421 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2422 }
2423
2424 /* It should now be out of any other write domains, and we can update
2425 * the domain values for our changes.
2426 */
2427 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2428
2429 /* If we're writing through the CPU, then the GPU read domains will
2430 * need to be invalidated at next use.
2431 */
2432 if (write) {
2433 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2434 obj->write_domain = I915_GEM_DOMAIN_CPU;
2435 }
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002436
2437 return 0;
2438}
2439
Eric Anholt673a3942008-07-30 12:06:12 -07002440/*
2441 * Set the next domain for the specified object. This
2442 * may not actually perform the necessary flushing/invaliding though,
2443 * as that may want to be batched with other set_domain operations
2444 *
2445 * This is (we hope) the only really tricky part of gem. The goal
2446 * is fairly simple -- track which caches hold bits of the object
2447 * and make sure they remain coherent. A few concrete examples may
2448 * help to explain how it works. For shorthand, we use the notation
2449 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2450 * a pair of read and write domain masks.
2451 *
2452 * Case 1: the batch buffer
2453 *
2454 * 1. Allocated
2455 * 2. Written by CPU
2456 * 3. Mapped to GTT
2457 * 4. Read by GPU
2458 * 5. Unmapped from GTT
2459 * 6. Freed
2460 *
2461 * Let's take these a step at a time
2462 *
2463 * 1. Allocated
2464 * Pages allocated from the kernel may still have
2465 * cache contents, so we set them to (CPU, CPU) always.
2466 * 2. Written by CPU (using pwrite)
2467 * The pwrite function calls set_domain (CPU, CPU) and
2468 * this function does nothing (as nothing changes)
2469 * 3. Mapped by GTT
2470 * This function asserts that the object is not
2471 * currently in any GPU-based read or write domains
2472 * 4. Read by GPU
2473 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2474 * As write_domain is zero, this function adds in the
2475 * current read domains (CPU+COMMAND, 0).
2476 * flush_domains is set to CPU.
2477 * invalidate_domains is set to COMMAND
2478 * clflush is run to get data out of the CPU caches
2479 * then i915_dev_set_domain calls i915_gem_flush to
2480 * emit an MI_FLUSH and drm_agp_chipset_flush
2481 * 5. Unmapped from GTT
2482 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2483 * flush_domains and invalidate_domains end up both zero
2484 * so no flushing/invalidating happens
2485 * 6. Freed
2486 * yay, done
2487 *
2488 * Case 2: The shared render buffer
2489 *
2490 * 1. Allocated
2491 * 2. Mapped to GTT
2492 * 3. Read/written by GPU
2493 * 4. set_domain to (CPU,CPU)
2494 * 5. Read/written by CPU
2495 * 6. Read/written by GPU
2496 *
2497 * 1. Allocated
2498 * Same as last example, (CPU, CPU)
2499 * 2. Mapped to GTT
2500 * Nothing changes (assertions find that it is not in the GPU)
2501 * 3. Read/written by GPU
2502 * execbuffer calls set_domain (RENDER, RENDER)
2503 * flush_domains gets CPU
2504 * invalidate_domains gets GPU
2505 * clflush (obj)
2506 * MI_FLUSH and drm_agp_chipset_flush
2507 * 4. set_domain (CPU, CPU)
2508 * flush_domains gets GPU
2509 * invalidate_domains gets CPU
2510 * wait_rendering (obj) to make sure all drawing is complete.
2511 * This will include an MI_FLUSH to get the data from GPU
2512 * to memory
2513 * clflush (obj) to invalidate the CPU cache
2514 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2515 * 5. Read/written by CPU
2516 * cache lines are loaded and dirtied
2517 * 6. Read written by GPU
2518 * Same as last GPU access
2519 *
2520 * Case 3: The constant buffer
2521 *
2522 * 1. Allocated
2523 * 2. Written by CPU
2524 * 3. Read by GPU
2525 * 4. Updated (written) by CPU again
2526 * 5. Read by GPU
2527 *
2528 * 1. Allocated
2529 * (CPU, CPU)
2530 * 2. Written by CPU
2531 * (CPU, CPU)
2532 * 3. Read by GPU
2533 * (CPU+RENDER, 0)
2534 * flush_domains = CPU
2535 * invalidate_domains = RENDER
2536 * clflush (obj)
2537 * MI_FLUSH
2538 * drm_agp_chipset_flush
2539 * 4. Updated (written) by CPU again
2540 * (CPU, CPU)
2541 * flush_domains = 0 (no previous write domain)
2542 * invalidate_domains = 0 (no new read domains)
2543 * 5. Read by GPU
2544 * (CPU+RENDER, 0)
2545 * flush_domains = CPU
2546 * invalidate_domains = RENDER
2547 * clflush (obj)
2548 * MI_FLUSH
2549 * drm_agp_chipset_flush
2550 */
Keith Packardc0d90822008-11-20 23:11:08 -08002551static void
Eric Anholt8b0e3782009-02-19 14:40:50 -08002552i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
Eric Anholt673a3942008-07-30 12:06:12 -07002553{
2554 struct drm_device *dev = obj->dev;
2555 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2556 uint32_t invalidate_domains = 0;
2557 uint32_t flush_domains = 0;
Eric Anholte47c68e2008-11-14 13:35:19 -08002558
Eric Anholt8b0e3782009-02-19 14:40:50 -08002559 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2560 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07002561
2562#if WATCH_BUF
2563 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2564 __func__, obj,
Eric Anholt8b0e3782009-02-19 14:40:50 -08002565 obj->read_domains, obj->pending_read_domains,
2566 obj->write_domain, obj->pending_write_domain);
Eric Anholt673a3942008-07-30 12:06:12 -07002567#endif
2568 /*
2569 * If the object isn't moving to a new write domain,
2570 * let the object stay in multiple read domains
2571 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002572 if (obj->pending_write_domain == 0)
2573 obj->pending_read_domains |= obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07002574 else
2575 obj_priv->dirty = 1;
2576
2577 /*
2578 * Flush the current write domain if
2579 * the new read domains don't match. Invalidate
2580 * any read domains which differ from the old
2581 * write domain
2582 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002583 if (obj->write_domain &&
2584 obj->write_domain != obj->pending_read_domains) {
Eric Anholt673a3942008-07-30 12:06:12 -07002585 flush_domains |= obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08002586 invalidate_domains |=
2587 obj->pending_read_domains & ~obj->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07002588 }
2589 /*
2590 * Invalidate any read caches which may have
2591 * stale data. That is, any new read domains.
2592 */
Eric Anholt8b0e3782009-02-19 14:40:50 -08002593 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07002594 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2595#if WATCH_BUF
2596 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2597 __func__, flush_domains, invalidate_domains);
2598#endif
Eric Anholt673a3942008-07-30 12:06:12 -07002599 i915_gem_clflush_object(obj);
2600 }
2601
Eric Anholtefbeed92009-02-19 14:54:51 -08002602 /* The actual obj->write_domain will be updated with
2603 * pending_write_domain after we emit the accumulated flush for all
2604 * of our domain changes in execbuffers (which clears objects'
2605 * write_domains). So if we have a current write domain that we
2606 * aren't changing, set pending_write_domain to that.
2607 */
2608 if (flush_domains == 0 && obj->pending_write_domain == 0)
2609 obj->pending_write_domain = obj->write_domain;
Eric Anholt8b0e3782009-02-19 14:40:50 -08002610 obj->read_domains = obj->pending_read_domains;
Eric Anholt673a3942008-07-30 12:06:12 -07002611
2612 dev->invalidate_domains |= invalidate_domains;
2613 dev->flush_domains |= flush_domains;
2614#if WATCH_BUF
2615 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2616 __func__,
2617 obj->read_domains, obj->write_domain,
2618 dev->invalidate_domains, dev->flush_domains);
2619#endif
Eric Anholt673a3942008-07-30 12:06:12 -07002620}
2621
2622/**
Eric Anholte47c68e2008-11-14 13:35:19 -08002623 * Moves the object from a partially CPU read to a full one.
Eric Anholt673a3942008-07-30 12:06:12 -07002624 *
Eric Anholte47c68e2008-11-14 13:35:19 -08002625 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2626 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2627 */
2628static void
2629i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
2630{
Eric Anholte47c68e2008-11-14 13:35:19 -08002631 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2632
2633 if (!obj_priv->page_cpu_valid)
2634 return;
2635
2636 /* If we're partially in the CPU read domain, finish moving it in.
2637 */
2638 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
2639 int i;
2640
2641 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
2642 if (obj_priv->page_cpu_valid[i])
2643 continue;
Eric Anholt856fa192009-03-19 14:10:50 -07002644 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholte47c68e2008-11-14 13:35:19 -08002645 }
Eric Anholte47c68e2008-11-14 13:35:19 -08002646 }
2647
2648 /* Free the page_cpu_valid mappings which are now stale, whether
2649 * or not we've got I915_GEM_DOMAIN_CPU.
2650 */
2651 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
2652 DRM_MEM_DRIVER);
2653 obj_priv->page_cpu_valid = NULL;
2654}
2655
2656/**
2657 * Set the CPU read domain on a range of the object.
2658 *
2659 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2660 * not entirely valid. The page_cpu_valid member of the object flags which
2661 * pages have been flushed, and will be respected by
2662 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2663 * of the whole object.
2664 *
2665 * This function returns when the move is complete, including waiting on
2666 * flushes to occur.
Eric Anholt673a3942008-07-30 12:06:12 -07002667 */
2668static int
Eric Anholte47c68e2008-11-14 13:35:19 -08002669i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
2670 uint64_t offset, uint64_t size)
Eric Anholt673a3942008-07-30 12:06:12 -07002671{
2672 struct drm_i915_gem_object *obj_priv = obj->driver_private;
Eric Anholte47c68e2008-11-14 13:35:19 -08002673 int i, ret;
Eric Anholt673a3942008-07-30 12:06:12 -07002674
Eric Anholte47c68e2008-11-14 13:35:19 -08002675 if (offset == 0 && size == obj->size)
2676 return i915_gem_object_set_to_cpu_domain(obj, 0);
2677
2678 i915_gem_object_flush_gpu_write_domain(obj);
2679 /* Wait on any GPU rendering and flushing to occur. */
2680 ret = i915_gem_object_wait_rendering(obj);
2681 if (ret != 0)
2682 return ret;
2683 i915_gem_object_flush_gtt_write_domain(obj);
2684
2685 /* If we're already fully in the CPU read domain, we're done. */
2686 if (obj_priv->page_cpu_valid == NULL &&
2687 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
Eric Anholt673a3942008-07-30 12:06:12 -07002688 return 0;
2689
Eric Anholte47c68e2008-11-14 13:35:19 -08002690 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2691 * newly adding I915_GEM_DOMAIN_CPU
2692 */
Eric Anholt673a3942008-07-30 12:06:12 -07002693 if (obj_priv->page_cpu_valid == NULL) {
2694 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
2695 DRM_MEM_DRIVER);
Eric Anholte47c68e2008-11-14 13:35:19 -08002696 if (obj_priv->page_cpu_valid == NULL)
2697 return -ENOMEM;
2698 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
2699 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
Eric Anholt673a3942008-07-30 12:06:12 -07002700
2701 /* Flush the cache on any pages that are still invalid from the CPU's
2702 * perspective.
2703 */
Eric Anholte47c68e2008-11-14 13:35:19 -08002704 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
2705 i++) {
Eric Anholt673a3942008-07-30 12:06:12 -07002706 if (obj_priv->page_cpu_valid[i])
2707 continue;
2708
Eric Anholt856fa192009-03-19 14:10:50 -07002709 drm_clflush_pages(obj_priv->pages + i, 1);
Eric Anholt673a3942008-07-30 12:06:12 -07002710
2711 obj_priv->page_cpu_valid[i] = 1;
2712 }
2713
Eric Anholte47c68e2008-11-14 13:35:19 -08002714 /* It should now be out of any other write domains, and we can update
2715 * the domain values for our changes.
2716 */
2717 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2718
2719 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2720
Eric Anholt673a3942008-07-30 12:06:12 -07002721 return 0;
2722}
2723
2724/**
Eric Anholt673a3942008-07-30 12:06:12 -07002725 * Pin an object to the GTT and evaluate the relocations landing in it.
2726 */
2727static int
2728i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
2729 struct drm_file *file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002730 struct drm_i915_gem_exec_object *entry,
2731 struct drm_i915_gem_relocation_entry *relocs)
Eric Anholt673a3942008-07-30 12:06:12 -07002732{
2733 struct drm_device *dev = obj->dev;
Keith Packard0839ccb2008-10-30 19:38:48 -07002734 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07002735 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2736 int i, ret;
Keith Packard0839ccb2008-10-30 19:38:48 -07002737 void __iomem *reloc_page;
Eric Anholt673a3942008-07-30 12:06:12 -07002738
2739 /* Choose the GTT offset for our buffer and put it there. */
2740 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
2741 if (ret)
2742 return ret;
2743
2744 entry->offset = obj_priv->gtt_offset;
2745
Eric Anholt673a3942008-07-30 12:06:12 -07002746 /* Apply the relocations, using the GTT aperture to avoid cache
2747 * flushing requirements.
2748 */
2749 for (i = 0; i < entry->relocation_count; i++) {
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002750 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
Eric Anholt673a3942008-07-30 12:06:12 -07002751 struct drm_gem_object *target_obj;
2752 struct drm_i915_gem_object *target_obj_priv;
Eric Anholt3043c602008-10-02 12:24:47 -07002753 uint32_t reloc_val, reloc_offset;
2754 uint32_t __iomem *reloc_entry;
Eric Anholt673a3942008-07-30 12:06:12 -07002755
Eric Anholt673a3942008-07-30 12:06:12 -07002756 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002757 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07002758 if (target_obj == NULL) {
2759 i915_gem_object_unpin(obj);
2760 return -EBADF;
2761 }
2762 target_obj_priv = target_obj->driver_private;
2763
2764 /* The target buffer should have appeared before us in the
2765 * exec_object list, so it should have a GTT space bound by now.
2766 */
2767 if (target_obj_priv->gtt_space == NULL) {
2768 DRM_ERROR("No GTT space found for object %d\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002769 reloc->target_handle);
Eric Anholt673a3942008-07-30 12:06:12 -07002770 drm_gem_object_unreference(target_obj);
2771 i915_gem_object_unpin(obj);
2772 return -EINVAL;
2773 }
2774
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002775 if (reloc->offset > obj->size - 4) {
Eric Anholt673a3942008-07-30 12:06:12 -07002776 DRM_ERROR("Relocation beyond object bounds: "
2777 "obj %p target %d offset %d size %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002778 obj, reloc->target_handle,
2779 (int) reloc->offset, (int) obj->size);
Eric Anholt673a3942008-07-30 12:06:12 -07002780 drm_gem_object_unreference(target_obj);
2781 i915_gem_object_unpin(obj);
2782 return -EINVAL;
2783 }
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002784 if (reloc->offset & 3) {
Eric Anholt673a3942008-07-30 12:06:12 -07002785 DRM_ERROR("Relocation not 4-byte aligned: "
2786 "obj %p target %d offset %d.\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002787 obj, reloc->target_handle,
2788 (int) reloc->offset);
Eric Anholt673a3942008-07-30 12:06:12 -07002789 drm_gem_object_unreference(target_obj);
2790 i915_gem_object_unpin(obj);
2791 return -EINVAL;
2792 }
2793
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002794 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
2795 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
Eric Anholte47c68e2008-11-14 13:35:19 -08002796 DRM_ERROR("reloc with read/write CPU domains: "
2797 "obj %p target %d offset %d "
2798 "read %08x write %08x",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002799 obj, reloc->target_handle,
2800 (int) reloc->offset,
2801 reloc->read_domains,
2802 reloc->write_domain);
Chris Wilson491152b2009-02-11 14:26:32 +00002803 drm_gem_object_unreference(target_obj);
2804 i915_gem_object_unpin(obj);
Eric Anholte47c68e2008-11-14 13:35:19 -08002805 return -EINVAL;
2806 }
2807
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002808 if (reloc->write_domain && target_obj->pending_write_domain &&
2809 reloc->write_domain != target_obj->pending_write_domain) {
Eric Anholt673a3942008-07-30 12:06:12 -07002810 DRM_ERROR("Write domain conflict: "
2811 "obj %p target %d offset %d "
2812 "new %08x old %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002813 obj, reloc->target_handle,
2814 (int) reloc->offset,
2815 reloc->write_domain,
Eric Anholt673a3942008-07-30 12:06:12 -07002816 target_obj->pending_write_domain);
2817 drm_gem_object_unreference(target_obj);
2818 i915_gem_object_unpin(obj);
2819 return -EINVAL;
2820 }
2821
2822#if WATCH_RELOC
2823 DRM_INFO("%s: obj %p offset %08x target %d "
2824 "read %08x write %08x gtt %08x "
2825 "presumed %08x delta %08x\n",
2826 __func__,
2827 obj,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002828 (int) reloc->offset,
2829 (int) reloc->target_handle,
2830 (int) reloc->read_domains,
2831 (int) reloc->write_domain,
Eric Anholt673a3942008-07-30 12:06:12 -07002832 (int) target_obj_priv->gtt_offset,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002833 (int) reloc->presumed_offset,
2834 reloc->delta);
Eric Anholt673a3942008-07-30 12:06:12 -07002835#endif
2836
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002837 target_obj->pending_read_domains |= reloc->read_domains;
2838 target_obj->pending_write_domain |= reloc->write_domain;
Eric Anholt673a3942008-07-30 12:06:12 -07002839
2840 /* If the relocation already has the right value in it, no
2841 * more work needs to be done.
2842 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002843 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
Eric Anholt673a3942008-07-30 12:06:12 -07002844 drm_gem_object_unreference(target_obj);
2845 continue;
2846 }
2847
Eric Anholt2ef7eea2008-11-10 10:53:25 -08002848 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
2849 if (ret != 0) {
2850 drm_gem_object_unreference(target_obj);
2851 i915_gem_object_unpin(obj);
2852 return -EINVAL;
Eric Anholt673a3942008-07-30 12:06:12 -07002853 }
2854
2855 /* Map the page containing the relocation we're going to
2856 * perform.
2857 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002858 reloc_offset = obj_priv->gtt_offset + reloc->offset;
Keith Packard0839ccb2008-10-30 19:38:48 -07002859 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
2860 (reloc_offset &
2861 ~(PAGE_SIZE - 1)));
Eric Anholt3043c602008-10-02 12:24:47 -07002862 reloc_entry = (uint32_t __iomem *)(reloc_page +
Keith Packard0839ccb2008-10-30 19:38:48 -07002863 (reloc_offset & (PAGE_SIZE - 1)));
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002864 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
Eric Anholt673a3942008-07-30 12:06:12 -07002865
2866#if WATCH_BUF
2867 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002868 obj, (unsigned int) reloc->offset,
Eric Anholt673a3942008-07-30 12:06:12 -07002869 readl(reloc_entry), reloc_val);
2870#endif
2871 writel(reloc_val, reloc_entry);
Keith Packard0839ccb2008-10-30 19:38:48 -07002872 io_mapping_unmap_atomic(reloc_page);
Eric Anholt673a3942008-07-30 12:06:12 -07002873
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002874 /* The updated presumed offset for this entry will be
2875 * copied back out to the user.
Eric Anholt673a3942008-07-30 12:06:12 -07002876 */
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002877 reloc->presumed_offset = target_obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07002878
2879 drm_gem_object_unreference(target_obj);
2880 }
2881
Eric Anholt673a3942008-07-30 12:06:12 -07002882#if WATCH_BUF
2883 if (0)
2884 i915_gem_dump_object(obj, 128, __func__, ~0);
2885#endif
2886 return 0;
2887}
2888
2889/** Dispatch a batchbuffer to the ring
2890 */
2891static int
2892i915_dispatch_gem_execbuffer(struct drm_device *dev,
2893 struct drm_i915_gem_execbuffer *exec,
Eric Anholt201361a2009-03-11 12:30:04 -07002894 struct drm_clip_rect *cliprects,
Eric Anholt673a3942008-07-30 12:06:12 -07002895 uint64_t exec_offset)
2896{
2897 drm_i915_private_t *dev_priv = dev->dev_private;
Eric Anholt673a3942008-07-30 12:06:12 -07002898 int nbox = exec->num_cliprects;
2899 int i = 0, count;
2900 uint32_t exec_start, exec_len;
2901 RING_LOCALS;
2902
2903 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
2904 exec_len = (uint32_t) exec->batch_len;
2905
2906 if ((exec_start | exec_len) & 0x7) {
2907 DRM_ERROR("alignment\n");
2908 return -EINVAL;
2909 }
2910
2911 if (!exec_start)
2912 return -EINVAL;
2913
2914 count = nbox ? nbox : 1;
2915
2916 for (i = 0; i < count; i++) {
2917 if (i < nbox) {
Eric Anholt201361a2009-03-11 12:30:04 -07002918 int ret = i915_emit_box(dev, cliprects, i,
Eric Anholt673a3942008-07-30 12:06:12 -07002919 exec->DR1, exec->DR4);
2920 if (ret)
2921 return ret;
2922 }
2923
2924 if (IS_I830(dev) || IS_845G(dev)) {
2925 BEGIN_LP_RING(4);
2926 OUT_RING(MI_BATCH_BUFFER);
2927 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2928 OUT_RING(exec_start + exec_len - 4);
2929 OUT_RING(0);
2930 ADVANCE_LP_RING();
2931 } else {
2932 BEGIN_LP_RING(2);
2933 if (IS_I965G(dev)) {
2934 OUT_RING(MI_BATCH_BUFFER_START |
2935 (2 << 6) |
2936 MI_BATCH_NON_SECURE_I965);
2937 OUT_RING(exec_start);
2938 } else {
2939 OUT_RING(MI_BATCH_BUFFER_START |
2940 (2 << 6));
2941 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
2942 }
2943 ADVANCE_LP_RING();
2944 }
2945 }
2946
2947 /* XXX breadcrumb */
2948 return 0;
2949}
2950
2951/* Throttle our rendering by waiting until the ring has completed our requests
2952 * emitted over 20 msec ago.
2953 *
2954 * This should get us reasonable parallelism between CPU and GPU but also
2955 * relatively low latency when blocking on a particular request to finish.
2956 */
2957static int
2958i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
2959{
2960 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2961 int ret = 0;
2962 uint32_t seqno;
2963
2964 mutex_lock(&dev->struct_mutex);
2965 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
2966 i915_file_priv->mm.last_gem_throttle_seqno =
2967 i915_file_priv->mm.last_gem_seqno;
2968 if (seqno)
2969 ret = i915_wait_request(dev, seqno);
2970 mutex_unlock(&dev->struct_mutex);
2971 return ret;
2972}
2973
Eric Anholt40a5f0d2009-03-12 11:23:52 -07002974static int
2975i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
2976 uint32_t buffer_count,
2977 struct drm_i915_gem_relocation_entry **relocs)
2978{
2979 uint32_t reloc_count = 0, reloc_index = 0, i;
2980 int ret;
2981
2982 *relocs = NULL;
2983 for (i = 0; i < buffer_count; i++) {
2984 if (reloc_count + exec_list[i].relocation_count < reloc_count)
2985 return -EINVAL;
2986 reloc_count += exec_list[i].relocation_count;
2987 }
2988
2989 *relocs = drm_calloc(reloc_count, sizeof(**relocs), DRM_MEM_DRIVER);
2990 if (*relocs == NULL)
2991 return -ENOMEM;
2992
2993 for (i = 0; i < buffer_count; i++) {
2994 struct drm_i915_gem_relocation_entry __user *user_relocs;
2995
2996 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
2997
2998 ret = copy_from_user(&(*relocs)[reloc_index],
2999 user_relocs,
3000 exec_list[i].relocation_count *
3001 sizeof(**relocs));
3002 if (ret != 0) {
3003 drm_free(*relocs, reloc_count * sizeof(**relocs),
3004 DRM_MEM_DRIVER);
3005 *relocs = NULL;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003006 return -EFAULT;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003007 }
3008
3009 reloc_index += exec_list[i].relocation_count;
3010 }
3011
Florian Mickler2bc43b52009-04-06 22:55:41 +02003012 return 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003013}
3014
3015static int
3016i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3017 uint32_t buffer_count,
3018 struct drm_i915_gem_relocation_entry *relocs)
3019{
3020 uint32_t reloc_count = 0, i;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003021 int ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003022
3023 for (i = 0; i < buffer_count; i++) {
3024 struct drm_i915_gem_relocation_entry __user *user_relocs;
Florian Mickler2bc43b52009-04-06 22:55:41 +02003025 int unwritten;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003026
3027 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3028
Florian Mickler2bc43b52009-04-06 22:55:41 +02003029 unwritten = copy_to_user(user_relocs,
3030 &relocs[reloc_count],
3031 exec_list[i].relocation_count *
3032 sizeof(*relocs));
3033
3034 if (unwritten) {
3035 ret = -EFAULT;
3036 goto err;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003037 }
3038
3039 reloc_count += exec_list[i].relocation_count;
3040 }
3041
Florian Mickler2bc43b52009-04-06 22:55:41 +02003042err:
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003043 drm_free(relocs, reloc_count * sizeof(*relocs), DRM_MEM_DRIVER);
3044
3045 return ret;
3046}
3047
Eric Anholt673a3942008-07-30 12:06:12 -07003048int
3049i915_gem_execbuffer(struct drm_device *dev, void *data,
3050 struct drm_file *file_priv)
3051{
3052 drm_i915_private_t *dev_priv = dev->dev_private;
3053 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3054 struct drm_i915_gem_execbuffer *args = data;
3055 struct drm_i915_gem_exec_object *exec_list = NULL;
3056 struct drm_gem_object **object_list = NULL;
3057 struct drm_gem_object *batch_obj;
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003058 struct drm_i915_gem_object *obj_priv;
Eric Anholt201361a2009-03-11 12:30:04 -07003059 struct drm_clip_rect *cliprects = NULL;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003060 struct drm_i915_gem_relocation_entry *relocs;
3061 int ret, ret2, i, pinned = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003062 uint64_t exec_offset;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003063 uint32_t seqno, flush_domains, reloc_index;
Keith Packardac94a962008-11-20 23:30:27 -08003064 int pin_tries;
Eric Anholt673a3942008-07-30 12:06:12 -07003065
3066#if WATCH_EXEC
3067 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3068 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3069#endif
3070
Eric Anholt4f481ed2008-09-10 14:22:49 -07003071 if (args->buffer_count < 1) {
3072 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3073 return -EINVAL;
3074 }
Eric Anholt673a3942008-07-30 12:06:12 -07003075 /* Copy in the exec list from userland */
3076 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
3077 DRM_MEM_DRIVER);
3078 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
3079 DRM_MEM_DRIVER);
3080 if (exec_list == NULL || object_list == NULL) {
3081 DRM_ERROR("Failed to allocate exec or object list "
3082 "for %d buffers\n",
3083 args->buffer_count);
3084 ret = -ENOMEM;
3085 goto pre_mutex_err;
3086 }
3087 ret = copy_from_user(exec_list,
3088 (struct drm_i915_relocation_entry __user *)
3089 (uintptr_t) args->buffers_ptr,
3090 sizeof(*exec_list) * args->buffer_count);
3091 if (ret != 0) {
3092 DRM_ERROR("copy %d exec entries failed %d\n",
3093 args->buffer_count, ret);
3094 goto pre_mutex_err;
3095 }
3096
Eric Anholt201361a2009-03-11 12:30:04 -07003097 if (args->num_cliprects != 0) {
3098 cliprects = drm_calloc(args->num_cliprects, sizeof(*cliprects),
3099 DRM_MEM_DRIVER);
3100 if (cliprects == NULL)
3101 goto pre_mutex_err;
3102
3103 ret = copy_from_user(cliprects,
3104 (struct drm_clip_rect __user *)
3105 (uintptr_t) args->cliprects_ptr,
3106 sizeof(*cliprects) * args->num_cliprects);
3107 if (ret != 0) {
3108 DRM_ERROR("copy %d cliprects failed: %d\n",
3109 args->num_cliprects, ret);
3110 goto pre_mutex_err;
3111 }
3112 }
3113
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003114 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3115 &relocs);
3116 if (ret != 0)
3117 goto pre_mutex_err;
3118
Eric Anholt673a3942008-07-30 12:06:12 -07003119 mutex_lock(&dev->struct_mutex);
3120
3121 i915_verify_inactive(dev, __FILE__, __LINE__);
3122
3123 if (dev_priv->mm.wedged) {
3124 DRM_ERROR("Execbuf while wedged\n");
3125 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003126 ret = -EIO;
3127 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003128 }
3129
3130 if (dev_priv->mm.suspended) {
3131 DRM_ERROR("Execbuf while VT-switched.\n");
3132 mutex_unlock(&dev->struct_mutex);
Chris Wilsona198bc82009-02-06 16:55:20 +00003133 ret = -EBUSY;
3134 goto pre_mutex_err;
Eric Anholt673a3942008-07-30 12:06:12 -07003135 }
3136
Keith Packardac94a962008-11-20 23:30:27 -08003137 /* Look up object handles */
Eric Anholt673a3942008-07-30 12:06:12 -07003138 for (i = 0; i < args->buffer_count; i++) {
3139 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3140 exec_list[i].handle);
3141 if (object_list[i] == NULL) {
3142 DRM_ERROR("Invalid object handle %d at index %d\n",
3143 exec_list[i].handle, i);
3144 ret = -EBADF;
3145 goto err;
3146 }
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003147
3148 obj_priv = object_list[i]->driver_private;
3149 if (obj_priv->in_execbuffer) {
3150 DRM_ERROR("Object %p appears more than once in object list\n",
3151 object_list[i]);
3152 ret = -EBADF;
3153 goto err;
3154 }
3155 obj_priv->in_execbuffer = true;
Keith Packardac94a962008-11-20 23:30:27 -08003156 }
Eric Anholt673a3942008-07-30 12:06:12 -07003157
Keith Packardac94a962008-11-20 23:30:27 -08003158 /* Pin and relocate */
3159 for (pin_tries = 0; ; pin_tries++) {
3160 ret = 0;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003161 reloc_index = 0;
3162
Keith Packardac94a962008-11-20 23:30:27 -08003163 for (i = 0; i < args->buffer_count; i++) {
3164 object_list[i]->pending_read_domains = 0;
3165 object_list[i]->pending_write_domain = 0;
3166 ret = i915_gem_object_pin_and_relocate(object_list[i],
3167 file_priv,
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003168 &exec_list[i],
3169 &relocs[reloc_index]);
Keith Packardac94a962008-11-20 23:30:27 -08003170 if (ret)
3171 break;
3172 pinned = i + 1;
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003173 reloc_index += exec_list[i].relocation_count;
Keith Packardac94a962008-11-20 23:30:27 -08003174 }
3175 /* success */
3176 if (ret == 0)
3177 break;
3178
3179 /* error other than GTT full, or we've already tried again */
3180 if (ret != -ENOMEM || pin_tries >= 1) {
Eric Anholtf1acec92008-12-19 14:47:48 -08003181 if (ret != -ERESTARTSYS)
3182 DRM_ERROR("Failed to pin buffers %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07003183 goto err;
3184 }
Keith Packardac94a962008-11-20 23:30:27 -08003185
3186 /* unpin all of our buffers */
3187 for (i = 0; i < pinned; i++)
3188 i915_gem_object_unpin(object_list[i]);
Eric Anholtb1177632008-12-10 10:09:41 -08003189 pinned = 0;
Keith Packardac94a962008-11-20 23:30:27 -08003190
3191 /* evict everyone we can from the aperture */
3192 ret = i915_gem_evict_everything(dev);
3193 if (ret)
3194 goto err;
Eric Anholt673a3942008-07-30 12:06:12 -07003195 }
3196
3197 /* Set the pending read domains for the batch buffer to COMMAND */
3198 batch_obj = object_list[args->buffer_count-1];
3199 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
3200 batch_obj->pending_write_domain = 0;
3201
3202 i915_verify_inactive(dev, __FILE__, __LINE__);
3203
Keith Packard646f0f62008-11-20 23:23:03 -08003204 /* Zero the global flush/invalidate flags. These
3205 * will be modified as new domains are computed
3206 * for each object
3207 */
3208 dev->invalidate_domains = 0;
3209 dev->flush_domains = 0;
3210
Eric Anholt673a3942008-07-30 12:06:12 -07003211 for (i = 0; i < args->buffer_count; i++) {
3212 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003213
Keith Packard646f0f62008-11-20 23:23:03 -08003214 /* Compute new gpu domains and update invalidate/flush */
Eric Anholt8b0e3782009-02-19 14:40:50 -08003215 i915_gem_object_set_to_gpu_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003216 }
3217
3218 i915_verify_inactive(dev, __FILE__, __LINE__);
3219
Keith Packard646f0f62008-11-20 23:23:03 -08003220 if (dev->invalidate_domains | dev->flush_domains) {
3221#if WATCH_EXEC
3222 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3223 __func__,
3224 dev->invalidate_domains,
3225 dev->flush_domains);
3226#endif
3227 i915_gem_flush(dev,
3228 dev->invalidate_domains,
3229 dev->flush_domains);
3230 if (dev->flush_domains)
3231 (void)i915_add_request(dev, dev->flush_domains);
3232 }
Eric Anholt673a3942008-07-30 12:06:12 -07003233
Eric Anholtefbeed92009-02-19 14:54:51 -08003234 for (i = 0; i < args->buffer_count; i++) {
3235 struct drm_gem_object *obj = object_list[i];
3236
3237 obj->write_domain = obj->pending_write_domain;
3238 }
3239
Eric Anholt673a3942008-07-30 12:06:12 -07003240 i915_verify_inactive(dev, __FILE__, __LINE__);
3241
3242#if WATCH_COHERENCY
3243 for (i = 0; i < args->buffer_count; i++) {
3244 i915_gem_object_check_coherency(object_list[i],
3245 exec_list[i].handle);
3246 }
3247#endif
3248
3249 exec_offset = exec_list[args->buffer_count - 1].offset;
3250
3251#if WATCH_EXEC
Ben Gamari6911a9b2009-04-02 11:24:54 -07003252 i915_gem_dump_object(batch_obj,
Eric Anholt673a3942008-07-30 12:06:12 -07003253 args->batch_len,
3254 __func__,
3255 ~0);
3256#endif
3257
Eric Anholt673a3942008-07-30 12:06:12 -07003258 /* Exec the batchbuffer */
Eric Anholt201361a2009-03-11 12:30:04 -07003259 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
Eric Anholt673a3942008-07-30 12:06:12 -07003260 if (ret) {
3261 DRM_ERROR("dispatch failed %d\n", ret);
3262 goto err;
3263 }
3264
3265 /*
3266 * Ensure that the commands in the batch buffer are
3267 * finished before the interrupt fires
3268 */
3269 flush_domains = i915_retire_commands(dev);
3270
3271 i915_verify_inactive(dev, __FILE__, __LINE__);
3272
3273 /*
3274 * Get a seqno representing the execution of the current buffer,
3275 * which we can wait on. We would like to mitigate these interrupts,
3276 * likely by only creating seqnos occasionally (so that we have
3277 * *some* interrupts representing completion of buffers that we can
3278 * wait on when trying to clear up gtt space).
3279 */
3280 seqno = i915_add_request(dev, flush_domains);
3281 BUG_ON(seqno == 0);
3282 i915_file_priv->mm.last_gem_seqno = seqno;
3283 for (i = 0; i < args->buffer_count; i++) {
3284 struct drm_gem_object *obj = object_list[i];
Eric Anholt673a3942008-07-30 12:06:12 -07003285
Eric Anholtce44b0e2008-11-06 16:00:31 -08003286 i915_gem_object_move_to_active(obj, seqno);
Eric Anholt673a3942008-07-30 12:06:12 -07003287#if WATCH_LRU
3288 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3289#endif
3290 }
3291#if WATCH_LRU
3292 i915_dump_lru(dev, __func__);
3293#endif
3294
3295 i915_verify_inactive(dev, __FILE__, __LINE__);
3296
Eric Anholt673a3942008-07-30 12:06:12 -07003297err:
Julia Lawallaad87df2008-12-21 16:28:47 +01003298 for (i = 0; i < pinned; i++)
3299 i915_gem_object_unpin(object_list[i]);
Eric Anholt673a3942008-07-30 12:06:12 -07003300
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003301 for (i = 0; i < args->buffer_count; i++) {
3302 if (object_list[i]) {
3303 obj_priv = object_list[i]->driver_private;
3304 obj_priv->in_execbuffer = false;
3305 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003306 drm_gem_object_unreference(object_list[i]);
Kristian Høgsbergb70d11d2009-03-03 14:45:57 -05003307 }
Julia Lawallaad87df2008-12-21 16:28:47 +01003308
Eric Anholt673a3942008-07-30 12:06:12 -07003309 mutex_unlock(&dev->struct_mutex);
3310
Roland Dreiera35f2e22009-02-06 17:48:09 -08003311 if (!ret) {
3312 /* Copy the new buffer offsets back to the user's exec list. */
3313 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3314 (uintptr_t) args->buffers_ptr,
3315 exec_list,
3316 sizeof(*exec_list) * args->buffer_count);
Florian Mickler2bc43b52009-04-06 22:55:41 +02003317 if (ret) {
3318 ret = -EFAULT;
Roland Dreiera35f2e22009-02-06 17:48:09 -08003319 DRM_ERROR("failed to copy %d exec entries "
3320 "back to user (%d)\n",
3321 args->buffer_count, ret);
Florian Mickler2bc43b52009-04-06 22:55:41 +02003322 }
Roland Dreiera35f2e22009-02-06 17:48:09 -08003323 }
3324
Eric Anholt40a5f0d2009-03-12 11:23:52 -07003325 /* Copy the updated relocations out regardless of current error
3326 * state. Failure to update the relocs would mean that the next
3327 * time userland calls execbuf, it would do so with presumed offset
3328 * state that didn't match the actual object state.
3329 */
3330 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3331 relocs);
3332 if (ret2 != 0) {
3333 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3334
3335 if (ret == 0)
3336 ret = ret2;
3337 }
3338
Eric Anholt673a3942008-07-30 12:06:12 -07003339pre_mutex_err:
3340 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
3341 DRM_MEM_DRIVER);
3342 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
3343 DRM_MEM_DRIVER);
Eric Anholt201361a2009-03-11 12:30:04 -07003344 drm_free(cliprects, sizeof(*cliprects) * args->num_cliprects,
3345 DRM_MEM_DRIVER);
Eric Anholt673a3942008-07-30 12:06:12 -07003346
3347 return ret;
3348}
3349
3350int
3351i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3352{
3353 struct drm_device *dev = obj->dev;
3354 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3355 int ret;
3356
3357 i915_verify_inactive(dev, __FILE__, __LINE__);
3358 if (obj_priv->gtt_space == NULL) {
3359 ret = i915_gem_object_bind_to_gtt(obj, alignment);
3360 if (ret != 0) {
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08003361 if (ret != -EBUSY && ret != -ERESTARTSYS)
Kyle McMartin0fce81e2009-02-28 15:01:16 -05003362 DRM_ERROR("Failure to bind: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07003363 return ret;
3364 }
Chris Wilson22c344e2009-02-11 14:26:45 +00003365 }
3366 /*
3367 * Pre-965 chips need a fence register set up in order to
3368 * properly handle tiled surfaces.
3369 */
3370 if (!IS_I965G(dev) &&
3371 obj_priv->fence_reg == I915_FENCE_REG_NONE &&
3372 obj_priv->tiling_mode != I915_TILING_NONE) {
3373 ret = i915_gem_object_get_fence_reg(obj, true);
3374 if (ret != 0) {
3375 if (ret != -EBUSY && ret != -ERESTARTSYS)
3376 DRM_ERROR("Failure to install fence: %d\n",
3377 ret);
3378 return ret;
3379 }
Eric Anholt673a3942008-07-30 12:06:12 -07003380 }
3381 obj_priv->pin_count++;
3382
3383 /* If the object is not active and not pending a flush,
3384 * remove it from the inactive list
3385 */
3386 if (obj_priv->pin_count == 1) {
3387 atomic_inc(&dev->pin_count);
3388 atomic_add(obj->size, &dev->pin_memory);
3389 if (!obj_priv->active &&
3390 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
3391 I915_GEM_DOMAIN_GTT)) == 0 &&
3392 !list_empty(&obj_priv->list))
3393 list_del_init(&obj_priv->list);
3394 }
3395 i915_verify_inactive(dev, __FILE__, __LINE__);
3396
3397 return 0;
3398}
3399
3400void
3401i915_gem_object_unpin(struct drm_gem_object *obj)
3402{
3403 struct drm_device *dev = obj->dev;
3404 drm_i915_private_t *dev_priv = dev->dev_private;
3405 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3406
3407 i915_verify_inactive(dev, __FILE__, __LINE__);
3408 obj_priv->pin_count--;
3409 BUG_ON(obj_priv->pin_count < 0);
3410 BUG_ON(obj_priv->gtt_space == NULL);
3411
3412 /* If the object is no longer pinned, and is
3413 * neither active nor being flushed, then stick it on
3414 * the inactive list
3415 */
3416 if (obj_priv->pin_count == 0) {
3417 if (!obj_priv->active &&
3418 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
3419 I915_GEM_DOMAIN_GTT)) == 0)
3420 list_move_tail(&obj_priv->list,
3421 &dev_priv->mm.inactive_list);
3422 atomic_dec(&dev->pin_count);
3423 atomic_sub(obj->size, &dev->pin_memory);
3424 }
3425 i915_verify_inactive(dev, __FILE__, __LINE__);
3426}
3427
3428int
3429i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3430 struct drm_file *file_priv)
3431{
3432 struct drm_i915_gem_pin *args = data;
3433 struct drm_gem_object *obj;
3434 struct drm_i915_gem_object *obj_priv;
3435 int ret;
3436
3437 mutex_lock(&dev->struct_mutex);
3438
3439 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3440 if (obj == NULL) {
3441 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3442 args->handle);
3443 mutex_unlock(&dev->struct_mutex);
3444 return -EBADF;
3445 }
3446 obj_priv = obj->driver_private;
3447
Jesse Barnes79e53942008-11-07 14:24:08 -08003448 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3449 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3450 args->handle);
Chris Wilson96dec612009-02-08 19:08:04 +00003451 drm_gem_object_unreference(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003452 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08003453 return -EINVAL;
3454 }
3455
3456 obj_priv->user_pin_count++;
3457 obj_priv->pin_filp = file_priv;
3458 if (obj_priv->user_pin_count == 1) {
3459 ret = i915_gem_object_pin(obj, args->alignment);
3460 if (ret != 0) {
3461 drm_gem_object_unreference(obj);
3462 mutex_unlock(&dev->struct_mutex);
3463 return ret;
3464 }
Eric Anholt673a3942008-07-30 12:06:12 -07003465 }
3466
3467 /* XXX - flush the CPU caches for pinned objects
3468 * as the X server doesn't manage domains yet
3469 */
Eric Anholte47c68e2008-11-14 13:35:19 -08003470 i915_gem_object_flush_cpu_write_domain(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003471 args->offset = obj_priv->gtt_offset;
3472 drm_gem_object_unreference(obj);
3473 mutex_unlock(&dev->struct_mutex);
3474
3475 return 0;
3476}
3477
3478int
3479i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3480 struct drm_file *file_priv)
3481{
3482 struct drm_i915_gem_pin *args = data;
3483 struct drm_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08003484 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07003485
3486 mutex_lock(&dev->struct_mutex);
3487
3488 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3489 if (obj == NULL) {
3490 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3491 args->handle);
3492 mutex_unlock(&dev->struct_mutex);
3493 return -EBADF;
3494 }
3495
Jesse Barnes79e53942008-11-07 14:24:08 -08003496 obj_priv = obj->driver_private;
3497 if (obj_priv->pin_filp != file_priv) {
3498 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3499 args->handle);
3500 drm_gem_object_unreference(obj);
3501 mutex_unlock(&dev->struct_mutex);
3502 return -EINVAL;
3503 }
3504 obj_priv->user_pin_count--;
3505 if (obj_priv->user_pin_count == 0) {
3506 obj_priv->pin_filp = NULL;
3507 i915_gem_object_unpin(obj);
3508 }
Eric Anholt673a3942008-07-30 12:06:12 -07003509
3510 drm_gem_object_unreference(obj);
3511 mutex_unlock(&dev->struct_mutex);
3512 return 0;
3513}
3514
3515int
3516i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3517 struct drm_file *file_priv)
3518{
3519 struct drm_i915_gem_busy *args = data;
3520 struct drm_gem_object *obj;
3521 struct drm_i915_gem_object *obj_priv;
3522
3523 mutex_lock(&dev->struct_mutex);
3524 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3525 if (obj == NULL) {
3526 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
3527 args->handle);
3528 mutex_unlock(&dev->struct_mutex);
3529 return -EBADF;
3530 }
3531
Eric Anholtf21289b2009-02-18 09:44:56 -08003532 /* Update the active list for the hardware's current position.
3533 * Otherwise this only updates on a delayed timer or when irqs are
3534 * actually unmasked, and our working set ends up being larger than
3535 * required.
3536 */
3537 i915_gem_retire_requests(dev);
3538
Eric Anholt673a3942008-07-30 12:06:12 -07003539 obj_priv = obj->driver_private;
Eric Anholtc4de0a52008-12-14 19:05:04 -08003540 /* Don't count being on the flushing list against the object being
3541 * done. Otherwise, a buffer left on the flushing list but not getting
3542 * flushed (because nobody's flushing that domain) won't ever return
3543 * unbusy and get reused by libdrm's bo cache. The other expected
3544 * consumer of this interface, OpenGL's occlusion queries, also specs
3545 * that the objects get unbusy "eventually" without any interference.
3546 */
3547 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003548
3549 drm_gem_object_unreference(obj);
3550 mutex_unlock(&dev->struct_mutex);
3551 return 0;
3552}
3553
3554int
3555i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3556 struct drm_file *file_priv)
3557{
3558 return i915_gem_ring_throttle(dev, file_priv);
3559}
3560
3561int i915_gem_init_object(struct drm_gem_object *obj)
3562{
3563 struct drm_i915_gem_object *obj_priv;
3564
3565 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
3566 if (obj_priv == NULL)
3567 return -ENOMEM;
3568
3569 /*
3570 * We've just allocated pages from the kernel,
3571 * so they've just been written by the CPU with
3572 * zeros. They'll need to be clflushed before we
3573 * use them with the GPU.
3574 */
3575 obj->write_domain = I915_GEM_DOMAIN_CPU;
3576 obj->read_domains = I915_GEM_DOMAIN_CPU;
3577
Keith Packardba1eb1d2008-10-14 19:55:10 -07003578 obj_priv->agp_type = AGP_USER_MEMORY;
3579
Eric Anholt673a3942008-07-30 12:06:12 -07003580 obj->driver_private = obj_priv;
3581 obj_priv->obj = obj;
Jesse Barnesde151cf2008-11-12 10:03:55 -08003582 obj_priv->fence_reg = I915_FENCE_REG_NONE;
Eric Anholt673a3942008-07-30 12:06:12 -07003583 INIT_LIST_HEAD(&obj_priv->list);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003584
Eric Anholt673a3942008-07-30 12:06:12 -07003585 return 0;
3586}
3587
3588void i915_gem_free_object(struct drm_gem_object *obj)
3589{
Jesse Barnesde151cf2008-11-12 10:03:55 -08003590 struct drm_device *dev = obj->dev;
Eric Anholt673a3942008-07-30 12:06:12 -07003591 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3592
3593 while (obj_priv->pin_count > 0)
3594 i915_gem_object_unpin(obj);
3595
Dave Airlie71acb5e2008-12-30 20:31:46 +10003596 if (obj_priv->phys_obj)
3597 i915_gem_detach_phys_object(dev, obj);
3598
Eric Anholt673a3942008-07-30 12:06:12 -07003599 i915_gem_object_unbind(obj);
3600
Jesse Barnesab00b3e2009-02-11 14:01:46 -08003601 i915_gem_free_mmap_offset(obj);
Jesse Barnesde151cf2008-11-12 10:03:55 -08003602
Eric Anholt673a3942008-07-30 12:06:12 -07003603 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
3604 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
3605}
3606
Eric Anholt673a3942008-07-30 12:06:12 -07003607/** Unbinds all objects that are on the given buffer list. */
3608static int
3609i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
3610{
3611 struct drm_gem_object *obj;
3612 struct drm_i915_gem_object *obj_priv;
3613 int ret;
3614
3615 while (!list_empty(head)) {
3616 obj_priv = list_first_entry(head,
3617 struct drm_i915_gem_object,
3618 list);
3619 obj = obj_priv->obj;
3620
3621 if (obj_priv->pin_count != 0) {
3622 DRM_ERROR("Pinned object in unbind list\n");
3623 mutex_unlock(&dev->struct_mutex);
3624 return -EINVAL;
3625 }
3626
3627 ret = i915_gem_object_unbind(obj);
3628 if (ret != 0) {
3629 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
3630 ret);
3631 mutex_unlock(&dev->struct_mutex);
3632 return ret;
3633 }
3634 }
3635
3636
3637 return 0;
3638}
3639
Jesse Barnes5669fca2009-02-17 15:13:31 -08003640int
Eric Anholt673a3942008-07-30 12:06:12 -07003641i915_gem_idle(struct drm_device *dev)
3642{
3643 drm_i915_private_t *dev_priv = dev->dev_private;
3644 uint32_t seqno, cur_seqno, last_seqno;
3645 int stuck, ret;
3646
Keith Packard6dbe2772008-10-14 21:41:13 -07003647 mutex_lock(&dev->struct_mutex);
3648
3649 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
3650 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07003651 return 0;
Keith Packard6dbe2772008-10-14 21:41:13 -07003652 }
Eric Anholt673a3942008-07-30 12:06:12 -07003653
3654 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3655 * We need to replace this with a semaphore, or something.
3656 */
3657 dev_priv->mm.suspended = 1;
3658
Keith Packard6dbe2772008-10-14 21:41:13 -07003659 /* Cancel the retire work handler, wait for it to finish if running
3660 */
3661 mutex_unlock(&dev->struct_mutex);
3662 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3663 mutex_lock(&dev->struct_mutex);
3664
Eric Anholt673a3942008-07-30 12:06:12 -07003665 i915_kernel_lost_context(dev);
3666
3667 /* Flush the GPU along with all non-CPU write domains
3668 */
3669 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
3670 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
Jesse Barnesde151cf2008-11-12 10:03:55 -08003671 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
Eric Anholt673a3942008-07-30 12:06:12 -07003672
3673 if (seqno == 0) {
3674 mutex_unlock(&dev->struct_mutex);
3675 return -ENOMEM;
3676 }
3677
3678 dev_priv->mm.waiting_gem_seqno = seqno;
3679 last_seqno = 0;
3680 stuck = 0;
3681 for (;;) {
3682 cur_seqno = i915_get_gem_seqno(dev);
3683 if (i915_seqno_passed(cur_seqno, seqno))
3684 break;
3685 if (last_seqno == cur_seqno) {
3686 if (stuck++ > 100) {
3687 DRM_ERROR("hardware wedged\n");
3688 dev_priv->mm.wedged = 1;
3689 DRM_WAKEUP(&dev_priv->irq_queue);
3690 break;
3691 }
3692 }
3693 msleep(10);
3694 last_seqno = cur_seqno;
3695 }
3696 dev_priv->mm.waiting_gem_seqno = 0;
3697
3698 i915_gem_retire_requests(dev);
3699
Carl Worth5e118f42009-03-20 11:54:25 -07003700 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt28dfe522008-11-13 15:00:55 -08003701 if (!dev_priv->mm.wedged) {
3702 /* Active and flushing should now be empty as we've
3703 * waited for a sequence higher than any pending execbuffer
3704 */
3705 WARN_ON(!list_empty(&dev_priv->mm.active_list));
3706 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
3707 /* Request should now be empty as we've also waited
3708 * for the last request in the list
3709 */
3710 WARN_ON(!list_empty(&dev_priv->mm.request_list));
3711 }
Eric Anholt673a3942008-07-30 12:06:12 -07003712
Eric Anholt28dfe522008-11-13 15:00:55 -08003713 /* Empty the active and flushing lists to inactive. If there's
3714 * anything left at this point, it means that we're wedged and
3715 * nothing good's going to happen by leaving them there. So strip
3716 * the GPU domains and just stuff them onto inactive.
Eric Anholt673a3942008-07-30 12:06:12 -07003717 */
Eric Anholt28dfe522008-11-13 15:00:55 -08003718 while (!list_empty(&dev_priv->mm.active_list)) {
3719 struct drm_i915_gem_object *obj_priv;
Eric Anholt673a3942008-07-30 12:06:12 -07003720
Eric Anholt28dfe522008-11-13 15:00:55 -08003721 obj_priv = list_first_entry(&dev_priv->mm.active_list,
3722 struct drm_i915_gem_object,
3723 list);
3724 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3725 i915_gem_object_move_to_inactive(obj_priv->obj);
3726 }
Carl Worth5e118f42009-03-20 11:54:25 -07003727 spin_unlock(&dev_priv->mm.active_list_lock);
Eric Anholt28dfe522008-11-13 15:00:55 -08003728
3729 while (!list_empty(&dev_priv->mm.flushing_list)) {
3730 struct drm_i915_gem_object *obj_priv;
3731
Eric Anholt151903d2008-12-01 10:23:21 +10003732 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
Eric Anholt28dfe522008-11-13 15:00:55 -08003733 struct drm_i915_gem_object,
3734 list);
3735 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
3736 i915_gem_object_move_to_inactive(obj_priv->obj);
3737 }
3738
3739
3740 /* Move all inactive buffers out of the GTT. */
Eric Anholt673a3942008-07-30 12:06:12 -07003741 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
Eric Anholt28dfe522008-11-13 15:00:55 -08003742 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
Keith Packard6dbe2772008-10-14 21:41:13 -07003743 if (ret) {
3744 mutex_unlock(&dev->struct_mutex);
Eric Anholt673a3942008-07-30 12:06:12 -07003745 return ret;
Keith Packard6dbe2772008-10-14 21:41:13 -07003746 }
Eric Anholt673a3942008-07-30 12:06:12 -07003747
Keith Packard6dbe2772008-10-14 21:41:13 -07003748 i915_gem_cleanup_ringbuffer(dev);
3749 mutex_unlock(&dev->struct_mutex);
3750
Eric Anholt673a3942008-07-30 12:06:12 -07003751 return 0;
3752}
3753
3754static int
3755i915_gem_init_hws(struct drm_device *dev)
3756{
3757 drm_i915_private_t *dev_priv = dev->dev_private;
3758 struct drm_gem_object *obj;
3759 struct drm_i915_gem_object *obj_priv;
3760 int ret;
3761
3762 /* If we need a physical address for the status page, it's already
3763 * initialized at driver load time.
3764 */
3765 if (!I915_NEED_GFX_HWS(dev))
3766 return 0;
3767
3768 obj = drm_gem_object_alloc(dev, 4096);
3769 if (obj == NULL) {
3770 DRM_ERROR("Failed to allocate status page\n");
3771 return -ENOMEM;
3772 }
3773 obj_priv = obj->driver_private;
Keith Packardba1eb1d2008-10-14 19:55:10 -07003774 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
Eric Anholt673a3942008-07-30 12:06:12 -07003775
3776 ret = i915_gem_object_pin(obj, 4096);
3777 if (ret != 0) {
3778 drm_gem_object_unreference(obj);
3779 return ret;
3780 }
3781
3782 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
Eric Anholt673a3942008-07-30 12:06:12 -07003783
Eric Anholt856fa192009-03-19 14:10:50 -07003784 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
Keith Packardba1eb1d2008-10-14 19:55:10 -07003785 if (dev_priv->hw_status_page == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07003786 DRM_ERROR("Failed to map status page.\n");
3787 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
Chris Wilson3eb2ee72009-02-11 14:26:34 +00003788 i915_gem_object_unpin(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003789 drm_gem_object_unreference(obj);
3790 return -EINVAL;
3791 }
3792 dev_priv->hws_obj = obj;
Eric Anholt673a3942008-07-30 12:06:12 -07003793 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
3794 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
Keith Packardba1eb1d2008-10-14 19:55:10 -07003795 I915_READ(HWS_PGA); /* posting read */
Eric Anholt673a3942008-07-30 12:06:12 -07003796 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
3797
3798 return 0;
3799}
3800
Chris Wilson85a7bb92009-02-11 14:52:44 +00003801static void
3802i915_gem_cleanup_hws(struct drm_device *dev)
3803{
3804 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00003805 struct drm_gem_object *obj;
3806 struct drm_i915_gem_object *obj_priv;
Chris Wilson85a7bb92009-02-11 14:52:44 +00003807
3808 if (dev_priv->hws_obj == NULL)
3809 return;
3810
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00003811 obj = dev_priv->hws_obj;
3812 obj_priv = obj->driver_private;
3813
Eric Anholt856fa192009-03-19 14:10:50 -07003814 kunmap(obj_priv->pages[0]);
Chris Wilson85a7bb92009-02-11 14:52:44 +00003815 i915_gem_object_unpin(obj);
3816 drm_gem_object_unreference(obj);
3817 dev_priv->hws_obj = NULL;
Chris Wilsonbab2d1f2009-02-20 17:52:20 +00003818
Chris Wilson85a7bb92009-02-11 14:52:44 +00003819 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3820 dev_priv->hw_status_page = NULL;
3821
3822 /* Write high address into HWS_PGA when disabling. */
3823 I915_WRITE(HWS_PGA, 0x1ffff000);
3824}
3825
Jesse Barnes79e53942008-11-07 14:24:08 -08003826int
Eric Anholt673a3942008-07-30 12:06:12 -07003827i915_gem_init_ringbuffer(struct drm_device *dev)
3828{
3829 drm_i915_private_t *dev_priv = dev->dev_private;
3830 struct drm_gem_object *obj;
3831 struct drm_i915_gem_object *obj_priv;
Jesse Barnes79e53942008-11-07 14:24:08 -08003832 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
Eric Anholt673a3942008-07-30 12:06:12 -07003833 int ret;
Keith Packard50aa253d2008-10-14 17:20:35 -07003834 u32 head;
Eric Anholt673a3942008-07-30 12:06:12 -07003835
3836 ret = i915_gem_init_hws(dev);
3837 if (ret != 0)
3838 return ret;
3839
3840 obj = drm_gem_object_alloc(dev, 128 * 1024);
3841 if (obj == NULL) {
3842 DRM_ERROR("Failed to allocate ringbuffer\n");
Chris Wilson85a7bb92009-02-11 14:52:44 +00003843 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003844 return -ENOMEM;
3845 }
3846 obj_priv = obj->driver_private;
3847
3848 ret = i915_gem_object_pin(obj, 4096);
3849 if (ret != 0) {
3850 drm_gem_object_unreference(obj);
Chris Wilson85a7bb92009-02-11 14:52:44 +00003851 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003852 return ret;
3853 }
3854
3855 /* Set up the kernel mapping for the ring. */
Jesse Barnes79e53942008-11-07 14:24:08 -08003856 ring->Size = obj->size;
3857 ring->tail_mask = obj->size - 1;
Eric Anholt673a3942008-07-30 12:06:12 -07003858
Jesse Barnes79e53942008-11-07 14:24:08 -08003859 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
3860 ring->map.size = obj->size;
3861 ring->map.type = 0;
3862 ring->map.flags = 0;
3863 ring->map.mtrr = 0;
Eric Anholt673a3942008-07-30 12:06:12 -07003864
Jesse Barnes79e53942008-11-07 14:24:08 -08003865 drm_core_ioremap_wc(&ring->map, dev);
3866 if (ring->map.handle == NULL) {
Eric Anholt673a3942008-07-30 12:06:12 -07003867 DRM_ERROR("Failed to map ringbuffer.\n");
3868 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
Chris Wilson47ed1852009-02-11 14:26:33 +00003869 i915_gem_object_unpin(obj);
Eric Anholt673a3942008-07-30 12:06:12 -07003870 drm_gem_object_unreference(obj);
Chris Wilson85a7bb92009-02-11 14:52:44 +00003871 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003872 return -EINVAL;
3873 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003874 ring->ring_obj = obj;
3875 ring->virtual_start = ring->map.handle;
Eric Anholt673a3942008-07-30 12:06:12 -07003876
3877 /* Stop the ring if it's running. */
3878 I915_WRITE(PRB0_CTL, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003879 I915_WRITE(PRB0_TAIL, 0);
Keith Packard50aa253d2008-10-14 17:20:35 -07003880 I915_WRITE(PRB0_HEAD, 0);
Eric Anholt673a3942008-07-30 12:06:12 -07003881
3882 /* Initialize the ring. */
3883 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
Keith Packard50aa253d2008-10-14 17:20:35 -07003884 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3885
3886 /* G45 ring initialization fails to reset head to zero */
3887 if (head != 0) {
3888 DRM_ERROR("Ring head not reset to zero "
3889 "ctl %08x head %08x tail %08x start %08x\n",
3890 I915_READ(PRB0_CTL),
3891 I915_READ(PRB0_HEAD),
3892 I915_READ(PRB0_TAIL),
3893 I915_READ(PRB0_START));
3894 I915_WRITE(PRB0_HEAD, 0);
3895
3896 DRM_ERROR("Ring head forced to zero "
3897 "ctl %08x head %08x tail %08x start %08x\n",
3898 I915_READ(PRB0_CTL),
3899 I915_READ(PRB0_HEAD),
3900 I915_READ(PRB0_TAIL),
3901 I915_READ(PRB0_START));
3902 }
3903
Eric Anholt673a3942008-07-30 12:06:12 -07003904 I915_WRITE(PRB0_CTL,
3905 ((obj->size - 4096) & RING_NR_PAGES) |
3906 RING_NO_REPORT |
3907 RING_VALID);
3908
Keith Packard50aa253d2008-10-14 17:20:35 -07003909 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3910
3911 /* If the head is still not zero, the ring is dead */
3912 if (head != 0) {
3913 DRM_ERROR("Ring initialization failed "
3914 "ctl %08x head %08x tail %08x start %08x\n",
3915 I915_READ(PRB0_CTL),
3916 I915_READ(PRB0_HEAD),
3917 I915_READ(PRB0_TAIL),
3918 I915_READ(PRB0_START));
3919 return -EIO;
3920 }
3921
Eric Anholt673a3942008-07-30 12:06:12 -07003922 /* Update our cache of the ring state */
Jesse Barnes79e53942008-11-07 14:24:08 -08003923 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3924 i915_kernel_lost_context(dev);
3925 else {
3926 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
3927 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
3928 ring->space = ring->head - (ring->tail + 8);
3929 if (ring->space < 0)
3930 ring->space += ring->Size;
3931 }
Eric Anholt673a3942008-07-30 12:06:12 -07003932
3933 return 0;
3934}
3935
Jesse Barnes79e53942008-11-07 14:24:08 -08003936void
Eric Anholt673a3942008-07-30 12:06:12 -07003937i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3938{
3939 drm_i915_private_t *dev_priv = dev->dev_private;
3940
3941 if (dev_priv->ring.ring_obj == NULL)
3942 return;
3943
3944 drm_core_ioremapfree(&dev_priv->ring.map, dev);
3945
3946 i915_gem_object_unpin(dev_priv->ring.ring_obj);
3947 drm_gem_object_unreference(dev_priv->ring.ring_obj);
3948 dev_priv->ring.ring_obj = NULL;
3949 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
3950
Chris Wilson85a7bb92009-02-11 14:52:44 +00003951 i915_gem_cleanup_hws(dev);
Eric Anholt673a3942008-07-30 12:06:12 -07003952}
3953
3954int
3955i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3956 struct drm_file *file_priv)
3957{
3958 drm_i915_private_t *dev_priv = dev->dev_private;
3959 int ret;
3960
Jesse Barnes79e53942008-11-07 14:24:08 -08003961 if (drm_core_check_feature(dev, DRIVER_MODESET))
3962 return 0;
3963
Eric Anholt673a3942008-07-30 12:06:12 -07003964 if (dev_priv->mm.wedged) {
3965 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3966 dev_priv->mm.wedged = 0;
3967 }
3968
Eric Anholt673a3942008-07-30 12:06:12 -07003969 mutex_lock(&dev->struct_mutex);
Eric Anholt9bb2d6f2008-12-23 18:42:32 -08003970 dev_priv->mm.suspended = 0;
3971
3972 ret = i915_gem_init_ringbuffer(dev);
3973 if (ret != 0)
3974 return ret;
3975
Carl Worth5e118f42009-03-20 11:54:25 -07003976 spin_lock(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07003977 BUG_ON(!list_empty(&dev_priv->mm.active_list));
Carl Worth5e118f42009-03-20 11:54:25 -07003978 spin_unlock(&dev_priv->mm.active_list_lock);
3979
Eric Anholt673a3942008-07-30 12:06:12 -07003980 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3981 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3982 BUG_ON(!list_empty(&dev_priv->mm.request_list));
Eric Anholt673a3942008-07-30 12:06:12 -07003983 mutex_unlock(&dev->struct_mutex);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04003984
3985 drm_irq_install(dev);
3986
Eric Anholt673a3942008-07-30 12:06:12 -07003987 return 0;
3988}
3989
3990int
3991i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3992 struct drm_file *file_priv)
3993{
3994 int ret;
3995
Jesse Barnes79e53942008-11-07 14:24:08 -08003996 if (drm_core_check_feature(dev, DRIVER_MODESET))
3997 return 0;
3998
Eric Anholt673a3942008-07-30 12:06:12 -07003999 ret = i915_gem_idle(dev);
Kristian Høgsbergdbb19d32008-08-20 11:04:27 -04004000 drm_irq_uninstall(dev);
4001
Keith Packard6dbe2772008-10-14 21:41:13 -07004002 return ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004003}
4004
4005void
4006i915_gem_lastclose(struct drm_device *dev)
4007{
4008 int ret;
Eric Anholt673a3942008-07-30 12:06:12 -07004009
Eric Anholte806b492009-01-22 09:56:58 -08004010 if (drm_core_check_feature(dev, DRIVER_MODESET))
4011 return;
4012
Keith Packard6dbe2772008-10-14 21:41:13 -07004013 ret = i915_gem_idle(dev);
4014 if (ret)
4015 DRM_ERROR("failed to idle hardware: %d\n", ret);
Eric Anholt673a3942008-07-30 12:06:12 -07004016}
4017
4018void
4019i915_gem_load(struct drm_device *dev)
4020{
4021 drm_i915_private_t *dev_priv = dev->dev_private;
4022
Carl Worth5e118f42009-03-20 11:54:25 -07004023 spin_lock_init(&dev_priv->mm.active_list_lock);
Eric Anholt673a3942008-07-30 12:06:12 -07004024 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4025 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4026 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4027 INIT_LIST_HEAD(&dev_priv->mm.request_list);
4028 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4029 i915_gem_retire_work_handler);
Eric Anholt673a3942008-07-30 12:06:12 -07004030 dev_priv->mm.next_gem_seqno = 1;
4031
Jesse Barnesde151cf2008-11-12 10:03:55 -08004032 /* Old X drivers will take 0-2 for front, back, depth buffers */
4033 dev_priv->fence_reg_start = 3;
4034
Jesse Barnes0f973f22009-01-26 17:10:45 -08004035 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
Jesse Barnesde151cf2008-11-12 10:03:55 -08004036 dev_priv->num_fence_regs = 16;
4037 else
4038 dev_priv->num_fence_regs = 8;
4039
Eric Anholt673a3942008-07-30 12:06:12 -07004040 i915_gem_detect_bit_6_swizzle(dev);
4041}
Dave Airlie71acb5e2008-12-30 20:31:46 +10004042
4043/*
4044 * Create a physically contiguous memory object for this object
4045 * e.g. for cursor + overlay regs
4046 */
4047int i915_gem_init_phys_object(struct drm_device *dev,
4048 int id, int size)
4049{
4050 drm_i915_private_t *dev_priv = dev->dev_private;
4051 struct drm_i915_gem_phys_object *phys_obj;
4052 int ret;
4053
4054 if (dev_priv->mm.phys_objs[id - 1] || !size)
4055 return 0;
4056
4057 phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4058 if (!phys_obj)
4059 return -ENOMEM;
4060
4061 phys_obj->id = id;
4062
4063 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4064 if (!phys_obj->handle) {
4065 ret = -ENOMEM;
4066 goto kfree_obj;
4067 }
4068#ifdef CONFIG_X86
4069 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4070#endif
4071
4072 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4073
4074 return 0;
4075kfree_obj:
4076 drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
4077 return ret;
4078}
4079
4080void i915_gem_free_phys_object(struct drm_device *dev, int id)
4081{
4082 drm_i915_private_t *dev_priv = dev->dev_private;
4083 struct drm_i915_gem_phys_object *phys_obj;
4084
4085 if (!dev_priv->mm.phys_objs[id - 1])
4086 return;
4087
4088 phys_obj = dev_priv->mm.phys_objs[id - 1];
4089 if (phys_obj->cur_obj) {
4090 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4091 }
4092
4093#ifdef CONFIG_X86
4094 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4095#endif
4096 drm_pci_free(dev, phys_obj->handle);
4097 kfree(phys_obj);
4098 dev_priv->mm.phys_objs[id - 1] = NULL;
4099}
4100
4101void i915_gem_free_all_phys_object(struct drm_device *dev)
4102{
4103 int i;
4104
Dave Airlie260883c2009-01-22 17:58:49 +10004105 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
Dave Airlie71acb5e2008-12-30 20:31:46 +10004106 i915_gem_free_phys_object(dev, i);
4107}
4108
4109void i915_gem_detach_phys_object(struct drm_device *dev,
4110 struct drm_gem_object *obj)
4111{
4112 struct drm_i915_gem_object *obj_priv;
4113 int i;
4114 int ret;
4115 int page_count;
4116
4117 obj_priv = obj->driver_private;
4118 if (!obj_priv->phys_obj)
4119 return;
4120
Eric Anholt856fa192009-03-19 14:10:50 -07004121 ret = i915_gem_object_get_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004122 if (ret)
4123 goto out;
4124
4125 page_count = obj->size / PAGE_SIZE;
4126
4127 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004128 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004129 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4130
4131 memcpy(dst, src, PAGE_SIZE);
4132 kunmap_atomic(dst, KM_USER0);
4133 }
Eric Anholt856fa192009-03-19 14:10:50 -07004134 drm_clflush_pages(obj_priv->pages, page_count);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004135 drm_agp_chipset_flush(dev);
4136out:
4137 obj_priv->phys_obj->cur_obj = NULL;
4138 obj_priv->phys_obj = NULL;
4139}
4140
4141int
4142i915_gem_attach_phys_object(struct drm_device *dev,
4143 struct drm_gem_object *obj, int id)
4144{
4145 drm_i915_private_t *dev_priv = dev->dev_private;
4146 struct drm_i915_gem_object *obj_priv;
4147 int ret = 0;
4148 int page_count;
4149 int i;
4150
4151 if (id > I915_MAX_PHYS_OBJECT)
4152 return -EINVAL;
4153
4154 obj_priv = obj->driver_private;
4155
4156 if (obj_priv->phys_obj) {
4157 if (obj_priv->phys_obj->id == id)
4158 return 0;
4159 i915_gem_detach_phys_object(dev, obj);
4160 }
4161
4162
4163 /* create a new object */
4164 if (!dev_priv->mm.phys_objs[id - 1]) {
4165 ret = i915_gem_init_phys_object(dev, id,
4166 obj->size);
4167 if (ret) {
Linus Torvaldsaeb565d2009-01-26 10:01:53 -08004168 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004169 goto out;
4170 }
4171 }
4172
4173 /* bind to the object */
4174 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4175 obj_priv->phys_obj->cur_obj = obj;
4176
Eric Anholt856fa192009-03-19 14:10:50 -07004177 ret = i915_gem_object_get_pages(obj);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004178 if (ret) {
4179 DRM_ERROR("failed to get page list\n");
4180 goto out;
4181 }
4182
4183 page_count = obj->size / PAGE_SIZE;
4184
4185 for (i = 0; i < page_count; i++) {
Eric Anholt856fa192009-03-19 14:10:50 -07004186 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004187 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4188
4189 memcpy(dst, src, PAGE_SIZE);
4190 kunmap_atomic(src, KM_USER0);
4191 }
4192
4193 return 0;
4194out:
4195 return ret;
4196}
4197
4198static int
4199i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4200 struct drm_i915_gem_pwrite *args,
4201 struct drm_file *file_priv)
4202{
4203 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4204 void *obj_addr;
4205 int ret;
4206 char __user *user_data;
4207
4208 user_data = (char __user *) (uintptr_t) args->data_ptr;
4209 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4210
Dave Airliee08fb4f2009-02-25 14:52:30 +10004211 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
Dave Airlie71acb5e2008-12-30 20:31:46 +10004212 ret = copy_from_user(obj_addr, user_data, args->size);
4213 if (ret)
4214 return -EFAULT;
4215
4216 drm_agp_chipset_flush(dev);
4217 return 0;
4218}