| Andrei Konovalov | e6b6239 | 2005-07-05 18:54:43 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * A collection of structures, addresses, and values associated with |
| 3 | * the Freescale MPC885ADS board. |
| 4 | * Copied from the FADS stuff. |
| 5 | * |
| 6 | * Author: MontaVista Software, Inc. |
| 7 | * source@mvista.com |
| 8 | * |
| 9 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the |
| 10 | * terms of the GNU General Public License version 2. This program is licensed |
| 11 | * "as is" without any warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | #ifdef __KERNEL__ |
| 15 | #ifndef __ASM_MPC885ADS_H__ |
| 16 | #define __ASM_MPC885ADS_H__ |
| 17 | |
| 18 | #include <linux/config.h> |
| 19 | |
| 20 | #include <asm/ppcboot.h> |
| 21 | |
| 22 | /* U-Boot maps BCSR to 0xff080000 */ |
| 23 | #define BCSR_ADDR ((uint)0xff080000) |
| 24 | #define BCSR_SIZE ((uint)32) |
| 25 | #define BCSR0 ((uint)(BCSR_ADDR + 0x00)) |
| 26 | #define BCSR1 ((uint)(BCSR_ADDR + 0x04)) |
| 27 | #define BCSR2 ((uint)(BCSR_ADDR + 0x08)) |
| 28 | #define BCSR3 ((uint)(BCSR_ADDR + 0x0c)) |
| 29 | #define BCSR4 ((uint)(BCSR_ADDR + 0x10)) |
| 30 | |
| 31 | #define CFG_PHYDEV_ADDR ((uint)0xff0a0000) |
| 32 | #define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300)) |
| 33 | |
| 34 | #define IMAP_ADDR ((uint)0xff000000) |
| 35 | #define IMAP_SIZE ((uint)(64 * 1024)) |
| 36 | |
| 37 | #define PCMCIA_MEM_ADDR ((uint)0xff020000) |
| 38 | #define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) |
| 39 | |
| 40 | /* Bits of interest in the BCSRs. |
| 41 | */ |
| 42 | #define BCSR1_ETHEN ((uint)0x20000000) |
| 43 | #define BCSR1_IRDAEN ((uint)0x10000000) |
| 44 | #define BCSR1_RS232EN_1 ((uint)0x01000000) |
| 45 | #define BCSR1_PCCEN ((uint)0x00800000) |
| 46 | #define BCSR1_PCCVCC0 ((uint)0x00400000) |
| 47 | #define BCSR1_PCCVPP0 ((uint)0x00200000) |
| 48 | #define BCSR1_PCCVPP1 ((uint)0x00100000) |
| 49 | #define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1) |
| 50 | #define BCSR1_RS232EN_2 ((uint)0x00040000) |
| 51 | #define BCSR1_PCCVCC1 ((uint)0x00010000) |
| 52 | #define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1) |
| 53 | |
| 54 | #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/ |
| 55 | #define BCSR4_USB_LO_SPD ((uint)0x04000000) |
| 56 | #define BCSR4_USB_VCC ((uint)0x02000000) |
| 57 | #define BCSR4_USB_FULL_SPD ((uint)0x00040000) |
| 58 | #define BCSR4_USB_EN ((uint)0x00020000) |
| 59 | |
| 60 | #define BCSR5_MII2_EN 0x40 |
| 61 | #define BCSR5_MII2_RST 0x20 |
| 62 | #define BCSR5_T1_RST 0x10 |
| 63 | #define BCSR5_ATM155_RST 0x08 |
| 64 | #define BCSR5_ATM25_RST 0x04 |
| 65 | #define BCSR5_MII1_EN 0x02 |
| 66 | #define BCSR5_MII1_RST 0x01 |
| 67 | |
| 68 | /* Interrupt level assignments */ |
| 69 | #define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */ |
| 70 | #define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */ |
| 71 | #define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */ |
| 72 | #define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */ |
| 73 | |
| 74 | /* We don't use the 8259 */ |
| 75 | #define NR_8259_INTS 0 |
| 76 | |
| 77 | /* CPM Ethernet through SCC3 */ |
| 78 | #define PA_ENET_RXD ((ushort)0x0040) |
| 79 | #define PA_ENET_TXD ((ushort)0x0080) |
| 80 | #define PE_ENET_TCLK ((uint)0x00004000) |
| 81 | #define PE_ENET_RCLK ((uint)0x00008000) |
| 82 | #define PE_ENET_TENA ((uint)0x00000010) |
| 83 | #define PC_ENET_CLSN ((ushort)0x0400) |
| 84 | #define PC_ENET_RENA ((ushort)0x0800) |
| 85 | |
| 86 | /* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to |
| 87 | * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */ |
| 88 | #define SICR_ENET_MASK ((uint)0x00ff0000) |
| 89 | #define SICR_ENET_CLKRT ((uint)0x002c0000) |
| 90 | |
| 91 | #endif /* __ASM_MPC885ADS_H__ */ |
| 92 | #endif /* __KERNEL__ */ |