blob: 3bb85b127cb0d6fcd336d10168604f03fba11342 [file] [log] [blame]
Alex Dai33a732f2015-08-12 15:43:36 +01001/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24#ifndef _INTEL_GUC_H_
25#define _INTEL_GUC_H_
26
27#include "intel_guc_fwif.h"
28#include "i915_guc_reg.h"
29
Chris Wilsone73bdd22016-04-13 17:35:01 +010030struct drm_i915_gem_request;
31
Dave Gordon44a28b12015-08-12 15:43:41 +010032struct i915_guc_client {
33 struct drm_i915_gem_object *client_obj;
Alex Daid1675192015-08-12 15:43:43 +010034 struct intel_context *owner;
Dave Gordon44a28b12015-08-12 15:43:41 +010035 struct intel_guc *guc;
36 uint32_t priority;
37 uint32_t ctx_index;
38
39 uint32_t proc_desc_offset;
40 uint32_t doorbell_offset;
41 uint32_t cookie;
42 uint16_t doorbell_id;
43 uint16_t padding; /* Maintain alignment */
44
45 uint32_t wq_offset;
46 uint32_t wq_size;
Dave Gordon44a28b12015-08-12 15:43:41 +010047 uint32_t wq_tail;
Alex Daia7e02192015-12-16 11:45:55 -080048 uint32_t wq_head;
Dave Gordon44a28b12015-08-12 15:43:41 +010049
50 /* GuC submission statistics & status */
Alex Dai397097b2016-01-23 11:58:14 -080051 uint64_t submissions[GUC_MAX_ENGINES_NUM];
Dave Gordon44a28b12015-08-12 15:43:41 +010052 uint32_t q_fail;
53 uint32_t b_fail;
54 int retcode;
55};
56
Alex Dai33a732f2015-08-12 15:43:36 +010057enum intel_guc_fw_status {
58 GUC_FIRMWARE_FAIL = -1,
59 GUC_FIRMWARE_NONE = 0,
60 GUC_FIRMWARE_PENDING,
61 GUC_FIRMWARE_SUCCESS
62};
63
64/*
65 * This structure encapsulates all the data needed during the process
66 * of fetching, caching, and loading the firmware image into the GuC.
67 */
68struct intel_guc_fw {
69 struct drm_device * guc_dev;
70 const char * guc_fw_path;
71 size_t guc_fw_size;
72 struct drm_i915_gem_object * guc_fw_obj;
73 enum intel_guc_fw_status guc_fw_fetch_status;
74 enum intel_guc_fw_status guc_fw_load_status;
75
76 uint16_t guc_fw_major_wanted;
77 uint16_t guc_fw_minor_wanted;
78 uint16_t guc_fw_major_found;
79 uint16_t guc_fw_minor_found;
Alex Daifeda33e2015-10-19 16:10:54 -070080
81 uint32_t header_size;
82 uint32_t header_offset;
83 uint32_t rsa_size;
84 uint32_t rsa_offset;
85 uint32_t ucode_size;
86 uint32_t ucode_offset;
Alex Dai33a732f2015-08-12 15:43:36 +010087};
88
89struct intel_guc {
90 struct intel_guc_fw guc_fw;
Alex Dai33a732f2015-08-12 15:43:36 +010091 uint32_t log_flags;
Alex Dai4c7e77f2015-08-12 15:43:40 +010092 struct drm_i915_gem_object *log_obj;
Alex Daibac427f2015-08-12 15:43:39 +010093
Alex Dai68371a92015-12-18 12:00:09 -080094 struct drm_i915_gem_object *ads_obj;
95
Alex Daibac427f2015-08-12 15:43:39 +010096 struct drm_i915_gem_object *ctx_pool_obj;
97 struct ida ctx_ids;
Dave Gordon44a28b12015-08-12 15:43:41 +010098
99 struct i915_guc_client *execbuf_client;
100
Dave Gordon44a28b12015-08-12 15:43:41 +0100101 DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS);
102 uint32_t db_cacheline; /* Cyclic counter mod pagesize */
103
104 /* Action status & statistics */
105 uint64_t action_count; /* Total commands issued */
106 uint32_t action_cmd; /* Last command word */
107 uint32_t action_status; /* Last return status */
108 uint32_t action_fail; /* Total number of failures */
109 int32_t action_err; /* Last error code */
110
Alex Dai397097b2016-01-23 11:58:14 -0800111 uint64_t submissions[GUC_MAX_ENGINES_NUM];
112 uint32_t last_seqno[GUC_MAX_ENGINES_NUM];
Alex Dai33a732f2015-08-12 15:43:36 +0100113};
114
115/* intel_guc_loader.c */
116extern void intel_guc_ucode_init(struct drm_device *dev);
117extern int intel_guc_ucode_load(struct drm_device *dev);
118extern void intel_guc_ucode_fini(struct drm_device *dev);
119extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status);
Alex Daia1c41992015-09-30 09:46:37 -0700120extern int intel_guc_suspend(struct drm_device *dev);
121extern int intel_guc_resume(struct drm_device *dev);
Alex Dai33a732f2015-08-12 15:43:36 +0100122
Alex Daibac427f2015-08-12 15:43:39 +0100123/* i915_guc_submission.c */
124int i915_guc_submission_init(struct drm_device *dev);
Dave Gordon44a28b12015-08-12 15:43:41 +0100125int i915_guc_submission_enable(struct drm_device *dev);
126int i915_guc_submit(struct i915_guc_client *client,
127 struct drm_i915_gem_request *rq);
128void i915_guc_submission_disable(struct drm_device *dev);
Alex Daibac427f2015-08-12 15:43:39 +0100129void i915_guc_submission_fini(struct drm_device *dev);
Alex Daia7e02192015-12-16 11:45:55 -0800130int i915_guc_wq_check_space(struct i915_guc_client *client);
Alex Daibac427f2015-08-12 15:43:39 +0100131
Alex Dai33a732f2015-08-12 15:43:36 +0100132#endif