Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2008 Atheros Communications Inc. |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ATH9K_H |
| 18 | #define ATH9K_H |
| 19 | |
| 20 | #include <linux/io.h> |
| 21 | |
| 22 | #define ATHEROS_VENDOR_ID 0x168c |
| 23 | |
| 24 | #define AR5416_DEVID_PCI 0x0023 |
| 25 | #define AR5416_DEVID_PCIE 0x0024 |
| 26 | #define AR9160_DEVID_PCI 0x0027 |
| 27 | #define AR9280_DEVID_PCI 0x0029 |
| 28 | #define AR9280_DEVID_PCIE 0x002a |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame^] | 29 | #define AR9285_DEVID_PCIE 0x002b |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 30 | |
| 31 | #define AR5416_AR9100_DEVID 0x000b |
| 32 | |
| 33 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
| 34 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 |
| 35 | |
| 36 | #define ATH9K_TXERR_XRETRY 0x01 |
| 37 | #define ATH9K_TXERR_FILT 0x02 |
| 38 | #define ATH9K_TXERR_FIFO 0x04 |
| 39 | #define ATH9K_TXERR_XTXOP 0x08 |
| 40 | #define ATH9K_TXERR_TIMER_EXPIRED 0x10 |
| 41 | |
| 42 | #define ATH9K_TX_BA 0x01 |
| 43 | #define ATH9K_TX_PWRMGMT 0x02 |
| 44 | #define ATH9K_TX_DESC_CFG_ERR 0x04 |
| 45 | #define ATH9K_TX_DATA_UNDERRUN 0x08 |
| 46 | #define ATH9K_TX_DELIM_UNDERRUN 0x10 |
| 47 | #define ATH9K_TX_SW_ABORTED 0x40 |
| 48 | #define ATH9K_TX_SW_FILTERED 0x80 |
| 49 | |
| 50 | #define NBBY 8 |
| 51 | |
| 52 | struct ath_tx_status { |
| 53 | u32 ts_tstamp; |
| 54 | u16 ts_seqnum; |
| 55 | u8 ts_status; |
| 56 | u8 ts_ratecode; |
| 57 | u8 ts_rateindex; |
| 58 | int8_t ts_rssi; |
| 59 | u8 ts_shortretry; |
| 60 | u8 ts_longretry; |
| 61 | u8 ts_virtcol; |
| 62 | u8 ts_antenna; |
| 63 | u8 ts_flags; |
| 64 | int8_t ts_rssi_ctl0; |
| 65 | int8_t ts_rssi_ctl1; |
| 66 | int8_t ts_rssi_ctl2; |
| 67 | int8_t ts_rssi_ext0; |
| 68 | int8_t ts_rssi_ext1; |
| 69 | int8_t ts_rssi_ext2; |
| 70 | u8 pad[3]; |
| 71 | u32 ba_low; |
| 72 | u32 ba_high; |
| 73 | u32 evm0; |
| 74 | u32 evm1; |
| 75 | u32 evm2; |
| 76 | }; |
| 77 | |
| 78 | struct ath_rx_status { |
| 79 | u32 rs_tstamp; |
| 80 | u16 rs_datalen; |
| 81 | u8 rs_status; |
| 82 | u8 rs_phyerr; |
| 83 | int8_t rs_rssi; |
| 84 | u8 rs_keyix; |
| 85 | u8 rs_rate; |
| 86 | u8 rs_antenna; |
| 87 | u8 rs_more; |
| 88 | int8_t rs_rssi_ctl0; |
| 89 | int8_t rs_rssi_ctl1; |
| 90 | int8_t rs_rssi_ctl2; |
| 91 | int8_t rs_rssi_ext0; |
| 92 | int8_t rs_rssi_ext1; |
| 93 | int8_t rs_rssi_ext2; |
| 94 | u8 rs_isaggr; |
| 95 | u8 rs_moreaggr; |
| 96 | u8 rs_num_delims; |
| 97 | u8 rs_flags; |
| 98 | u32 evm0; |
| 99 | u32 evm1; |
| 100 | u32 evm2; |
| 101 | }; |
| 102 | |
| 103 | #define ATH9K_RXERR_CRC 0x01 |
| 104 | #define ATH9K_RXERR_PHY 0x02 |
| 105 | #define ATH9K_RXERR_FIFO 0x04 |
| 106 | #define ATH9K_RXERR_DECRYPT 0x08 |
| 107 | #define ATH9K_RXERR_MIC 0x10 |
| 108 | |
| 109 | #define ATH9K_RX_MORE 0x01 |
| 110 | #define ATH9K_RX_MORE_AGGR 0x02 |
| 111 | #define ATH9K_RX_GI 0x04 |
| 112 | #define ATH9K_RX_2040 0x08 |
| 113 | #define ATH9K_RX_DELIM_CRC_PRE 0x10 |
| 114 | #define ATH9K_RX_DELIM_CRC_POST 0x20 |
| 115 | #define ATH9K_RX_DECRYPT_BUSY 0x40 |
| 116 | |
| 117 | #define ATH9K_RXKEYIX_INVALID ((u8)-1) |
| 118 | #define ATH9K_TXKEYIX_INVALID ((u32)-1) |
| 119 | |
| 120 | struct ath_desc { |
| 121 | u32 ds_link; |
| 122 | u32 ds_data; |
| 123 | u32 ds_ctl0; |
| 124 | u32 ds_ctl1; |
| 125 | u32 ds_hw[20]; |
| 126 | union { |
| 127 | struct ath_tx_status tx; |
| 128 | struct ath_rx_status rx; |
| 129 | void *stats; |
| 130 | } ds_us; |
| 131 | void *ds_vdata; |
| 132 | } __packed; |
| 133 | |
| 134 | #define ds_txstat ds_us.tx |
| 135 | #define ds_rxstat ds_us.rx |
| 136 | #define ds_stat ds_us.stats |
| 137 | |
| 138 | #define ATH9K_TXDESC_CLRDMASK 0x0001 |
| 139 | #define ATH9K_TXDESC_NOACK 0x0002 |
| 140 | #define ATH9K_TXDESC_RTSENA 0x0004 |
| 141 | #define ATH9K_TXDESC_CTSENA 0x0008 |
Luis R. Rodriguez | b139a10 | 2008-10-22 13:28:43 -0700 | [diff] [blame] | 142 | /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for |
| 143 | * the descriptor its marked on. We take a tx interrupt to reap |
| 144 | * descriptors when the h/w hits an EOL condition or |
| 145 | * when the descriptor is specifically marked to generate |
| 146 | * an interrupt with this flag. Descriptors should be |
| 147 | * marked periodically to insure timely replenishing of the |
| 148 | * supply needed for sending frames. Defering interrupts |
| 149 | * reduces system load and potentially allows more concurrent |
| 150 | * work to be done but if done to aggressively can cause |
| 151 | * senders to backup. When the hardware queue is left too |
| 152 | * large rate control information may also be too out of |
| 153 | * date. An Alternative for this is TX interrupt mitigation |
| 154 | * but this needs more testing. */ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 155 | #define ATH9K_TXDESC_INTREQ 0x0010 |
| 156 | #define ATH9K_TXDESC_VEOL 0x0020 |
| 157 | #define ATH9K_TXDESC_EXT_ONLY 0x0040 |
| 158 | #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 |
| 159 | #define ATH9K_TXDESC_VMF 0x0100 |
| 160 | #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 |
Jouni Malinen | e022edb | 2008-08-22 17:31:33 +0300 | [diff] [blame] | 161 | #define ATH9K_TXDESC_CAB 0x0400 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 162 | |
| 163 | #define ATH9K_RXDESC_INTREQ 0x0020 |
| 164 | |
Sujith | 86b89ee | 2008-08-07 10:54:57 +0530 | [diff] [blame] | 165 | enum wireless_mode { |
| 166 | ATH9K_MODE_11A = 0, |
| 167 | ATH9K_MODE_11B = 2, |
| 168 | ATH9K_MODE_11G = 3, |
| 169 | ATH9K_MODE_11NA_HT20 = 6, |
| 170 | ATH9K_MODE_11NG_HT20 = 7, |
| 171 | ATH9K_MODE_11NA_HT40PLUS = 8, |
| 172 | ATH9K_MODE_11NA_HT40MINUS = 9, |
| 173 | ATH9K_MODE_11NG_HT40PLUS = 10, |
| 174 | ATH9K_MODE_11NG_HT40MINUS = 11, |
| 175 | ATH9K_MODE_MAX |
| 176 | }; |
| 177 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 178 | enum ath9k_hw_caps { |
| 179 | ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), |
| 180 | ATH9K_HW_CAP_MIC_AESCCM = BIT(1), |
| 181 | ATH9K_HW_CAP_MIC_CKIP = BIT(2), |
| 182 | ATH9K_HW_CAP_MIC_TKIP = BIT(3), |
| 183 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), |
| 184 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), |
| 185 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), |
| 186 | ATH9K_HW_CAP_VEOL = BIT(7), |
| 187 | ATH9K_HW_CAP_BSSIDMASK = BIT(8), |
| 188 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), |
| 189 | ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), |
| 190 | ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), |
| 191 | ATH9K_HW_CAP_HT = BIT(12), |
| 192 | ATH9K_HW_CAP_GTT = BIT(13), |
| 193 | ATH9K_HW_CAP_FASTCC = BIT(14), |
| 194 | ATH9K_HW_CAP_RFSILENT = BIT(15), |
| 195 | ATH9K_HW_CAP_WOW = BIT(16), |
| 196 | ATH9K_HW_CAP_CST = BIT(17), |
| 197 | ATH9K_HW_CAP_ENHANCEDPM = BIT(18), |
| 198 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), |
| 199 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), |
| 200 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 201 | }; |
| 202 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 203 | enum ath9k_capability_type { |
| 204 | ATH9K_CAP_CIPHER = 0, |
| 205 | ATH9K_CAP_TKIP_MIC, |
| 206 | ATH9K_CAP_TKIP_SPLIT, |
| 207 | ATH9K_CAP_PHYCOUNTERS, |
| 208 | ATH9K_CAP_DIVERSITY, |
| 209 | ATH9K_CAP_TXPOW, |
| 210 | ATH9K_CAP_PHYDIAG, |
| 211 | ATH9K_CAP_MCAST_KEYSRCH, |
| 212 | ATH9K_CAP_TSF_ADJUST, |
| 213 | ATH9K_CAP_WME_TKIPMIC, |
| 214 | ATH9K_CAP_RFSILENT, |
| 215 | ATH9K_CAP_ANT_CFG_2GHZ, |
| 216 | ATH9K_CAP_ANT_CFG_5GHZ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 217 | }; |
| 218 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 219 | struct ath9k_hw_capabilities { |
| 220 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ |
Sujith | 86b89ee | 2008-08-07 10:54:57 +0530 | [diff] [blame] | 221 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 222 | u16 total_queues; |
| 223 | u16 keycache_size; |
| 224 | u16 low_5ghz_chan, high_5ghz_chan; |
| 225 | u16 low_2ghz_chan, high_2ghz_chan; |
| 226 | u16 num_mr_retries; |
| 227 | u16 rts_aggr_limit; |
| 228 | u8 tx_chainmask; |
| 229 | u8 rx_chainmask; |
| 230 | u16 tx_triglevel_max; |
| 231 | u16 reg_cap; |
| 232 | u8 num_gpio_pins; |
| 233 | u8 num_antcfg_2ghz; |
| 234 | u8 num_antcfg_5ghz; |
| 235 | }; |
| 236 | |
| 237 | struct ath9k_ops_config { |
| 238 | int dma_beacon_response_time; |
| 239 | int sw_beacon_response_time; |
| 240 | int additional_swba_backoff; |
| 241 | int ack_6mb; |
| 242 | int cwm_ignore_extcca; |
| 243 | u8 pcie_powersave_enable; |
| 244 | u8 pcie_l1skp_enable; |
| 245 | u8 pcie_clock_req; |
| 246 | u32 pcie_waen; |
| 247 | int pcie_power_reset; |
| 248 | u8 pcie_restore; |
| 249 | u8 analog_shiftreg; |
| 250 | u8 ht_enable; |
| 251 | u32 ofdm_trig_low; |
| 252 | u32 ofdm_trig_high; |
| 253 | u32 cck_trig_high; |
| 254 | u32 cck_trig_low; |
| 255 | u32 enable_ani; |
| 256 | u8 noise_immunity_level; |
| 257 | u32 ofdm_weaksignal_det; |
| 258 | u32 cck_weaksignal_thr; |
| 259 | u8 spur_immunity_level; |
| 260 | u8 firstep_level; |
| 261 | int8_t rssi_thr_high; |
| 262 | int8_t rssi_thr_low; |
| 263 | u16 diversity_control; |
| 264 | u16 antenna_switch_swap; |
| 265 | int serialize_regmode; |
| 266 | int intr_mitigation; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 267 | #define SPUR_DISABLE 0 |
| 268 | #define SPUR_ENABLE_IOCTL 1 |
| 269 | #define SPUR_ENABLE_EEPROM 2 |
| 270 | #define AR_EEPROM_MODAL_SPURS 5 |
| 271 | #define AR_SPUR_5413_1 1640 |
| 272 | #define AR_SPUR_5413_2 1200 |
| 273 | #define AR_NO_SPUR 0x8000 |
| 274 | #define AR_BASE_FREQ_2GHZ 2300 |
| 275 | #define AR_BASE_FREQ_5GHZ 4900 |
| 276 | #define AR_SPUR_FEEQ_BOUND_HT40 19 |
| 277 | #define AR_SPUR_FEEQ_BOUND_HT20 10 |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 278 | int spurmode; |
| 279 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 280 | }; |
| 281 | |
| 282 | enum ath9k_tx_queue { |
| 283 | ATH9K_TX_QUEUE_INACTIVE = 0, |
| 284 | ATH9K_TX_QUEUE_DATA, |
| 285 | ATH9K_TX_QUEUE_BEACON, |
| 286 | ATH9K_TX_QUEUE_CAB, |
| 287 | ATH9K_TX_QUEUE_UAPSD, |
| 288 | ATH9K_TX_QUEUE_PSPOLL |
| 289 | }; |
| 290 | |
| 291 | #define ATH9K_NUM_TX_QUEUES 10 |
| 292 | |
| 293 | enum ath9k_tx_queue_subtype { |
| 294 | ATH9K_WME_AC_BK = 0, |
| 295 | ATH9K_WME_AC_BE, |
| 296 | ATH9K_WME_AC_VI, |
| 297 | ATH9K_WME_AC_VO, |
| 298 | ATH9K_WME_UPSD |
| 299 | }; |
| 300 | |
| 301 | enum ath9k_tx_queue_flags { |
| 302 | TXQ_FLAG_TXOKINT_ENABLE = 0x0001, |
| 303 | TXQ_FLAG_TXERRINT_ENABLE = 0x0001, |
| 304 | TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, |
| 305 | TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, |
| 306 | TXQ_FLAG_TXURNINT_ENABLE = 0x0008, |
| 307 | TXQ_FLAG_BACKOFF_DISABLE = 0x0010, |
| 308 | TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, |
| 309 | TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, |
| 310 | TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, |
| 311 | }; |
| 312 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 313 | #define ATH9K_TXQ_USEDEFAULT ((u32) -1) |
| 314 | |
| 315 | #define ATH9K_DECOMP_MASK_SIZE 128 |
| 316 | #define ATH9K_READY_TIME_LO_BOUND 50 |
| 317 | #define ATH9K_READY_TIME_HI_BOUND 96 |
| 318 | |
| 319 | enum ath9k_pkt_type { |
| 320 | ATH9K_PKT_TYPE_NORMAL = 0, |
| 321 | ATH9K_PKT_TYPE_ATIM, |
| 322 | ATH9K_PKT_TYPE_PSPOLL, |
| 323 | ATH9K_PKT_TYPE_BEACON, |
| 324 | ATH9K_PKT_TYPE_PROBE_RESP, |
| 325 | ATH9K_PKT_TYPE_CHIRP, |
| 326 | ATH9K_PKT_TYPE_GRP_POLL, |
| 327 | }; |
| 328 | |
| 329 | struct ath9k_tx_queue_info { |
| 330 | u32 tqi_ver; |
| 331 | enum ath9k_tx_queue tqi_type; |
| 332 | enum ath9k_tx_queue_subtype tqi_subtype; |
| 333 | enum ath9k_tx_queue_flags tqi_qflags; |
| 334 | u32 tqi_priority; |
| 335 | u32 tqi_aifs; |
| 336 | u32 tqi_cwmin; |
| 337 | u32 tqi_cwmax; |
| 338 | u16 tqi_shretry; |
| 339 | u16 tqi_lgretry; |
| 340 | u32 tqi_cbrPeriod; |
| 341 | u32 tqi_cbrOverflowLimit; |
| 342 | u32 tqi_burstTime; |
| 343 | u32 tqi_readyTime; |
| 344 | u32 tqi_physCompBuf; |
| 345 | u32 tqi_intFlags; |
| 346 | }; |
| 347 | |
| 348 | enum ath9k_rx_filter { |
| 349 | ATH9K_RX_FILTER_UCAST = 0x00000001, |
| 350 | ATH9K_RX_FILTER_MCAST = 0x00000002, |
| 351 | ATH9K_RX_FILTER_BCAST = 0x00000004, |
| 352 | ATH9K_RX_FILTER_CONTROL = 0x00000008, |
| 353 | ATH9K_RX_FILTER_BEACON = 0x00000010, |
| 354 | ATH9K_RX_FILTER_PROM = 0x00000020, |
| 355 | ATH9K_RX_FILTER_PROBEREQ = 0x00000080, |
| 356 | ATH9K_RX_FILTER_PSPOLL = 0x00004000, |
| 357 | ATH9K_RX_FILTER_PHYERR = 0x00000100, |
| 358 | ATH9K_RX_FILTER_PHYRADAR = 0x00002000, |
| 359 | }; |
| 360 | |
| 361 | enum ath9k_int { |
| 362 | ATH9K_INT_RX = 0x00000001, |
| 363 | ATH9K_INT_RXDESC = 0x00000002, |
| 364 | ATH9K_INT_RXNOFRM = 0x00000008, |
| 365 | ATH9K_INT_RXEOL = 0x00000010, |
| 366 | ATH9K_INT_RXORN = 0x00000020, |
| 367 | ATH9K_INT_TX = 0x00000040, |
| 368 | ATH9K_INT_TXDESC = 0x00000080, |
| 369 | ATH9K_INT_TIM_TIMER = 0x00000100, |
| 370 | ATH9K_INT_TXURN = 0x00000800, |
| 371 | ATH9K_INT_MIB = 0x00001000, |
| 372 | ATH9K_INT_RXPHY = 0x00004000, |
| 373 | ATH9K_INT_RXKCM = 0x00008000, |
| 374 | ATH9K_INT_SWBA = 0x00010000, |
| 375 | ATH9K_INT_BMISS = 0x00040000, |
| 376 | ATH9K_INT_BNR = 0x00100000, |
| 377 | ATH9K_INT_TIM = 0x00200000, |
| 378 | ATH9K_INT_DTIM = 0x00400000, |
| 379 | ATH9K_INT_DTIMSYNC = 0x00800000, |
| 380 | ATH9K_INT_GPIO = 0x01000000, |
| 381 | ATH9K_INT_CABEND = 0x02000000, |
| 382 | ATH9K_INT_CST = 0x10000000, |
| 383 | ATH9K_INT_GTT = 0x20000000, |
| 384 | ATH9K_INT_FATAL = 0x40000000, |
| 385 | ATH9K_INT_GLOBAL = 0x80000000, |
| 386 | ATH9K_INT_BMISC = ATH9K_INT_TIM | |
| 387 | ATH9K_INT_DTIM | |
| 388 | ATH9K_INT_DTIMSYNC | |
| 389 | ATH9K_INT_CABEND, |
| 390 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | |
| 391 | ATH9K_INT_RXDESC | |
| 392 | ATH9K_INT_RXEOL | |
| 393 | ATH9K_INT_RXORN | |
| 394 | ATH9K_INT_TXURN | |
| 395 | ATH9K_INT_TXDESC | |
| 396 | ATH9K_INT_MIB | |
| 397 | ATH9K_INT_RXPHY | |
| 398 | ATH9K_INT_RXKCM | |
| 399 | ATH9K_INT_SWBA | |
| 400 | ATH9K_INT_BMISS | |
| 401 | ATH9K_INT_GPIO, |
| 402 | ATH9K_INT_NOCARD = 0xffffffff |
| 403 | }; |
| 404 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 405 | #define ATH9K_RATESERIES_RTS_CTS 0x0001 |
| 406 | #define ATH9K_RATESERIES_2040 0x0002 |
| 407 | #define ATH9K_RATESERIES_HALFGI 0x0004 |
| 408 | |
| 409 | struct ath9k_11n_rate_series { |
| 410 | u32 Tries; |
| 411 | u32 Rate; |
| 412 | u32 PktDuration; |
| 413 | u32 ChSel; |
| 414 | u32 RateFlags; |
| 415 | }; |
| 416 | |
| 417 | #define CHANNEL_CW_INT 0x00002 |
| 418 | #define CHANNEL_CCK 0x00020 |
| 419 | #define CHANNEL_OFDM 0x00040 |
| 420 | #define CHANNEL_2GHZ 0x00080 |
| 421 | #define CHANNEL_5GHZ 0x00100 |
| 422 | #define CHANNEL_PASSIVE 0x00200 |
| 423 | #define CHANNEL_DYN 0x00400 |
| 424 | #define CHANNEL_HALF 0x04000 |
| 425 | #define CHANNEL_QUARTER 0x08000 |
| 426 | #define CHANNEL_HT20 0x10000 |
| 427 | #define CHANNEL_HT40PLUS 0x20000 |
| 428 | #define CHANNEL_HT40MINUS 0x40000 |
| 429 | |
| 430 | #define CHANNEL_INTERFERENCE 0x01 |
| 431 | #define CHANNEL_DFS 0x02 |
| 432 | #define CHANNEL_4MS_LIMIT 0x04 |
| 433 | #define CHANNEL_DFS_CLEAR 0x08 |
| 434 | #define CHANNEL_DISALLOW_ADHOC 0x10 |
| 435 | #define CHANNEL_PER_11D_ADHOC 0x20 |
| 436 | |
| 437 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
| 438 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
| 439 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
| 440 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) |
| 441 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) |
| 442 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) |
| 443 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) |
| 444 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) |
| 445 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) |
| 446 | #define CHANNEL_ALL \ |
| 447 | (CHANNEL_OFDM| \ |
| 448 | CHANNEL_CCK| \ |
| 449 | CHANNEL_2GHZ | \ |
| 450 | CHANNEL_5GHZ | \ |
| 451 | CHANNEL_HT20 | \ |
| 452 | CHANNEL_HT40PLUS | \ |
| 453 | CHANNEL_HT40MINUS) |
| 454 | |
| 455 | struct ath9k_channel { |
| 456 | u16 channel; |
| 457 | u32 channelFlags; |
| 458 | u8 privFlags; |
| 459 | int8_t maxRegTxPower; |
| 460 | int8_t maxTxPower; |
| 461 | int8_t minTxPower; |
| 462 | u32 chanmode; |
| 463 | int32_t CalValid; |
| 464 | bool oneTimeCalsDone; |
| 465 | int8_t iCoff; |
| 466 | int8_t qCoff; |
| 467 | int16_t rawNoiseFloor; |
| 468 | int8_t antennaMax; |
| 469 | u32 regDmnFlags; |
| 470 | u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */ |
| 471 | #ifdef ATH_NF_PER_CHAN |
| 472 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
| 473 | #endif |
| 474 | }; |
| 475 | |
| 476 | #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \ |
| 477 | (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \ |
| 478 | (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \ |
| 479 | (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 480 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
| 481 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ |
| 482 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ |
| 483 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 484 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) |
| 485 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) |
| 486 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) |
| 487 | #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0) |
| 488 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
| 489 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) |
| 490 | |
| 491 | /* These macros check chanmode and not channelFlags */ |
Sujith | 788a3d6 | 2008-11-18 09:09:54 +0530 | [diff] [blame] | 492 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 493 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ |
| 494 | ((_c)->chanmode == CHANNEL_G_HT20)) |
| 495 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ |
| 496 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ |
| 497 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ |
| 498 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) |
| 499 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) |
| 500 | |
| 501 | #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990) |
| 502 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ |
| 503 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ |
| 504 | (((_c)->channel % 20) != 0) && \ |
| 505 | (((_c)->channel % 10) != 0)) |
| 506 | |
| 507 | struct ath9k_keyval { |
| 508 | u8 kv_type; |
| 509 | u8 kv_pad; |
| 510 | u16 kv_len; |
| 511 | u8 kv_val[16]; |
| 512 | u8 kv_mic[8]; |
| 513 | u8 kv_txmic[8]; |
| 514 | }; |
| 515 | |
| 516 | enum ath9k_key_type { |
| 517 | ATH9K_KEY_TYPE_CLEAR, |
| 518 | ATH9K_KEY_TYPE_WEP, |
| 519 | ATH9K_KEY_TYPE_AES, |
| 520 | ATH9K_KEY_TYPE_TKIP, |
| 521 | }; |
| 522 | |
| 523 | enum ath9k_cipher { |
| 524 | ATH9K_CIPHER_WEP = 0, |
| 525 | ATH9K_CIPHER_AES_OCB = 1, |
| 526 | ATH9K_CIPHER_AES_CCM = 2, |
| 527 | ATH9K_CIPHER_CKIP = 3, |
| 528 | ATH9K_CIPHER_TKIP = 4, |
| 529 | ATH9K_CIPHER_CLR = 5, |
| 530 | ATH9K_CIPHER_MIC = 127 |
| 531 | }; |
| 532 | |
| 533 | #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 |
| 534 | #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 |
| 535 | #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 |
| 536 | #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 |
| 537 | #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 |
| 538 | #define AR_EEPROM_EEPCAP_MAXQCU_S 4 |
| 539 | #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 |
| 540 | #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 |
| 541 | #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 |
| 542 | |
| 543 | #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 |
| 544 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 |
| 545 | #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 |
| 546 | #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 |
| 547 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 |
| 548 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 |
| 549 | |
| 550 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 |
| 551 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 |
| 552 | |
| 553 | #define SD_NO_CTL 0xE0 |
| 554 | #define NO_CTL 0xff |
| 555 | #define CTL_MODE_M 7 |
| 556 | #define CTL_11A 0 |
| 557 | #define CTL_11B 1 |
| 558 | #define CTL_11G 2 |
| 559 | #define CTL_2GHT20 5 |
| 560 | #define CTL_5GHT20 6 |
| 561 | #define CTL_2GHT40 7 |
| 562 | #define CTL_5GHT40 8 |
| 563 | |
| 564 | #define AR_EEPROM_MAC(i) (0x1d+(i)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 565 | |
| 566 | #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c |
| 567 | #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 |
| 568 | #define AR_EEPROM_RFSILENT_POLARITY 0x0002 |
| 569 | #define AR_EEPROM_RFSILENT_POLARITY_S 1 |
| 570 | |
| 571 | #define CTRY_DEBUG 0x1ff |
| 572 | #define CTRY_DEFAULT 0 |
| 573 | |
| 574 | enum reg_ext_bitmap { |
| 575 | REG_EXT_JAPAN_MIDBAND = 1, |
| 576 | REG_EXT_FCC_DFS_HT40 = 2, |
| 577 | REG_EXT_JAPAN_NONDFS_HT40 = 3, |
| 578 | REG_EXT_JAPAN_DFS_HT40 = 4 |
| 579 | }; |
| 580 | |
| 581 | struct ath9k_country_entry { |
| 582 | u16 countryCode; |
| 583 | u16 regDmnEnum; |
| 584 | u16 regDmn5G; |
| 585 | u16 regDmn2G; |
| 586 | u8 isMultidomain; |
| 587 | u8 iso[3]; |
| 588 | }; |
| 589 | |
| 590 | #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) |
| 591 | #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) |
| 592 | |
| 593 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
| 594 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) |
| 595 | #define REG_RMW(_a, _r, _set, _clr) \ |
| 596 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) |
| 597 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ |
| 598 | REG_WRITE(_a, _r, \ |
| 599 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) |
| 600 | #define REG_SET_BIT(_a, _r, _f) \ |
| 601 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) |
| 602 | #define REG_CLR_BIT(_a, _r, _f) \ |
| 603 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) |
| 604 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 605 | #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 |
| 606 | |
| 607 | #define INIT_AIFS 2 |
| 608 | #define INIT_CWMIN 15 |
| 609 | #define INIT_CWMIN_11B 31 |
| 610 | #define INIT_CWMAX 1023 |
| 611 | #define INIT_SH_RETRY 10 |
| 612 | #define INIT_LG_RETRY 10 |
| 613 | #define INIT_SSH_RETRY 32 |
| 614 | #define INIT_SLG_RETRY 32 |
| 615 | |
| 616 | #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) |
| 617 | |
| 618 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
| 619 | #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX |
| 620 | |
| 621 | #define IEEE80211_WEP_IVLEN 3 |
| 622 | #define IEEE80211_WEP_KIDLEN 1 |
| 623 | #define IEEE80211_WEP_CRCLEN 4 |
| 624 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ |
| 625 | (IEEE80211_WEP_IVLEN + \ |
| 626 | IEEE80211_WEP_KIDLEN + \ |
| 627 | IEEE80211_WEP_CRCLEN)) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 628 | #define MAX_RATE_POWER 63 |
| 629 | |
| 630 | enum ath9k_power_mode { |
| 631 | ATH9K_PM_AWAKE = 0, |
| 632 | ATH9K_PM_FULL_SLEEP, |
| 633 | ATH9K_PM_NETWORK_SLEEP, |
| 634 | ATH9K_PM_UNDEFINED |
| 635 | }; |
| 636 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 637 | struct ath9k_mib_stats { |
| 638 | u32 ackrcv_bad; |
| 639 | u32 rts_bad; |
| 640 | u32 rts_good; |
| 641 | u32 fcs_bad; |
| 642 | u32 beacons; |
| 643 | }; |
| 644 | |
| 645 | enum ath9k_ant_setting { |
| 646 | ATH9K_ANT_VARIABLE = 0, |
| 647 | ATH9K_ANT_FIXED_A, |
| 648 | ATH9K_ANT_FIXED_B |
| 649 | }; |
| 650 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 651 | #define ATH9K_SLOT_TIME_6 6 |
| 652 | #define ATH9K_SLOT_TIME_9 9 |
| 653 | #define ATH9K_SLOT_TIME_20 20 |
| 654 | |
| 655 | enum ath9k_ht_macmode { |
| 656 | ATH9K_HT_MACMODE_20 = 0, |
| 657 | ATH9K_HT_MACMODE_2040 = 1, |
| 658 | }; |
| 659 | |
| 660 | enum ath9k_ht_extprotspacing { |
| 661 | ATH9K_HT_EXTPROTSPACING_20 = 0, |
| 662 | ATH9K_HT_EXTPROTSPACING_25 = 1, |
| 663 | }; |
| 664 | |
| 665 | struct ath9k_ht_cwm { |
| 666 | enum ath9k_ht_macmode ht_macmode; |
| 667 | enum ath9k_ht_extprotspacing ht_extprotspacing; |
| 668 | }; |
| 669 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 670 | enum ath9k_ani_cmd { |
| 671 | ATH9K_ANI_PRESENT = 0x1, |
| 672 | ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, |
| 673 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, |
| 674 | ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, |
| 675 | ATH9K_ANI_FIRSTEP_LEVEL = 0x10, |
| 676 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, |
| 677 | ATH9K_ANI_MODE = 0x40, |
| 678 | ATH9K_ANI_PHYERR_RESET = 0x80, |
| 679 | ATH9K_ANI_ALL = 0xff |
| 680 | }; |
| 681 | |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 682 | enum { |
| 683 | WLAN_RC_PHY_OFDM, |
| 684 | WLAN_RC_PHY_CCK, |
| 685 | WLAN_RC_PHY_HT_20_SS, |
| 686 | WLAN_RC_PHY_HT_20_DS, |
| 687 | WLAN_RC_PHY_HT_40_SS, |
| 688 | WLAN_RC_PHY_HT_40_DS, |
| 689 | WLAN_RC_PHY_HT_20_SS_HGI, |
| 690 | WLAN_RC_PHY_HT_20_DS_HGI, |
| 691 | WLAN_RC_PHY_HT_40_SS_HGI, |
| 692 | WLAN_RC_PHY_HT_40_DS_HGI, |
| 693 | WLAN_RC_PHY_MAX |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 694 | }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 695 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 696 | enum ath9k_tp_scale { |
| 697 | ATH9K_TP_SCALE_MAX = 0, |
| 698 | ATH9K_TP_SCALE_50, |
| 699 | ATH9K_TP_SCALE_25, |
| 700 | ATH9K_TP_SCALE_12, |
| 701 | ATH9K_TP_SCALE_MIN |
| 702 | }; |
| 703 | |
| 704 | enum ser_reg_mode { |
| 705 | SER_REG_MODE_OFF = 0, |
| 706 | SER_REG_MODE_ON = 1, |
| 707 | SER_REG_MODE_AUTO = 2, |
| 708 | }; |
| 709 | |
| 710 | #define AR_PHY_CCA_MAX_GOOD_VALUE -85 |
| 711 | #define AR_PHY_CCA_MAX_HIGH_VALUE -62 |
| 712 | #define AR_PHY_CCA_MIN_BAD_VALUE -121 |
| 713 | #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3 |
| 714 | #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5 |
| 715 | |
| 716 | #define ATH9K_NF_CAL_HIST_MAX 5 |
| 717 | #define NUM_NF_READINGS 6 |
| 718 | |
| 719 | struct ath9k_nfcal_hist { |
| 720 | int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; |
| 721 | u8 currIndex; |
| 722 | int16_t privNF; |
| 723 | u8 invalidNFcount; |
| 724 | }; |
| 725 | |
| 726 | struct ath9k_beacon_state { |
| 727 | u32 bs_nexttbtt; |
| 728 | u32 bs_nextdtim; |
| 729 | u32 bs_intval; |
| 730 | #define ATH9K_BEACON_PERIOD 0x0000ffff |
| 731 | #define ATH9K_BEACON_ENA 0x00800000 |
| 732 | #define ATH9K_BEACON_RESET_TSF 0x01000000 |
| 733 | u32 bs_dtimperiod; |
| 734 | u16 bs_cfpperiod; |
| 735 | u16 bs_cfpmaxduration; |
| 736 | u32 bs_cfpnext; |
| 737 | u16 bs_timoffset; |
| 738 | u16 bs_bmissthreshold; |
| 739 | u32 bs_sleepduration; |
| 740 | }; |
| 741 | |
| 742 | struct ath9k_node_stats { |
| 743 | u32 ns_avgbrssi; |
| 744 | u32 ns_avgrssi; |
| 745 | u32 ns_avgtxrssi; |
| 746 | u32 ns_avgtxrate; |
| 747 | }; |
| 748 | |
| 749 | #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) |
| 750 | |
Vasanthakumar Thiagarajan | c83be68 | 2008-08-25 20:47:29 +0530 | [diff] [blame] | 751 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
| 752 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 |
| 753 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 |
| 754 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
| 755 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 756 | |
| 757 | enum { |
| 758 | ATH9K_RESET_POWER_ON, |
| 759 | ATH9K_RESET_WARM, |
| 760 | ATH9K_RESET_COLD, |
| 761 | }; |
| 762 | |
| 763 | #define AH_USE_EEPROM 0x1 |
| 764 | |
| 765 | struct ath_hal { |
| 766 | u32 ah_magic; |
| 767 | u16 ah_devid; |
| 768 | u16 ah_subvendorid; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 769 | u32 ah_macVersion; |
| 770 | u16 ah_macRev; |
| 771 | u16 ah_phyRev; |
| 772 | u16 ah_analog5GhzRev; |
| 773 | u16 ah_analog2GhzRev; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 774 | |
| 775 | void __iomem *ah_sh; |
| 776 | struct ath_softc *ah_sc; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 777 | |
| 778 | enum nl80211_iftype ah_opmode; |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 779 | struct ath9k_ops_config ah_config; |
| 780 | struct ath9k_hw_capabilities ah_caps; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 781 | |
| 782 | u16 ah_countryCode; |
| 783 | u32 ah_flags; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 784 | int16_t ah_powerLimit; |
| 785 | u16 ah_maxPowerLevel; |
| 786 | u32 ah_tpScale; |
| 787 | u16 ah_currentRD; |
| 788 | u16 ah_currentRDExt; |
| 789 | u16 ah_currentRDInUse; |
| 790 | u16 ah_currentRD5G; |
| 791 | u16 ah_currentRD2G; |
| 792 | char ah_iso[4]; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 793 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 794 | struct ath9k_channel ah_channels[150]; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 795 | struct ath9k_channel *ah_curchan; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 796 | u32 ah_nchan; |
| 797 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 798 | bool ah_isPciExpress; |
| 799 | u16 ah_txTrigLevel; |
Vasanthakumar Thiagarajan | 500c064 | 2008-09-10 18:50:17 +0530 | [diff] [blame] | 800 | u16 ah_rfsilent; |
| 801 | u32 ah_rfkill_gpio; |
| 802 | u32 ah_rfkill_polarity; |
Sujith | 6a2b9e8 | 2008-08-11 14:04:32 +0530 | [diff] [blame] | 803 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 804 | #ifndef ATH_NF_PER_CHAN |
| 805 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
| 806 | #endif |
| 807 | }; |
| 808 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 809 | struct chan_centers { |
| 810 | u16 synth_center; |
| 811 | u16 ctl_center; |
| 812 | u16 ext_center; |
| 813 | }; |
| 814 | |
Sujith | e63835b | 2008-11-18 09:07:53 +0530 | [diff] [blame] | 815 | struct ath_rate_table; |
| 816 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 817 | /* Helpers */ |
| 818 | |
| 819 | enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah, |
| 820 | const struct ath9k_channel *chan); |
| 821 | bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); |
| 822 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
| 823 | bool ath9k_get_channel_edges(struct ath_hal *ah, |
| 824 | u16 flags, u16 *low, |
| 825 | u16 *high); |
| 826 | u16 ath9k_hw_computetxtime(struct ath_hal *ah, |
Sujith | e63835b | 2008-11-18 09:07:53 +0530 | [diff] [blame] | 827 | struct ath_rate_table *rates, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 828 | u32 frameLen, u16 rateix, |
| 829 | bool shortPreamble); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 830 | u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 831 | void ath9k_hw_get_channel_centers(struct ath_hal *ah, |
| 832 | struct ath9k_channel *chan, |
| 833 | struct chan_centers *centers); |
| 834 | |
| 835 | /* Attach, Detach */ |
| 836 | |
| 837 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
| 838 | void ath9k_hw_detach(struct ath_hal *ah); |
| 839 | struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, |
| 840 | void __iomem *mem, int *error); |
| 841 | void ath9k_hw_rfdetach(struct ath_hal *ah); |
| 842 | |
| 843 | |
| 844 | /* HW Reset */ |
| 845 | |
| 846 | bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 847 | enum ath9k_ht_macmode macmode, |
| 848 | u8 txchainmask, u8 rxchainmask, |
| 849 | enum ath9k_ht_extprotspacing extprotspacing, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 850 | bool bChannelChange, int *status); |
| 851 | |
| 852 | /* Key Cache Management */ |
| 853 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 854 | bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 855 | bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac); |
| 856 | bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry, |
| 857 | const struct ath9k_keyval *k, |
| 858 | const u8 *mac, int xorKey); |
| 859 | bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry); |
| 860 | |
| 861 | /* Power Management */ |
| 862 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 863 | bool ath9k_hw_setpower(struct ath_hal *ah, |
| 864 | enum ath9k_power_mode mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 865 | void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore); |
| 866 | |
| 867 | /* Beacon timers */ |
| 868 | |
| 869 | void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period); |
| 870 | void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah, |
| 871 | const struct ath9k_beacon_state *bs); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 872 | /* HW Capabilities */ |
| 873 | |
| 874 | bool ath9k_hw_fill_cap_info(struct ath_hal *ah); |
| 875 | bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type, |
| 876 | u32 capability, u32 *result); |
| 877 | bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type, |
| 878 | u32 capability, u32 setting, int *status); |
| 879 | |
| 880 | /* GPIO / RFKILL / Antennae */ |
| 881 | |
| 882 | void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); |
| 883 | u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); |
| 884 | void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, |
| 885 | u32 ah_signal_type); |
| 886 | void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); |
Senthil Balasubramanian | e97275c | 2008-11-13 18:00:02 +0530 | [diff] [blame] | 887 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 888 | void ath9k_enable_rfkill(struct ath_hal *ah); |
| 889 | #endif |
| 890 | int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 891 | u32 ath9k_hw_getdefantenna(struct ath_hal *ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 892 | void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 893 | bool ath9k_hw_setantennaswitch(struct ath_hal *ah, |
| 894 | enum ath9k_ant_setting settings, |
| 895 | struct ath9k_channel *chan, |
| 896 | u8 *tx_chainmask, |
| 897 | u8 *rx_chainmask, |
| 898 | u8 *antenna_cfgd); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 899 | |
| 900 | /* General Operation */ |
| 901 | |
| 902 | u32 ath9k_hw_getrxfilter(struct ath_hal *ah); |
| 903 | void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits); |
| 904 | bool ath9k_hw_phy_disable(struct ath_hal *ah); |
| 905 | bool ath9k_hw_disable(struct ath_hal *ah); |
| 906 | bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit); |
| 907 | void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac); |
| 908 | bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac); |
| 909 | void ath9k_hw_setopmode(struct ath_hal *ah); |
| 910 | void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1); |
| 911 | void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask); |
| 912 | bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask); |
| 913 | void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId); |
| 914 | u64 ath9k_hw_gettsf64(struct ath_hal *ah); |
| 915 | void ath9k_hw_reset_tsf(struct ath_hal *ah); |
| 916 | bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting); |
| 917 | bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us); |
| 918 | void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode); |
| 919 | |
| 920 | /* Regulatory */ |
| 921 | |
| 922 | bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah); |
| 923 | struct ath9k_channel* ath9k_regd_check_channel(struct ath_hal *ah, |
| 924 | const struct ath9k_channel *c); |
| 925 | u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan); |
| 926 | u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah, |
| 927 | struct ath9k_channel *chan); |
| 928 | bool ath9k_regd_init_channels(struct ath_hal *ah, |
| 929 | u32 maxchans, u32 *nchans, u8 *regclassids, |
| 930 | u32 maxregids, u32 *nregids, u16 cc, |
| 931 | bool enableOutdoor, bool enableExtendedChannels); |
| 932 | |
| 933 | /* ANI */ |
| 934 | |
| 935 | void ath9k_ani_reset(struct ath_hal *ah); |
| 936 | void ath9k_hw_ani_monitor(struct ath_hal *ah, |
| 937 | const struct ath9k_node_stats *stats, |
| 938 | struct ath9k_channel *chan); |
| 939 | bool ath9k_hw_phycounters(struct ath_hal *ah); |
| 940 | void ath9k_enable_mib_counters(struct ath_hal *ah); |
| 941 | void ath9k_hw_disable_mib_counters(struct ath_hal *ah); |
| 942 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, |
| 943 | u32 *rxc_pcnt, |
| 944 | u32 *rxf_pcnt, |
| 945 | u32 *txf_pcnt); |
| 946 | void ath9k_hw_procmibevent(struct ath_hal *ah, |
| 947 | const struct ath9k_node_stats *stats); |
| 948 | void ath9k_hw_ani_setup(struct ath_hal *ah); |
| 949 | void ath9k_hw_ani_attach(struct ath_hal *ah); |
| 950 | void ath9k_hw_ani_detach(struct ath_hal *ah); |
| 951 | |
| 952 | /* Calibration */ |
| 953 | |
| 954 | void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan, |
| 955 | bool *isCalDone); |
| 956 | void ath9k_hw_start_nfcal(struct ath_hal *ah); |
| 957 | void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan); |
| 958 | int16_t ath9k_hw_getnf(struct ath_hal *ah, |
| 959 | struct ath9k_channel *chan); |
| 960 | void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah); |
| 961 | s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan); |
| 962 | bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, |
| 963 | u8 rxchainmask, bool longcal, |
| 964 | bool *isCalDone); |
| 965 | bool ath9k_hw_init_cal(struct ath_hal *ah, |
| 966 | struct ath9k_channel *chan); |
| 967 | |
| 968 | |
| 969 | /* EEPROM */ |
| 970 | |
| 971 | int ath9k_hw_set_txpower(struct ath_hal *ah, |
| 972 | struct ath9k_channel *chan, |
| 973 | u16 cfgCtl, |
| 974 | u8 twiceAntennaReduction, |
| 975 | u8 twiceMaxRegulatoryPower, |
| 976 | u8 powerLimit); |
| 977 | void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan); |
| 978 | bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, |
| 979 | struct ath9k_channel *chan, |
| 980 | int16_t *ratesArray, |
| 981 | u16 cfgCtl, |
| 982 | u8 AntennaReduction, |
| 983 | u8 twiceMaxRegulatoryPower, |
| 984 | u8 powerLimit); |
| 985 | bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, |
| 986 | struct ath9k_channel *chan, |
| 987 | int16_t *pTxPowerIndexOffset); |
| 988 | bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, |
| 989 | struct ath9k_channel *chan); |
| 990 | int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, |
| 991 | struct ath9k_channel *chan, |
| 992 | u8 index, u16 *config); |
| 993 | u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, |
| 994 | enum ieee80211_band freq_band); |
| 995 | u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz); |
| 996 | int ath9k_hw_eeprom_attach(struct ath_hal *ah); |
| 997 | |
| 998 | /* Interrupt Handling */ |
| 999 | |
| 1000 | bool ath9k_hw_intrpend(struct ath_hal *ah); |
| 1001 | bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked); |
| 1002 | enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah); |
| 1003 | enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints); |
| 1004 | |
| 1005 | /* MAC (PCU/QCU) */ |
| 1006 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1007 | u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q); |
| 1008 | bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1009 | bool ath9k_hw_txstart(struct ath_hal *ah, u32 q); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1010 | u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q); |
| 1011 | bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel); |
| 1012 | bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q); |
| 1013 | bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds, |
| 1014 | u32 segLen, bool firstSeg, |
| 1015 | bool lastSeg, const struct ath_desc *ds0); |
| 1016 | void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds); |
| 1017 | int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds); |
| 1018 | void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds, |
| 1019 | u32 pktLen, enum ath9k_pkt_type type, u32 txPower, |
| 1020 | u32 keyIx, enum ath9k_key_type keyType, u32 flags); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1021 | void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds, |
| 1022 | struct ath_desc *lastds, |
| 1023 | u32 durUpdateEn, u32 rtsctsRate, |
| 1024 | u32 rtsctsDuration, |
| 1025 | struct ath9k_11n_rate_series series[], |
| 1026 | u32 nseries, u32 flags); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1027 | void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds, |
| 1028 | u32 aggrLen); |
| 1029 | void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds, |
| 1030 | u32 numDelims); |
| 1031 | void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds); |
| 1032 | void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds); |
| 1033 | void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds, |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1034 | u32 burstDuration); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1035 | void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds, |
| 1036 | u32 vmf); |
| 1037 | void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs); |
Sujith | ea9880f | 2008-08-07 10:53:10 +0530 | [diff] [blame] | 1038 | bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q, |
| 1039 | const struct ath9k_tx_queue_info *qinfo); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1040 | bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q, |
| 1041 | struct ath9k_tx_queue_info *qinfo); |
| 1042 | int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type, |
| 1043 | const struct ath9k_tx_queue_info *qinfo); |
| 1044 | bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q); |
| 1045 | bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q); |
| 1046 | int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds, |
| 1047 | u32 pa, struct ath_desc *nds, u64 tsf); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1048 | bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds, |
| 1049 | u32 size, u32 flags); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1050 | bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1051 | void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp); |
| 1052 | void ath9k_hw_rxena(struct ath_hal *ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1053 | void ath9k_hw_startpcureceive(struct ath_hal *ah); |
| 1054 | void ath9k_hw_stoppcurecv(struct ath_hal *ah); |
| 1055 | bool ath9k_hw_stopdmarecv(struct ath_hal *ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1056 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1057 | #endif |