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gerrit-public.fairphone.software / kernel / msm-4.9 / e7c329a0a94b6bd7743a04f7f4309ad693f7a112 / . / drivers / media / i2c / smiapp-pll.h
blob: e8f035a50c76bba8cb7bcf9884020138da24c734 [file] [log] [blame]
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]1/*
Mauro Carvalho Chehabcb7a01a2012-08-14 16:23:43 -0300[diff] [blame]2 * drivers/media/i2c/smiapp-pll.h
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]3 *
4 * Generic driver for SMIA/SMIA++ compliant camera modules
5 *
6 * Copyright (C) 2012 Nokia Corporation
Sakari Ailus8c5dff92012-10-28 06:44:17 -0300[diff] [blame]7 * Contact: Sakari Ailus <sakari.ailus@iki.fi>
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef SMIAPP_PLL_H
26#define SMIAPP_PLL_H
27
28#include <linux/device.h>
29
Sakari Ailusf5984bb2012-10-20 10:35:25 -0300[diff] [blame]30/* CSI-2 or CCP-2 */
31#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
32#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
33
34/* op pix clock is for all lanes in total normally */
35#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
36#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
37
Sakari Ailuse3f8bc82014-09-16 09:07:11 -0300[diff] [blame]38struct smiapp_pll_branch {
39 uint16_t sys_clk_div;
40 uint16_t pix_clk_div;
41 uint32_t sys_clk_freq_hz;
42 uint32_t pix_clk_freq_hz;
43};
44
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]45struct smiapp_pll {
Sakari Ailusf5984bb2012-10-20 10:35:25 -0300[diff] [blame]46 /* input values */
47 uint8_t bus_type;
48 union {
49 struct {
50 uint8_t lanes;
51 } csi2;
52 struct {
53 uint8_t bus_width;
54 } parallel;
55 };
Sakari Ailus19e9f5f2014-04-08 18:14:42 -0300[diff] [blame]56 unsigned long flags;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]57 uint8_t binning_horizontal;
58 uint8_t binning_vertical;
59 uint8_t scale_m;
60 uint8_t scale_n;
61 uint8_t bits_per_pixel;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]62 uint32_t link_freq;
Sakari Ailusfff888c2014-09-16 09:04:35 -0300[diff] [blame]63 uint32_t ext_clk_freq_hz;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]64
Sakari Ailusf5984bb2012-10-20 10:35:25 -0300[diff] [blame]65 /* output values */
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]66 uint16_t pre_pll_clk_div;
67 uint16_t pll_multiplier;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]68 uint32_t pll_ip_clk_freq_hz;
69 uint32_t pll_op_clk_freq_hz;
Sakari Ailuse3f8bc82014-09-16 09:07:11 -0300[diff] [blame]70 struct smiapp_pll_branch vt;
71 struct smiapp_pll_branch op;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]72
73 uint32_t pixel_rate_csi;
Sakari Ailuse7c329a2014-04-01 19:18:09 -0300[diff] [blame^]74 uint32_t pixel_rate_pixel_array;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]75};
76
Laurent Pinchart6ec84a22012-10-22 11:40:56 -0300[diff] [blame]77struct smiapp_pll_branch_limits {
78 uint16_t min_sys_clk_div;
79 uint16_t max_sys_clk_div;
80 uint32_t min_sys_clk_freq_hz;
81 uint32_t max_sys_clk_freq_hz;
82 uint16_t min_pix_clk_div;
83 uint16_t max_pix_clk_div;
84 uint32_t min_pix_clk_freq_hz;
85 uint32_t max_pix_clk_freq_hz;
86};
87
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]88struct smiapp_pll_limits {
89 /* Strict PLL limits */
90 uint32_t min_ext_clk_freq_hz;
91 uint32_t max_ext_clk_freq_hz;
92 uint16_t min_pre_pll_clk_div;
93 uint16_t max_pre_pll_clk_div;
94 uint32_t min_pll_ip_freq_hz;
95 uint32_t max_pll_ip_freq_hz;
96 uint16_t min_pll_multiplier;
97 uint16_t max_pll_multiplier;
98 uint32_t min_pll_op_freq_hz;
99 uint32_t max_pll_op_freq_hz;
100
Laurent Pinchart6ec84a22012-10-22 11:40:56 -0300[diff] [blame]101 struct smiapp_pll_branch_limits vt;
102 struct smiapp_pll_branch_limits op;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]103
104 /* Other relevant limits */
105 uint32_t min_line_length_pck_bin;
106 uint32_t min_line_length_pck;
107};
108
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]109struct device;
110
Laurent Pinchart8f7e91a2012-10-22 11:40:57 -0300[diff] [blame]111int smiapp_pll_calculate(struct device *dev,
112 const struct smiapp_pll_limits *limits,
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]113 struct smiapp_pll *pll);
114
115#endif /* SMIAPP_PLL_H */