Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * ngene.c: nGene PCIe bridge driver |
| 3 | * |
| 4 | * Copyright (C) 2005-2007 Micronas |
| 5 | * |
| 6 | * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de> |
| 7 | * Modifications for new nGene firmware, |
| 8 | * support for EEPROM-copying, |
| 9 | * support for new dual DVB-S2 card prototype |
| 10 | * |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License |
| 14 | * version 2 only, as published by the Free Software Foundation. |
| 15 | * |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
| 26 | * 02110-1301, USA |
| 27 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html |
| 28 | */ |
| 29 | |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/init.h> |
| 32 | #include <linux/delay.h> |
| 33 | #include <linux/slab.h> |
| 34 | #include <linux/poll.h> |
| 35 | #include <asm/io.h> |
| 36 | #include <asm/div64.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/pci_ids.h> |
| 39 | #include <linux/smp_lock.h> |
| 40 | #include <linux/timer.h> |
| 41 | #include <linux/version.h> |
| 42 | #include <linux/byteorder/generic.h> |
| 43 | #include <linux/firmware.h> |
| 44 | |
| 45 | #include "ngene.h" |
| 46 | |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 47 | #include "stv6110x.h" |
| 48 | #include "stv090x.h" |
| 49 | #include "lnbh24.h" |
| 50 | |
Matthias Benesch | cf1b12f | 2009-12-23 05:55:02 -0300 | [diff] [blame] | 51 | static int one_adapter = 1; |
| 52 | module_param(one_adapter, int, 0444); |
| 53 | MODULE_PARM_DESC(one_adapter, "Use only one adapter."); |
| 54 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 55 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 56 | static int debug; |
| 57 | module_param(debug, int, 0444); |
| 58 | MODULE_PARM_DESC(debug, "Print debugging information."); |
| 59 | |
Oliver Endriss | 83f3c71 | 2009-12-19 04:54:44 -0300 | [diff] [blame] | 60 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
| 61 | |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 62 | #define COMMAND_TIMEOUT_WORKAROUND |
| 63 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 64 | #define dprintk if (debug) printk |
| 65 | |
| 66 | #define DEVICE_NAME "ngene" |
| 67 | |
| 68 | #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) |
| 69 | #define ngwritel(dat, adr) writel((dat), (char *)(dev->iomem + (adr))) |
| 70 | #define ngwriteb(dat, adr) writeb((dat), (char *)(dev->iomem + (adr))) |
| 71 | #define ngreadl(adr) readl(dev->iomem + (adr)) |
| 72 | #define ngreadb(adr) readb(dev->iomem + (adr)) |
| 73 | #define ngcpyto(adr, src, count) memcpy_toio((char *) \ |
| 74 | (dev->iomem + (adr)), (src), (count)) |
| 75 | #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), (char *) \ |
| 76 | (dev->iomem + (adr)), (count)) |
| 77 | |
| 78 | /****************************************************************************/ |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 79 | /* nGene interrupt handler **************************************************/ |
| 80 | /****************************************************************************/ |
| 81 | |
| 82 | static void event_tasklet(unsigned long data) |
| 83 | { |
| 84 | struct ngene *dev = (struct ngene *)data; |
| 85 | |
| 86 | while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) { |
| 87 | struct EVENT_BUFFER Event = |
| 88 | dev->EventQueue[dev->EventQueueReadIndex]; |
| 89 | dev->EventQueueReadIndex = |
| 90 | (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1); |
| 91 | |
| 92 | if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) |
| 93 | dev->TxEventNotify(dev, Event.TimeStamp); |
| 94 | if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) |
| 95 | dev->RxEventNotify(dev, Event.TimeStamp, |
| 96 | Event.RXCharacter); |
| 97 | } |
| 98 | } |
| 99 | |
| 100 | static void demux_tasklet(unsigned long data) |
| 101 | { |
| 102 | struct ngene_channel *chan = (struct ngene_channel *)data; |
| 103 | struct SBufferHeader *Cur = chan->nextBuffer; |
| 104 | |
| 105 | spin_lock_irq(&chan->state_lock); |
| 106 | |
| 107 | while (Cur->ngeneBuffer.SR.Flags & 0x80) { |
| 108 | if (chan->mode & NGENE_IO_TSOUT) { |
| 109 | u32 Flags = chan->DataFormatFlags; |
| 110 | if (Cur->ngeneBuffer.SR.Flags & 0x20) |
| 111 | Flags |= BEF_OVERFLOW; |
| 112 | if (chan->pBufferExchange) { |
| 113 | if (!chan->pBufferExchange(chan, |
| 114 | Cur->Buffer1, |
| 115 | chan->Capture1Length, |
| 116 | Cur->ngeneBuffer.SR. |
| 117 | Clock, Flags)) { |
| 118 | /* |
| 119 | We didn't get data |
| 120 | Clear in service flag to make sure we |
| 121 | get called on next interrupt again. |
| 122 | leave fill/empty (0x80) flag alone |
| 123 | to avoid hardware running out of |
| 124 | buffers during startup, we hold only |
| 125 | in run state ( the source may be late |
| 126 | delivering data ) |
| 127 | */ |
| 128 | |
| 129 | if (chan->HWState == HWSTATE_RUN) { |
| 130 | Cur->ngeneBuffer.SR.Flags &= |
| 131 | ~0x40; |
| 132 | break; |
| 133 | /* Stop proccessing stream */ |
| 134 | } |
| 135 | } else { |
| 136 | /* We got a valid buffer, |
| 137 | so switch to run state */ |
| 138 | chan->HWState = HWSTATE_RUN; |
| 139 | } |
| 140 | } else { |
| 141 | printk(KERN_ERR DEVICE_NAME ": OOPS\n"); |
| 142 | if (chan->HWState == HWSTATE_RUN) { |
| 143 | Cur->ngeneBuffer.SR.Flags &= ~0x40; |
| 144 | break; /* Stop proccessing stream */ |
| 145 | } |
| 146 | } |
| 147 | if (chan->AudioDTOUpdated) { |
| 148 | printk(KERN_INFO DEVICE_NAME |
| 149 | ": Update AudioDTO = %d\n", |
| 150 | chan->AudioDTOValue); |
| 151 | Cur->ngeneBuffer.SR.DTOUpdate = |
| 152 | chan->AudioDTOValue; |
| 153 | chan->AudioDTOUpdated = 0; |
| 154 | } |
| 155 | } else { |
| 156 | if (chan->HWState == HWSTATE_RUN) { |
| 157 | u32 Flags = 0; |
| 158 | if (Cur->ngeneBuffer.SR.Flags & 0x01) |
| 159 | Flags |= BEF_EVEN_FIELD; |
| 160 | if (Cur->ngeneBuffer.SR.Flags & 0x20) |
| 161 | Flags |= BEF_OVERFLOW; |
| 162 | if (chan->pBufferExchange) |
| 163 | chan->pBufferExchange(chan, |
| 164 | Cur->Buffer1, |
| 165 | chan-> |
| 166 | Capture1Length, |
| 167 | Cur->ngeneBuffer. |
| 168 | SR.Clock, Flags); |
| 169 | if (chan->pBufferExchange2) |
| 170 | chan->pBufferExchange2(chan, |
| 171 | Cur->Buffer2, |
| 172 | chan-> |
| 173 | Capture2Length, |
| 174 | Cur->ngeneBuffer. |
| 175 | SR.Clock, Flags); |
| 176 | } else if (chan->HWState != HWSTATE_STOP) |
| 177 | chan->HWState = HWSTATE_RUN; |
| 178 | } |
| 179 | Cur->ngeneBuffer.SR.Flags = 0x00; |
| 180 | Cur = Cur->Next; |
| 181 | } |
| 182 | chan->nextBuffer = Cur; |
| 183 | |
| 184 | spin_unlock_irq(&chan->state_lock); |
| 185 | } |
| 186 | |
| 187 | static irqreturn_t irq_handler(int irq, void *dev_id) |
| 188 | { |
| 189 | struct ngene *dev = (struct ngene *)dev_id; |
| 190 | u32 icounts = 0; |
| 191 | irqreturn_t rc = IRQ_NONE; |
| 192 | u32 i = MAX_STREAM; |
| 193 | u8 *tmpCmdDoneByte; |
| 194 | |
| 195 | if (dev->BootFirmware) { |
| 196 | icounts = ngreadl(NGENE_INT_COUNTS); |
| 197 | if (icounts != dev->icounts) { |
| 198 | ngwritel(0, FORCE_NMI); |
| 199 | dev->cmd_done = 1; |
| 200 | wake_up(&dev->cmd_wq); |
| 201 | dev->icounts = icounts; |
| 202 | rc = IRQ_HANDLED; |
| 203 | } |
| 204 | return rc; |
| 205 | } |
| 206 | |
| 207 | ngwritel(0, FORCE_NMI); |
| 208 | |
| 209 | spin_lock(&dev->cmd_lock); |
| 210 | tmpCmdDoneByte = dev->CmdDoneByte; |
| 211 | if (tmpCmdDoneByte && |
| 212 | (*tmpCmdDoneByte || |
| 213 | (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) { |
| 214 | dev->CmdDoneByte = NULL; |
| 215 | dev->cmd_done = 1; |
| 216 | wake_up(&dev->cmd_wq); |
| 217 | rc = IRQ_HANDLED; |
| 218 | } |
| 219 | spin_unlock(&dev->cmd_lock); |
| 220 | |
| 221 | if (dev->EventBuffer->EventStatus & 0x80) { |
| 222 | u8 nextWriteIndex = |
| 223 | (dev->EventQueueWriteIndex + 1) & |
| 224 | (EVENT_QUEUE_SIZE - 1); |
| 225 | if (nextWriteIndex != dev->EventQueueReadIndex) { |
| 226 | dev->EventQueue[dev->EventQueueWriteIndex] = |
| 227 | *(dev->EventBuffer); |
| 228 | dev->EventQueueWriteIndex = nextWriteIndex; |
| 229 | } else { |
| 230 | printk(KERN_ERR DEVICE_NAME ": event overflow\n"); |
| 231 | dev->EventQueueOverflowCount += 1; |
| 232 | dev->EventQueueOverflowFlag = 1; |
| 233 | } |
| 234 | dev->EventBuffer->EventStatus &= ~0x80; |
| 235 | tasklet_schedule(&dev->event_tasklet); |
| 236 | rc = IRQ_HANDLED; |
| 237 | } |
| 238 | |
| 239 | while (i > 0) { |
| 240 | i--; |
| 241 | spin_lock(&dev->channel[i].state_lock); |
| 242 | /* if (dev->channel[i].State>=KSSTATE_RUN) { */ |
| 243 | if (dev->channel[i].nextBuffer) { |
| 244 | if ((dev->channel[i].nextBuffer-> |
| 245 | ngeneBuffer.SR.Flags & 0xC0) == 0x80) { |
| 246 | dev->channel[i].nextBuffer-> |
| 247 | ngeneBuffer.SR.Flags |= 0x40; |
| 248 | tasklet_schedule( |
| 249 | &dev->channel[i].demux_tasklet); |
| 250 | rc = IRQ_HANDLED; |
| 251 | } |
| 252 | } |
| 253 | spin_unlock(&dev->channel[i].state_lock); |
| 254 | } |
| 255 | |
Oliver Endriss | ace30f7 | 2010-01-20 19:03:22 -0300 | [diff] [blame] | 256 | /* Request might have been processed by a previous call. */ |
| 257 | return IRQ_HANDLED; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | /****************************************************************************/ |
| 261 | /* nGene command interface **************************************************/ |
| 262 | /****************************************************************************/ |
| 263 | |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 264 | static void dump_command_io(struct ngene *dev) |
| 265 | { |
| 266 | u8 buf[8], *b; |
| 267 | |
| 268 | ngcpyfrom(buf, HOST_TO_NGENE, 8); |
| 269 | printk(KERN_ERR "host_to_ngene (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n", |
| 270 | HOST_TO_NGENE, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
| 271 | |
| 272 | ngcpyfrom(buf, NGENE_TO_HOST, 8); |
| 273 | printk(KERN_ERR "ngene_to_host (%04x): %02x %02x %02x %02x %02x %02x %02x %02x\n", |
| 274 | NGENE_TO_HOST, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
| 275 | |
| 276 | b = dev->hosttongene; |
| 277 | printk(KERN_ERR "dev->hosttongene (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n", |
| 278 | b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); |
| 279 | |
| 280 | b = dev->ngenetohost; |
| 281 | printk(KERN_ERR "dev->ngenetohost (%p): %02x %02x %02x %02x %02x %02x %02x %02x\n", |
| 282 | b, b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]); |
| 283 | } |
| 284 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 285 | static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) |
| 286 | { |
| 287 | int ret; |
| 288 | u8 *tmpCmdDoneByte; |
| 289 | |
| 290 | dev->cmd_done = 0; |
| 291 | |
| 292 | if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) { |
| 293 | dev->BootFirmware = 1; |
| 294 | dev->icounts = ngreadl(NGENE_INT_COUNTS); |
| 295 | ngwritel(0, NGENE_COMMAND); |
| 296 | ngwritel(0, NGENE_COMMAND_HI); |
| 297 | ngwritel(0, NGENE_STATUS); |
| 298 | ngwritel(0, NGENE_STATUS_HI); |
| 299 | ngwritel(0, NGENE_EVENT); |
| 300 | ngwritel(0, NGENE_EVENT_HI); |
| 301 | } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) { |
| 302 | u64 fwio = dev->PAFWInterfaceBuffer; |
| 303 | |
| 304 | ngwritel(fwio & 0xffffffff, NGENE_COMMAND); |
| 305 | ngwritel(fwio >> 32, NGENE_COMMAND_HI); |
| 306 | ngwritel((fwio + 256) & 0xffffffff, NGENE_STATUS); |
| 307 | ngwritel((fwio + 256) >> 32, NGENE_STATUS_HI); |
| 308 | ngwritel((fwio + 512) & 0xffffffff, NGENE_EVENT); |
| 309 | ngwritel((fwio + 512) >> 32, NGENE_EVENT_HI); |
| 310 | } |
| 311 | |
| 312 | memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2); |
| 313 | |
| 314 | if (dev->BootFirmware) |
| 315 | ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2); |
| 316 | |
| 317 | spin_lock_irq(&dev->cmd_lock); |
| 318 | tmpCmdDoneByte = dev->ngenetohost + com->out_len; |
| 319 | if (!com->out_len) |
| 320 | tmpCmdDoneByte++; |
| 321 | *tmpCmdDoneByte = 0; |
| 322 | dev->ngenetohost[0] = 0; |
| 323 | dev->ngenetohost[1] = 0; |
| 324 | dev->CmdDoneByte = tmpCmdDoneByte; |
| 325 | spin_unlock_irq(&dev->cmd_lock); |
| 326 | |
| 327 | /* Notify 8051. */ |
| 328 | ngwritel(1, FORCE_INT); |
| 329 | |
| 330 | ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); |
| 331 | if (!ret) { |
| 332 | /*ngwritel(0, FORCE_NMI);*/ |
| 333 | |
| 334 | printk(KERN_ERR DEVICE_NAME |
| 335 | ": Command timeout cmd=%02x prev=%02x\n", |
| 336 | com->cmd.hdr.Opcode, dev->prev_cmd); |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 337 | dump_command_io(dev); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 338 | return -1; |
| 339 | } |
| 340 | if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) |
| 341 | dev->BootFirmware = 0; |
| 342 | |
| 343 | dev->prev_cmd = com->cmd.hdr.Opcode; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 344 | |
| 345 | if (!com->out_len) |
| 346 | return 0; |
| 347 | |
| 348 | memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len); |
| 349 | |
| 350 | return 0; |
| 351 | } |
| 352 | |
| 353 | static int ngene_command(struct ngene *dev, struct ngene_command *com) |
| 354 | { |
| 355 | int result; |
| 356 | |
| 357 | down(&dev->cmd_mutex); |
| 358 | result = ngene_command_mutex(dev, com); |
| 359 | up(&dev->cmd_mutex); |
| 360 | return result; |
| 361 | } |
| 362 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 363 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 364 | static int ngene_command_i2c_read(struct ngene *dev, u8 adr, |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 365 | u8 *out, u8 outlen, u8 *in, u8 inlen, int flag) |
| 366 | { |
| 367 | struct ngene_command com; |
| 368 | |
| 369 | com.cmd.hdr.Opcode = CMD_I2C_READ; |
| 370 | com.cmd.hdr.Length = outlen + 3; |
| 371 | com.cmd.I2CRead.Device = adr << 1; |
| 372 | memcpy(com.cmd.I2CRead.Data, out, outlen); |
| 373 | com.cmd.I2CRead.Data[outlen] = inlen; |
| 374 | com.cmd.I2CRead.Data[outlen + 1] = 0; |
| 375 | com.in_len = outlen + 3; |
| 376 | com.out_len = inlen + 1; |
| 377 | |
| 378 | if (ngene_command(dev, &com) < 0) |
| 379 | return -EIO; |
| 380 | |
| 381 | if ((com.cmd.raw8[0] >> 1) != adr) |
| 382 | return -EIO; |
| 383 | |
| 384 | if (flag) |
| 385 | memcpy(in, com.cmd.raw8, inlen + 1); |
| 386 | else |
| 387 | memcpy(in, com.cmd.raw8 + 1, inlen); |
| 388 | return 0; |
| 389 | } |
| 390 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 391 | static int ngene_command_i2c_write(struct ngene *dev, u8 adr, |
| 392 | u8 *out, u8 outlen) |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 393 | { |
| 394 | struct ngene_command com; |
| 395 | |
| 396 | |
| 397 | com.cmd.hdr.Opcode = CMD_I2C_WRITE; |
| 398 | com.cmd.hdr.Length = outlen + 1; |
| 399 | com.cmd.I2CRead.Device = adr << 1; |
| 400 | memcpy(com.cmd.I2CRead.Data, out, outlen); |
| 401 | com.in_len = outlen + 1; |
| 402 | com.out_len = 1; |
| 403 | |
| 404 | if (ngene_command(dev, &com) < 0) |
| 405 | return -EIO; |
| 406 | |
| 407 | if (com.cmd.raw8[0] == 1) |
| 408 | return -EIO; |
| 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
| 413 | static int ngene_command_load_firmware(struct ngene *dev, |
| 414 | u8 *ngene_fw, u32 size) |
| 415 | { |
| 416 | #define FIRSTCHUNK (1024) |
| 417 | u32 cleft; |
| 418 | struct ngene_command com; |
| 419 | |
| 420 | com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE; |
| 421 | com.cmd.hdr.Length = 0; |
| 422 | com.in_len = 0; |
| 423 | com.out_len = 0; |
| 424 | |
| 425 | ngene_command(dev, &com); |
| 426 | |
| 427 | cleft = (size + 3) & ~3; |
| 428 | if (cleft > FIRSTCHUNK) { |
| 429 | ngcpyto(PROGRAM_SRAM + FIRSTCHUNK, ngene_fw + FIRSTCHUNK, |
| 430 | cleft - FIRSTCHUNK); |
| 431 | cleft = FIRSTCHUNK; |
| 432 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 433 | ngcpyto(DATA_FIFO_AREA, ngene_fw, cleft); |
| 434 | |
| 435 | memset(&com, 0, sizeof(struct ngene_command)); |
| 436 | com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH; |
| 437 | com.cmd.hdr.Length = 4; |
| 438 | com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA; |
| 439 | com.cmd.FWLoadFinish.Length = (unsigned short)cleft; |
| 440 | com.in_len = 4; |
| 441 | com.out_len = 0; |
| 442 | |
| 443 | return ngene_command(dev, &com); |
| 444 | } |
| 445 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 446 | |
| 447 | static int ngene_command_config_buf(struct ngene *dev, u8 config) |
| 448 | { |
| 449 | struct ngene_command com; |
| 450 | |
| 451 | com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER; |
| 452 | com.cmd.hdr.Length = 1; |
| 453 | com.cmd.ConfigureBuffers.config = config; |
| 454 | com.in_len = 1; |
| 455 | com.out_len = 0; |
| 456 | |
| 457 | if (ngene_command(dev, &com) < 0) |
| 458 | return -EIO; |
| 459 | return 0; |
| 460 | } |
| 461 | |
| 462 | static int ngene_command_config_free_buf(struct ngene *dev, u8 *config) |
| 463 | { |
| 464 | struct ngene_command com; |
| 465 | |
| 466 | com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; |
| 467 | com.cmd.hdr.Length = 6; |
| 468 | memcpy(&com.cmd.ConfigureBuffers.config, config, 6); |
| 469 | com.in_len = 6; |
| 470 | com.out_len = 0; |
| 471 | |
| 472 | if (ngene_command(dev, &com) < 0) |
| 473 | return -EIO; |
| 474 | |
| 475 | return 0; |
| 476 | } |
| 477 | |
| 478 | static int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level) |
| 479 | { |
| 480 | struct ngene_command com; |
| 481 | |
| 482 | com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN; |
| 483 | com.cmd.hdr.Length = 1; |
| 484 | com.cmd.SetGpioPin.select = select | (level << 7); |
| 485 | com.in_len = 1; |
| 486 | com.out_len = 0; |
| 487 | |
| 488 | return ngene_command(dev, &com); |
| 489 | } |
| 490 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 491 | |
| 492 | /* |
| 493 | 02000640 is sample on rising edge. |
| 494 | 02000740 is sample on falling edge. |
| 495 | 02000040 is ignore "valid" signal |
| 496 | |
| 497 | 0: FD_CTL1 Bit 7,6 must be 0,1 |
| 498 | 7 disable(fw controlled) |
| 499 | 6 0-AUX,1-TS |
| 500 | 5 0-par,1-ser |
| 501 | 4 0-lsb/1-msb |
| 502 | 3,2 reserved |
| 503 | 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both |
| 504 | 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge |
| 505 | 2: FD_STA is read-only. 0-sync |
| 506 | 3: FD_INSYNC is number of 47s to trigger "in sync". |
| 507 | 4: FD_OUTSYNC is number of 47s to trigger "out of sync". |
| 508 | 5: FD_MAXBYTE1 is low-order of bytes per packet. |
| 509 | 6: FD_MAXBYTE2 is high-order of bytes per packet. |
| 510 | 7: Top byte is unused. |
| 511 | */ |
| 512 | |
| 513 | /****************************************************************************/ |
| 514 | |
| 515 | static u8 TSFeatureDecoderSetup[8 * 4] = { |
| 516 | 0x42, 0x00, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, |
| 517 | 0x40, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXH */ |
| 518 | 0x71, 0x07, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* DRXHser */ |
| 519 | 0x72, 0x06, 0x00, 0x02, 0x02, 0xbc, 0x00, 0x00, /* S2ser */ |
| 520 | }; |
| 521 | |
| 522 | /* Set NGENE I2S Config to 16 bit packed */ |
| 523 | static u8 I2SConfiguration[] = { |
| 524 | 0x00, 0x10, 0x00, 0x00, |
| 525 | 0x80, 0x10, 0x00, 0x00, |
| 526 | }; |
| 527 | |
| 528 | static u8 SPDIFConfiguration[10] = { |
| 529 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 |
| 530 | }; |
| 531 | |
| 532 | /* Set NGENE I2S Config to transport stream compatible mode */ |
| 533 | |
| 534 | static u8 TS_I2SConfiguration[4] = { 0x3E, 0x1A, 0x00, 0x00 }; /*3e 18 00 00 ?*/ |
| 535 | |
| 536 | static u8 TS_I2SOutConfiguration[4] = { 0x80, 0x20, 0x00, 0x00 }; |
| 537 | |
| 538 | static u8 ITUDecoderSetup[4][16] = { |
| 539 | {0x1c, 0x13, 0x01, 0x68, 0x3d, 0x90, 0x14, 0x20, /* SDTV */ |
| 540 | 0x00, 0x00, 0x01, 0xb0, 0x9c, 0x00, 0x00, 0x00}, |
| 541 | {0x9c, 0x03, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, |
| 542 | 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, |
| 543 | {0x9f, 0x00, 0x23, 0xC0, 0x60, 0x0F, 0x13, 0x00, /* HDTV 1080i50 */ |
| 544 | 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, |
| 545 | {0x9c, 0x01, 0x23, 0xC0, 0x60, 0x0E, 0x13, 0x00, /* HDTV 1080i60 */ |
| 546 | 0x00, 0x00, 0x00, 0x01, 0xB0, 0x00, 0x00, 0x00}, |
| 547 | }; |
| 548 | |
| 549 | /* |
| 550 | * 50 48 60 gleich |
| 551 | * 27p50 9f 00 22 80 42 69 18 ... |
| 552 | * 27p60 93 00 22 80 82 69 1c ... |
| 553 | */ |
| 554 | |
| 555 | /* Maxbyte to 1144 (for raw data) */ |
| 556 | static u8 ITUFeatureDecoderSetup[8] = { |
| 557 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0x04, 0x00 |
| 558 | }; |
| 559 | |
| 560 | static void FillTSBuffer(void *Buffer, int Length, u32 Flags) |
| 561 | { |
| 562 | u32 *ptr = Buffer; |
| 563 | |
| 564 | memset(Buffer, Length, 0xff); |
| 565 | while (Length > 0) { |
| 566 | if (Flags & DF_SWAP32) |
| 567 | *ptr = 0x471FFF10; |
| 568 | else |
| 569 | *ptr = 0x10FF1F47; |
| 570 | ptr += (188 / 4); |
| 571 | Length -= 188; |
| 572 | } |
| 573 | } |
| 574 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 575 | |
| 576 | static void flush_buffers(struct ngene_channel *chan) |
| 577 | { |
| 578 | u8 val; |
| 579 | |
| 580 | do { |
| 581 | msleep(1); |
| 582 | spin_lock_irq(&chan->state_lock); |
| 583 | val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; |
| 584 | spin_unlock_irq(&chan->state_lock); |
| 585 | } while (val); |
| 586 | } |
| 587 | |
| 588 | static void clear_buffers(struct ngene_channel *chan) |
| 589 | { |
| 590 | struct SBufferHeader *Cur = chan->nextBuffer; |
| 591 | |
| 592 | do { |
| 593 | memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); |
| 594 | if (chan->mode & NGENE_IO_TSOUT) |
| 595 | FillTSBuffer(Cur->Buffer1, |
| 596 | chan->Capture1Length, |
| 597 | chan->DataFormatFlags); |
| 598 | Cur = Cur->Next; |
| 599 | } while (Cur != chan->nextBuffer); |
| 600 | |
| 601 | if (chan->mode & NGENE_IO_TSOUT) { |
| 602 | chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = |
| 603 | chan->AudioDTOValue; |
| 604 | chan->AudioDTOUpdated = 0; |
| 605 | |
| 606 | Cur = chan->TSIdleBuffer.Head; |
| 607 | |
| 608 | do { |
| 609 | memset(&Cur->ngeneBuffer.SR, 0, |
| 610 | sizeof(Cur->ngeneBuffer.SR)); |
| 611 | FillTSBuffer(Cur->Buffer1, |
| 612 | chan->Capture1Length, |
| 613 | chan->DataFormatFlags); |
| 614 | Cur = Cur->Next; |
| 615 | } while (Cur != chan->TSIdleBuffer.Head); |
| 616 | } |
| 617 | } |
| 618 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 619 | static int ngene_command_stream_control(struct ngene *dev, u8 stream, |
| 620 | u8 control, u8 mode, u8 flags) |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 621 | { |
| 622 | struct ngene_channel *chan = &dev->channel[stream]; |
| 623 | struct ngene_command com; |
| 624 | u16 BsUVI = ((stream & 1) ? 0x9400 : 0x9300); |
| 625 | u16 BsSDI = ((stream & 1) ? 0x9600 : 0x9500); |
| 626 | u16 BsSPI = ((stream & 1) ? 0x9800 : 0x9700); |
| 627 | u16 BsSDO = 0x9B00; |
| 628 | |
| 629 | /* down(&dev->stream_mutex); */ |
| 630 | while (down_trylock(&dev->stream_mutex)) { |
| 631 | printk(KERN_INFO DEVICE_NAME ": SC locked\n"); |
| 632 | msleep(1); |
| 633 | } |
| 634 | memset(&com, 0, sizeof(com)); |
| 635 | com.cmd.hdr.Opcode = CMD_CONTROL; |
| 636 | com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2; |
| 637 | com.cmd.StreamControl.Stream = stream | (control ? 8 : 0); |
| 638 | if (chan->mode & NGENE_IO_TSOUT) |
| 639 | com.cmd.StreamControl.Stream |= 0x07; |
| 640 | com.cmd.StreamControl.Control = control | |
| 641 | (flags & SFLAG_ORDER_LUMA_CHROMA); |
| 642 | com.cmd.StreamControl.Mode = mode; |
| 643 | com.in_len = sizeof(struct FW_STREAM_CONTROL); |
| 644 | com.out_len = 0; |
| 645 | |
Oliver Endriss | 44cdd06 | 2009-12-20 02:30:52 -0300 | [diff] [blame] | 646 | dprintk(KERN_INFO DEVICE_NAME |
| 647 | ": Stream=%02x, Control=%02x, Mode=%02x\n", |
| 648 | com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control, |
| 649 | com.cmd.StreamControl.Mode); |
| 650 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 651 | chan->Mode = mode; |
| 652 | |
| 653 | if (!(control & 0x80)) { |
| 654 | spin_lock_irq(&chan->state_lock); |
| 655 | if (chan->State == KSSTATE_RUN) { |
| 656 | chan->State = KSSTATE_ACQUIRE; |
| 657 | chan->HWState = HWSTATE_STOP; |
| 658 | spin_unlock_irq(&chan->state_lock); |
| 659 | if (ngene_command(dev, &com) < 0) { |
| 660 | up(&dev->stream_mutex); |
| 661 | return -1; |
| 662 | } |
| 663 | /* clear_buffers(chan); */ |
| 664 | flush_buffers(chan); |
| 665 | up(&dev->stream_mutex); |
| 666 | return 0; |
| 667 | } |
| 668 | spin_unlock_irq(&chan->state_lock); |
| 669 | up(&dev->stream_mutex); |
| 670 | return 0; |
| 671 | } |
| 672 | |
| 673 | if (mode & SMODE_AUDIO_CAPTURE) { |
| 674 | com.cmd.StreamControl.CaptureBlockCount = |
| 675 | chan->Capture1Length / AUDIO_BLOCK_SIZE; |
| 676 | com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; |
| 677 | } else if (mode & SMODE_TRANSPORT_STREAM) { |
| 678 | com.cmd.StreamControl.CaptureBlockCount = |
| 679 | chan->Capture1Length / TS_BLOCK_SIZE; |
| 680 | com.cmd.StreamControl.MaxLinesPerField = |
| 681 | chan->Capture1Length / TS_BLOCK_SIZE; |
| 682 | com.cmd.StreamControl.Buffer_Address = |
| 683 | chan->TSRingBuffer.PAHead; |
| 684 | if (chan->mode & NGENE_IO_TSOUT) { |
| 685 | com.cmd.StreamControl.BytesPerVBILine = |
| 686 | chan->Capture1Length / TS_BLOCK_SIZE; |
| 687 | com.cmd.StreamControl.Stream |= 0x07; |
| 688 | } |
| 689 | } else { |
| 690 | com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine; |
| 691 | com.cmd.StreamControl.MaxLinesPerField = chan->nLines; |
| 692 | com.cmd.StreamControl.MinLinesPerField = 100; |
| 693 | com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; |
| 694 | |
| 695 | if (mode & SMODE_VBI_CAPTURE) { |
| 696 | com.cmd.StreamControl.MaxVBILinesPerField = |
| 697 | chan->nVBILines; |
| 698 | com.cmd.StreamControl.MinVBILinesPerField = 0; |
| 699 | com.cmd.StreamControl.BytesPerVBILine = |
| 700 | chan->nBytesPerVBILine; |
| 701 | } |
| 702 | if (flags & SFLAG_COLORBAR) |
| 703 | com.cmd.StreamControl.Stream |= 0x04; |
| 704 | } |
| 705 | |
| 706 | spin_lock_irq(&chan->state_lock); |
| 707 | if (mode & SMODE_AUDIO_CAPTURE) { |
| 708 | chan->nextBuffer = chan->RingBuffer.Head; |
| 709 | if (mode & SMODE_AUDIO_SPDIF) { |
| 710 | com.cmd.StreamControl.SetupDataLen = |
| 711 | sizeof(SPDIFConfiguration); |
| 712 | com.cmd.StreamControl.SetupDataAddr = BsSPI; |
| 713 | memcpy(com.cmd.StreamControl.SetupData, |
| 714 | SPDIFConfiguration, sizeof(SPDIFConfiguration)); |
| 715 | } else { |
| 716 | com.cmd.StreamControl.SetupDataLen = 4; |
| 717 | com.cmd.StreamControl.SetupDataAddr = BsSDI; |
| 718 | memcpy(com.cmd.StreamControl.SetupData, |
| 719 | I2SConfiguration + |
| 720 | 4 * dev->card_info->i2s[stream], 4); |
| 721 | } |
| 722 | } else if (mode & SMODE_TRANSPORT_STREAM) { |
| 723 | chan->nextBuffer = chan->TSRingBuffer.Head; |
| 724 | if (stream >= STREAM_AUDIOIN1) { |
| 725 | if (chan->mode & NGENE_IO_TSOUT) { |
| 726 | com.cmd.StreamControl.SetupDataLen = |
| 727 | sizeof(TS_I2SOutConfiguration); |
| 728 | com.cmd.StreamControl.SetupDataAddr = BsSDO; |
| 729 | memcpy(com.cmd.StreamControl.SetupData, |
| 730 | TS_I2SOutConfiguration, |
| 731 | sizeof(TS_I2SOutConfiguration)); |
| 732 | } else { |
| 733 | com.cmd.StreamControl.SetupDataLen = |
| 734 | sizeof(TS_I2SConfiguration); |
| 735 | com.cmd.StreamControl.SetupDataAddr = BsSDI; |
| 736 | memcpy(com.cmd.StreamControl.SetupData, |
| 737 | TS_I2SConfiguration, |
| 738 | sizeof(TS_I2SConfiguration)); |
| 739 | } |
| 740 | } else { |
| 741 | com.cmd.StreamControl.SetupDataLen = 8; |
| 742 | com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10; |
| 743 | memcpy(com.cmd.StreamControl.SetupData, |
| 744 | TSFeatureDecoderSetup + |
| 745 | 8 * dev->card_info->tsf[stream], 8); |
| 746 | } |
| 747 | } else { |
| 748 | chan->nextBuffer = chan->RingBuffer.Head; |
| 749 | com.cmd.StreamControl.SetupDataLen = |
| 750 | 16 + sizeof(ITUFeatureDecoderSetup); |
| 751 | com.cmd.StreamControl.SetupDataAddr = BsUVI; |
| 752 | memcpy(com.cmd.StreamControl.SetupData, |
| 753 | ITUDecoderSetup[chan->itumode], 16); |
| 754 | memcpy(com.cmd.StreamControl.SetupData + 16, |
| 755 | ITUFeatureDecoderSetup, sizeof(ITUFeatureDecoderSetup)); |
| 756 | } |
| 757 | clear_buffers(chan); |
| 758 | chan->State = KSSTATE_RUN; |
| 759 | if (mode & SMODE_TRANSPORT_STREAM) |
| 760 | chan->HWState = HWSTATE_RUN; |
| 761 | else |
| 762 | chan->HWState = HWSTATE_STARTUP; |
| 763 | spin_unlock_irq(&chan->state_lock); |
| 764 | |
| 765 | if (ngene_command(dev, &com) < 0) { |
| 766 | up(&dev->stream_mutex); |
| 767 | return -1; |
| 768 | } |
| 769 | up(&dev->stream_mutex); |
| 770 | return 0; |
| 771 | } |
| 772 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 773 | |
| 774 | /****************************************************************************/ |
| 775 | /* I2C **********************************************************************/ |
| 776 | /****************************************************************************/ |
| 777 | |
| 778 | static void ngene_i2c_set_bus(struct ngene *dev, int bus) |
| 779 | { |
| 780 | if (!(dev->card_info->i2c_access & 2)) |
| 781 | return; |
| 782 | if (dev->i2c_current_bus == bus) |
| 783 | return; |
| 784 | |
| 785 | switch (bus) { |
| 786 | case 0: |
| 787 | ngene_command_gpio_set(dev, 3, 0); |
| 788 | ngene_command_gpio_set(dev, 2, 1); |
| 789 | break; |
| 790 | |
| 791 | case 1: |
| 792 | ngene_command_gpio_set(dev, 2, 0); |
| 793 | ngene_command_gpio_set(dev, 3, 1); |
| 794 | break; |
| 795 | } |
| 796 | dev->i2c_current_bus = bus; |
| 797 | } |
| 798 | |
| 799 | static int ngene_i2c_master_xfer(struct i2c_adapter *adapter, |
| 800 | struct i2c_msg msg[], int num) |
| 801 | { |
| 802 | struct ngene_channel *chan = |
| 803 | (struct ngene_channel *)i2c_get_adapdata(adapter); |
| 804 | struct ngene *dev = chan->dev; |
| 805 | |
| 806 | down(&dev->i2c_switch_mutex); |
| 807 | ngene_i2c_set_bus(dev, chan->number); |
| 808 | |
| 809 | if (num == 2 && msg[1].flags & I2C_M_RD && !(msg[0].flags & I2C_M_RD)) |
| 810 | if (!ngene_command_i2c_read(dev, msg[0].addr, |
| 811 | msg[0].buf, msg[0].len, |
| 812 | msg[1].buf, msg[1].len, 0)) |
| 813 | goto done; |
| 814 | |
| 815 | if (num == 1 && !(msg[0].flags & I2C_M_RD)) |
| 816 | if (!ngene_command_i2c_write(dev, msg[0].addr, |
| 817 | msg[0].buf, msg[0].len)) |
| 818 | goto done; |
| 819 | if (num == 1 && (msg[0].flags & I2C_M_RD)) |
| 820 | if (!ngene_command_i2c_read(dev, msg[0].addr, 0, 0, |
| 821 | msg[0].buf, msg[0].len, 0)) |
| 822 | goto done; |
| 823 | |
| 824 | up(&dev->i2c_switch_mutex); |
| 825 | return -EIO; |
| 826 | |
| 827 | done: |
| 828 | up(&dev->i2c_switch_mutex); |
| 829 | return num; |
| 830 | } |
| 831 | |
| 832 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 833 | static u32 ngene_i2c_functionality(struct i2c_adapter *adap) |
| 834 | { |
| 835 | return I2C_FUNC_SMBUS_EMUL; |
| 836 | } |
| 837 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 838 | static struct i2c_algorithm ngene_i2c_algo = { |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 839 | .master_xfer = ngene_i2c_master_xfer, |
| 840 | .functionality = ngene_i2c_functionality, |
| 841 | }; |
| 842 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 843 | static int ngene_i2c_init(struct ngene *dev, int dev_nr) |
| 844 | { |
| 845 | struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter); |
| 846 | |
| 847 | i2c_set_adapdata(adap, &(dev->channel[dev_nr])); |
| 848 | #ifdef I2C_ADAP_CLASS_TV_DIGITAL |
| 849 | adap->class = I2C_ADAP_CLASS_TV_DIGITAL | I2C_CLASS_TV_ANALOG; |
| 850 | #else |
| 851 | adap->class = I2C_CLASS_TV_ANALOG; |
| 852 | #endif |
| 853 | |
| 854 | strcpy(adap->name, "nGene"); |
| 855 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 856 | adap->algo = &ngene_i2c_algo; |
| 857 | adap->algo_data = (void *)&(dev->channel[dev_nr]); |
Manu Abraham | c58b5ec | 2009-12-26 16:56:26 -0300 | [diff] [blame] | 858 | adap->dev.parent = &dev->pci_dev->dev; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 859 | |
| 860 | mutex_init(&adap->bus_lock); |
| 861 | return i2c_add_adapter(adap); |
| 862 | } |
| 863 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 864 | |
| 865 | /****************************************************************************/ |
| 866 | /* DVB functions and API interface ******************************************/ |
| 867 | /****************************************************************************/ |
| 868 | |
| 869 | static void swap_buffer(u32 *p, u32 len) |
| 870 | { |
| 871 | while (len) { |
| 872 | *p = swab32(*p); |
| 873 | p++; |
| 874 | len -= 4; |
| 875 | } |
| 876 | } |
| 877 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 878 | |
| 879 | static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) |
| 880 | { |
| 881 | struct ngene_channel *chan = priv; |
| 882 | |
| 883 | |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 884 | #ifdef COMMAND_TIMEOUT_WORKAROUND |
| 885 | if (chan->users > 0) |
| 886 | #endif |
| 887 | dvb_dmx_swfilter(&chan->demux, buf, len); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 888 | return 0; |
| 889 | } |
| 890 | |
| 891 | u8 fill_ts[188] = { 0x47, 0x1f, 0xff, 0x10 }; |
| 892 | |
| 893 | static void *tsout_exchange(void *priv, void *buf, u32 len, |
| 894 | u32 clock, u32 flags) |
| 895 | { |
| 896 | struct ngene_channel *chan = priv; |
| 897 | struct ngene *dev = chan->dev; |
| 898 | u32 alen; |
| 899 | |
| 900 | alen = dvb_ringbuffer_avail(&dev->tsout_rbuf); |
| 901 | alen -= alen % 188; |
| 902 | |
| 903 | if (alen < len) |
| 904 | FillTSBuffer(buf + alen, len - alen, flags); |
| 905 | else |
| 906 | alen = len; |
| 907 | dvb_ringbuffer_read(&dev->tsout_rbuf, buf, alen); |
| 908 | if (flags & DF_SWAP32) |
| 909 | swap_buffer((u32 *)buf, alen); |
| 910 | wake_up_interruptible(&dev->tsout_rbuf.queue); |
| 911 | return buf; |
| 912 | } |
| 913 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 914 | |
| 915 | static void set_transfer(struct ngene_channel *chan, int state) |
| 916 | { |
| 917 | u8 control = 0, mode = 0, flags = 0; |
| 918 | struct ngene *dev = chan->dev; |
| 919 | int ret; |
| 920 | |
| 921 | /* |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 922 | printk(KERN_INFO DEVICE_NAME ": st %d\n", state); |
| 923 | msleep(100); |
| 924 | */ |
| 925 | |
| 926 | if (state) { |
| 927 | if (chan->running) { |
| 928 | printk(KERN_INFO DEVICE_NAME ": already running\n"); |
| 929 | return; |
| 930 | } |
| 931 | } else { |
| 932 | if (!chan->running) { |
| 933 | printk(KERN_INFO DEVICE_NAME ": already stopped\n"); |
| 934 | return; |
| 935 | } |
| 936 | } |
| 937 | |
| 938 | if (dev->card_info->switch_ctrl) |
| 939 | dev->card_info->switch_ctrl(chan, 1, state ^ 1); |
| 940 | |
| 941 | if (state) { |
| 942 | spin_lock_irq(&chan->state_lock); |
| 943 | |
| 944 | /* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", |
| 945 | ngreadl(0x9310)); */ |
Oliver Endriss | 126cd4b | 2009-12-22 04:37:53 -0300 | [diff] [blame] | 946 | dvb_ringbuffer_flush(&dev->tsout_rbuf); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 947 | control = 0x80; |
| 948 | if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { |
| 949 | chan->Capture1Length = 512 * 188; |
| 950 | mode = SMODE_TRANSPORT_STREAM; |
| 951 | } |
| 952 | if (chan->mode & NGENE_IO_TSOUT) { |
| 953 | chan->pBufferExchange = tsout_exchange; |
| 954 | /* 0x66666666 = 50MHz *2^33 /250MHz */ |
| 955 | chan->AudioDTOValue = 0x66666666; |
| 956 | /* set_dto(chan, 38810700+1000); */ |
| 957 | /* set_dto(chan, 19392658); */ |
| 958 | } |
| 959 | if (chan->mode & NGENE_IO_TSIN) |
| 960 | chan->pBufferExchange = tsin_exchange; |
| 961 | /* ngwritel(0, 0x9310); */ |
| 962 | spin_unlock_irq(&chan->state_lock); |
| 963 | } else |
| 964 | ;/* printk(KERN_INFO DEVICE_NAME ": lock=%08x\n", |
| 965 | ngreadl(0x9310)); */ |
| 966 | |
| 967 | ret = ngene_command_stream_control(dev, chan->number, |
| 968 | control, mode, flags); |
| 969 | if (!ret) |
| 970 | chan->running = state; |
| 971 | else |
| 972 | printk(KERN_ERR DEVICE_NAME ": set_transfer %d failed\n", |
| 973 | state); |
| 974 | if (!state) { |
| 975 | spin_lock_irq(&chan->state_lock); |
| 976 | chan->pBufferExchange = 0; |
Oliver Endriss | 126cd4b | 2009-12-22 04:37:53 -0300 | [diff] [blame] | 977 | dvb_ringbuffer_flush(&dev->tsout_rbuf); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 978 | spin_unlock_irq(&chan->state_lock); |
| 979 | } |
| 980 | } |
| 981 | |
| 982 | static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed) |
| 983 | { |
| 984 | struct dvb_demux *dvbdmx = dvbdmxfeed->demux; |
| 985 | struct ngene_channel *chan = dvbdmx->priv; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 986 | |
| 987 | if (chan->users == 0) { |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 988 | #ifdef COMMAND_TIMEOUT_WORKAROUND |
| 989 | if (!chan->running) |
| 990 | #endif |
| 991 | set_transfer(chan, 1); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 992 | /* msleep(10); */ |
| 993 | } |
| 994 | |
| 995 | return ++chan->users; |
| 996 | } |
| 997 | |
| 998 | static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed) |
| 999 | { |
| 1000 | struct dvb_demux *dvbdmx = dvbdmxfeed->demux; |
| 1001 | struct ngene_channel *chan = dvbdmx->priv; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1002 | |
| 1003 | if (--chan->users) |
| 1004 | return chan->users; |
| 1005 | |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 1006 | #ifndef COMMAND_TIMEOUT_WORKAROUND |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1007 | set_transfer(chan, 0); |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 1008 | #endif |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1009 | |
| 1010 | return 0; |
| 1011 | } |
| 1012 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1013 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1014 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1015 | static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, |
| 1016 | int (*start_feed)(struct dvb_demux_feed *), |
| 1017 | int (*stop_feed)(struct dvb_demux_feed *), |
| 1018 | void *priv) |
| 1019 | { |
| 1020 | dvbdemux->priv = priv; |
| 1021 | |
| 1022 | dvbdemux->filternum = 256; |
| 1023 | dvbdemux->feednum = 256; |
| 1024 | dvbdemux->start_feed = start_feed; |
| 1025 | dvbdemux->stop_feed = stop_feed; |
| 1026 | dvbdemux->write_to_decoder = 0; |
| 1027 | dvbdemux->dmx.capabilities = (DMX_TS_FILTERING | |
| 1028 | DMX_SECTION_FILTERING | |
| 1029 | DMX_MEMORY_BASED_FILTERING); |
| 1030 | return dvb_dmx_init(dvbdemux); |
| 1031 | } |
| 1032 | |
| 1033 | static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, |
| 1034 | struct dvb_demux *dvbdemux, |
| 1035 | struct dmx_frontend *hw_frontend, |
| 1036 | struct dmx_frontend *mem_frontend, |
| 1037 | struct dvb_adapter *dvb_adapter) |
| 1038 | { |
| 1039 | int ret; |
| 1040 | |
| 1041 | dmxdev->filternum = 256; |
| 1042 | dmxdev->demux = &dvbdemux->dmx; |
| 1043 | dmxdev->capabilities = 0; |
| 1044 | ret = dvb_dmxdev_init(dmxdev, dvb_adapter); |
| 1045 | if (ret < 0) |
| 1046 | return ret; |
| 1047 | |
| 1048 | hw_frontend->source = DMX_FRONTEND_0; |
| 1049 | dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend); |
| 1050 | mem_frontend->source = DMX_MEMORY_FE; |
| 1051 | dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend); |
| 1052 | return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend); |
| 1053 | } |
| 1054 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1055 | |
| 1056 | /****************************************************************************/ |
| 1057 | /* nGene hardware init and release functions ********************************/ |
| 1058 | /****************************************************************************/ |
| 1059 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 1060 | static void free_ringbuffer(struct ngene *dev, struct SRingBufferDescriptor *rb) |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1061 | { |
| 1062 | struct SBufferHeader *Cur = rb->Head; |
| 1063 | u32 j; |
| 1064 | |
| 1065 | if (!Cur) |
| 1066 | return; |
| 1067 | |
| 1068 | for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) { |
| 1069 | if (Cur->Buffer1) |
| 1070 | pci_free_consistent(dev->pci_dev, |
| 1071 | rb->Buffer1Length, |
| 1072 | Cur->Buffer1, |
| 1073 | Cur->scList1->Address); |
| 1074 | |
| 1075 | if (Cur->Buffer2) |
| 1076 | pci_free_consistent(dev->pci_dev, |
| 1077 | rb->Buffer2Length, |
| 1078 | Cur->Buffer2, |
| 1079 | Cur->scList2->Address); |
| 1080 | } |
| 1081 | |
| 1082 | if (rb->SCListMem) |
| 1083 | pci_free_consistent(dev->pci_dev, rb->SCListMemSize, |
| 1084 | rb->SCListMem, rb->PASCListMem); |
| 1085 | |
| 1086 | pci_free_consistent(dev->pci_dev, rb->MemSize, rb->Head, rb->PAHead); |
| 1087 | } |
| 1088 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 1089 | static void free_idlebuffer(struct ngene *dev, |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1090 | struct SRingBufferDescriptor *rb, |
| 1091 | struct SRingBufferDescriptor *tb) |
| 1092 | { |
| 1093 | int j; |
| 1094 | struct SBufferHeader *Cur = tb->Head; |
| 1095 | |
| 1096 | if (!rb->Head) |
| 1097 | return; |
| 1098 | free_ringbuffer(dev, rb); |
| 1099 | for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) { |
| 1100 | Cur->Buffer2 = 0; |
| 1101 | Cur->scList2 = 0; |
| 1102 | Cur->ngeneBuffer.Address_of_first_entry_2 = 0; |
| 1103 | Cur->ngeneBuffer.Number_of_entries_2 = 0; |
| 1104 | } |
| 1105 | } |
| 1106 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 1107 | static void free_common_buffers(struct ngene *dev) |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1108 | { |
| 1109 | u32 i; |
| 1110 | struct ngene_channel *chan; |
| 1111 | |
| 1112 | for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { |
| 1113 | chan = &dev->channel[i]; |
| 1114 | free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer); |
| 1115 | free_ringbuffer(dev, &chan->RingBuffer); |
| 1116 | free_ringbuffer(dev, &chan->TSRingBuffer); |
| 1117 | } |
| 1118 | |
| 1119 | if (dev->OverflowBuffer) |
| 1120 | pci_free_consistent(dev->pci_dev, |
| 1121 | OVERFLOW_BUFFER_SIZE, |
| 1122 | dev->OverflowBuffer, dev->PAOverflowBuffer); |
| 1123 | |
| 1124 | if (dev->FWInterfaceBuffer) |
| 1125 | pci_free_consistent(dev->pci_dev, |
| 1126 | 4096, |
| 1127 | dev->FWInterfaceBuffer, |
| 1128 | dev->PAFWInterfaceBuffer); |
| 1129 | } |
| 1130 | |
| 1131 | /****************************************************************************/ |
| 1132 | /* Ring buffer handling *****************************************************/ |
| 1133 | /****************************************************************************/ |
| 1134 | |
Oliver Endriss | 9fdd797 | 2009-12-23 16:26:17 -0300 | [diff] [blame] | 1135 | static int create_ring_buffer(struct pci_dev *pci_dev, |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1136 | struct SRingBufferDescriptor *descr, u32 NumBuffers) |
| 1137 | { |
| 1138 | dma_addr_t tmp; |
| 1139 | struct SBufferHeader *Head; |
| 1140 | u32 i; |
| 1141 | u32 MemSize = SIZEOF_SBufferHeader * NumBuffers; |
| 1142 | u64 PARingBufferHead; |
| 1143 | u64 PARingBufferCur; |
| 1144 | u64 PARingBufferNext; |
| 1145 | struct SBufferHeader *Cur, *Next; |
| 1146 | |
| 1147 | descr->Head = 0; |
| 1148 | descr->MemSize = 0; |
| 1149 | descr->PAHead = 0; |
| 1150 | descr->NumBuffers = 0; |
| 1151 | |
| 1152 | if (MemSize < 4096) |
| 1153 | MemSize = 4096; |
| 1154 | |
| 1155 | Head = pci_alloc_consistent(pci_dev, MemSize, &tmp); |
| 1156 | PARingBufferHead = tmp; |
| 1157 | |
| 1158 | if (!Head) |
| 1159 | return -ENOMEM; |
| 1160 | |
| 1161 | memset(Head, 0, MemSize); |
| 1162 | |
| 1163 | PARingBufferCur = PARingBufferHead; |
| 1164 | Cur = Head; |
| 1165 | |
| 1166 | for (i = 0; i < NumBuffers - 1; i++) { |
| 1167 | Next = (struct SBufferHeader *) |
| 1168 | (((u8 *) Cur) + SIZEOF_SBufferHeader); |
| 1169 | PARingBufferNext = PARingBufferCur + SIZEOF_SBufferHeader; |
| 1170 | Cur->Next = Next; |
| 1171 | Cur->ngeneBuffer.Next = PARingBufferNext; |
| 1172 | Cur = Next; |
| 1173 | PARingBufferCur = PARingBufferNext; |
| 1174 | } |
| 1175 | /* Last Buffer points back to first one */ |
| 1176 | Cur->Next = Head; |
| 1177 | Cur->ngeneBuffer.Next = PARingBufferHead; |
| 1178 | |
| 1179 | descr->Head = Head; |
| 1180 | descr->MemSize = MemSize; |
| 1181 | descr->PAHead = PARingBufferHead; |
| 1182 | descr->NumBuffers = NumBuffers; |
| 1183 | |
| 1184 | return 0; |
| 1185 | } |
| 1186 | |
| 1187 | static int AllocateRingBuffers(struct pci_dev *pci_dev, |
| 1188 | dma_addr_t of, |
| 1189 | struct SRingBufferDescriptor *pRingBuffer, |
| 1190 | u32 Buffer1Length, u32 Buffer2Length) |
| 1191 | { |
| 1192 | dma_addr_t tmp; |
| 1193 | u32 i, j; |
| 1194 | int status = 0; |
| 1195 | u32 SCListMemSize = pRingBuffer->NumBuffers |
| 1196 | * ((Buffer2Length != 0) ? (NUM_SCATTER_GATHER_ENTRIES * 2) : |
| 1197 | NUM_SCATTER_GATHER_ENTRIES) |
| 1198 | * sizeof(struct HW_SCATTER_GATHER_ELEMENT); |
| 1199 | |
| 1200 | u64 PASCListMem; |
| 1201 | PHW_SCATTER_GATHER_ELEMENT SCListEntry; |
| 1202 | u64 PASCListEntry; |
| 1203 | struct SBufferHeader *Cur; |
| 1204 | void *SCListMem; |
| 1205 | |
| 1206 | if (SCListMemSize < 4096) |
| 1207 | SCListMemSize = 4096; |
| 1208 | |
| 1209 | SCListMem = pci_alloc_consistent(pci_dev, SCListMemSize, &tmp); |
| 1210 | |
| 1211 | PASCListMem = tmp; |
| 1212 | if (SCListMem == NULL) |
| 1213 | return -ENOMEM; |
| 1214 | |
| 1215 | memset(SCListMem, 0, SCListMemSize); |
| 1216 | |
| 1217 | pRingBuffer->SCListMem = SCListMem; |
| 1218 | pRingBuffer->PASCListMem = PASCListMem; |
| 1219 | pRingBuffer->SCListMemSize = SCListMemSize; |
| 1220 | pRingBuffer->Buffer1Length = Buffer1Length; |
| 1221 | pRingBuffer->Buffer2Length = Buffer2Length; |
| 1222 | |
| 1223 | SCListEntry = (PHW_SCATTER_GATHER_ELEMENT) SCListMem; |
| 1224 | PASCListEntry = PASCListMem; |
| 1225 | Cur = pRingBuffer->Head; |
| 1226 | |
| 1227 | for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) { |
| 1228 | u64 PABuffer; |
| 1229 | |
| 1230 | void *Buffer = pci_alloc_consistent(pci_dev, Buffer1Length, |
| 1231 | &tmp); |
| 1232 | PABuffer = tmp; |
| 1233 | |
| 1234 | if (Buffer == NULL) |
| 1235 | return -ENOMEM; |
| 1236 | |
| 1237 | Cur->Buffer1 = Buffer; |
| 1238 | |
| 1239 | SCListEntry->Address = PABuffer; |
| 1240 | SCListEntry->Length = Buffer1Length; |
| 1241 | |
| 1242 | Cur->scList1 = SCListEntry; |
| 1243 | Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry; |
| 1244 | Cur->ngeneBuffer.Number_of_entries_1 = |
| 1245 | NUM_SCATTER_GATHER_ENTRIES; |
| 1246 | |
| 1247 | SCListEntry += 1; |
| 1248 | PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); |
| 1249 | |
| 1250 | #if NUM_SCATTER_GATHER_ENTRIES > 1 |
| 1251 | for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) { |
| 1252 | SCListEntry->Address = of; |
| 1253 | SCListEntry->Length = OVERFLOW_BUFFER_SIZE; |
| 1254 | SCListEntry += 1; |
| 1255 | PASCListEntry += |
| 1256 | sizeof(struct HW_SCATTER_GATHER_ELEMENT); |
| 1257 | } |
| 1258 | #endif |
| 1259 | |
| 1260 | if (!Buffer2Length) |
| 1261 | continue; |
| 1262 | |
| 1263 | Buffer = pci_alloc_consistent(pci_dev, Buffer2Length, &tmp); |
| 1264 | PABuffer = tmp; |
| 1265 | |
| 1266 | if (Buffer == NULL) |
| 1267 | return -ENOMEM; |
| 1268 | |
| 1269 | Cur->Buffer2 = Buffer; |
| 1270 | |
| 1271 | SCListEntry->Address = PABuffer; |
| 1272 | SCListEntry->Length = Buffer2Length; |
| 1273 | |
| 1274 | Cur->scList2 = SCListEntry; |
| 1275 | Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry; |
| 1276 | Cur->ngeneBuffer.Number_of_entries_2 = |
| 1277 | NUM_SCATTER_GATHER_ENTRIES; |
| 1278 | |
| 1279 | SCListEntry += 1; |
| 1280 | PASCListEntry += sizeof(struct HW_SCATTER_GATHER_ELEMENT); |
| 1281 | |
| 1282 | #if NUM_SCATTER_GATHER_ENTRIES > 1 |
| 1283 | for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) { |
| 1284 | SCListEntry->Address = of; |
| 1285 | SCListEntry->Length = OVERFLOW_BUFFER_SIZE; |
| 1286 | SCListEntry += 1; |
| 1287 | PASCListEntry += |
| 1288 | sizeof(struct HW_SCATTER_GATHER_ELEMENT); |
| 1289 | } |
| 1290 | #endif |
| 1291 | |
| 1292 | } |
| 1293 | |
| 1294 | return status; |
| 1295 | } |
| 1296 | |
| 1297 | static int FillTSIdleBuffer(struct SRingBufferDescriptor *pIdleBuffer, |
| 1298 | struct SRingBufferDescriptor *pRingBuffer) |
| 1299 | { |
| 1300 | int status = 0; |
| 1301 | |
| 1302 | /* Copy pointer to scatter gather list in TSRingbuffer |
| 1303 | structure for buffer 2 |
| 1304 | Load number of buffer |
| 1305 | */ |
| 1306 | u32 n = pRingBuffer->NumBuffers; |
| 1307 | |
| 1308 | /* Point to first buffer entry */ |
| 1309 | struct SBufferHeader *Cur = pRingBuffer->Head; |
| 1310 | int i; |
| 1311 | /* Loop thru all buffer and set Buffer 2 pointers to TSIdlebuffer */ |
| 1312 | for (i = 0; i < n; i++) { |
| 1313 | Cur->Buffer2 = pIdleBuffer->Head->Buffer1; |
| 1314 | Cur->scList2 = pIdleBuffer->Head->scList1; |
| 1315 | Cur->ngeneBuffer.Address_of_first_entry_2 = |
| 1316 | pIdleBuffer->Head->ngeneBuffer. |
| 1317 | Address_of_first_entry_1; |
| 1318 | Cur->ngeneBuffer.Number_of_entries_2 = |
| 1319 | pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; |
| 1320 | Cur = Cur->Next; |
| 1321 | } |
| 1322 | return status; |
| 1323 | } |
| 1324 | |
| 1325 | static u32 RingBufferSizes[MAX_STREAM] = { |
| 1326 | RING_SIZE_VIDEO, |
| 1327 | RING_SIZE_VIDEO, |
| 1328 | RING_SIZE_AUDIO, |
| 1329 | RING_SIZE_AUDIO, |
| 1330 | RING_SIZE_AUDIO, |
| 1331 | }; |
| 1332 | |
| 1333 | static u32 Buffer1Sizes[MAX_STREAM] = { |
| 1334 | MAX_VIDEO_BUFFER_SIZE, |
| 1335 | MAX_VIDEO_BUFFER_SIZE, |
| 1336 | MAX_AUDIO_BUFFER_SIZE, |
| 1337 | MAX_AUDIO_BUFFER_SIZE, |
| 1338 | MAX_AUDIO_BUFFER_SIZE |
| 1339 | }; |
| 1340 | |
| 1341 | static u32 Buffer2Sizes[MAX_STREAM] = { |
| 1342 | MAX_VBI_BUFFER_SIZE, |
| 1343 | MAX_VBI_BUFFER_SIZE, |
| 1344 | 0, |
| 1345 | 0, |
| 1346 | 0 |
| 1347 | }; |
| 1348 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1349 | |
| 1350 | static int AllocCommonBuffers(struct ngene *dev) |
| 1351 | { |
| 1352 | int status = 0, i; |
| 1353 | |
| 1354 | dev->FWInterfaceBuffer = pci_alloc_consistent(dev->pci_dev, 4096, |
| 1355 | &dev->PAFWInterfaceBuffer); |
| 1356 | if (!dev->FWInterfaceBuffer) |
| 1357 | return -ENOMEM; |
| 1358 | dev->hosttongene = dev->FWInterfaceBuffer; |
| 1359 | dev->ngenetohost = dev->FWInterfaceBuffer + 256; |
| 1360 | dev->EventBuffer = dev->FWInterfaceBuffer + 512; |
| 1361 | |
| 1362 | dev->OverflowBuffer = pci_alloc_consistent(dev->pci_dev, |
| 1363 | OVERFLOW_BUFFER_SIZE, |
| 1364 | &dev->PAOverflowBuffer); |
| 1365 | if (!dev->OverflowBuffer) |
| 1366 | return -ENOMEM; |
| 1367 | memset(dev->OverflowBuffer, 0, OVERFLOW_BUFFER_SIZE); |
| 1368 | |
| 1369 | for (i = STREAM_VIDEOIN1; i < MAX_STREAM; i++) { |
| 1370 | int type = dev->card_info->io_type[i]; |
| 1371 | |
| 1372 | dev->channel[i].State = KSSTATE_STOP; |
| 1373 | |
| 1374 | if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) { |
| 1375 | status = create_ring_buffer(dev->pci_dev, |
| 1376 | &dev->channel[i].RingBuffer, |
| 1377 | RingBufferSizes[i]); |
| 1378 | if (status < 0) |
| 1379 | break; |
| 1380 | |
| 1381 | if (type & (NGENE_IO_TV | NGENE_IO_AIN)) { |
| 1382 | status = AllocateRingBuffers(dev->pci_dev, |
| 1383 | dev-> |
| 1384 | PAOverflowBuffer, |
| 1385 | &dev->channel[i]. |
| 1386 | RingBuffer, |
| 1387 | Buffer1Sizes[i], |
| 1388 | Buffer2Sizes[i]); |
| 1389 | if (status < 0) |
| 1390 | break; |
| 1391 | } else if (type & NGENE_IO_HDTV) { |
| 1392 | status = AllocateRingBuffers(dev->pci_dev, |
| 1393 | dev-> |
| 1394 | PAOverflowBuffer, |
| 1395 | &dev->channel[i]. |
| 1396 | RingBuffer, |
| 1397 | MAX_HDTV_BUFFER_SIZE, |
| 1398 | 0); |
| 1399 | if (status < 0) |
| 1400 | break; |
| 1401 | } |
| 1402 | } |
| 1403 | |
| 1404 | if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { |
| 1405 | |
| 1406 | status = create_ring_buffer(dev->pci_dev, |
| 1407 | &dev->channel[i]. |
| 1408 | TSRingBuffer, RING_SIZE_TS); |
| 1409 | if (status < 0) |
| 1410 | break; |
| 1411 | |
| 1412 | status = AllocateRingBuffers(dev->pci_dev, |
| 1413 | dev->PAOverflowBuffer, |
| 1414 | &dev->channel[i]. |
| 1415 | TSRingBuffer, |
| 1416 | MAX_TS_BUFFER_SIZE, 0); |
| 1417 | if (status) |
| 1418 | break; |
| 1419 | } |
| 1420 | |
| 1421 | if (type & NGENE_IO_TSOUT) { |
| 1422 | status = create_ring_buffer(dev->pci_dev, |
| 1423 | &dev->channel[i]. |
| 1424 | TSIdleBuffer, 1); |
| 1425 | if (status < 0) |
| 1426 | break; |
| 1427 | status = AllocateRingBuffers(dev->pci_dev, |
| 1428 | dev->PAOverflowBuffer, |
| 1429 | &dev->channel[i]. |
| 1430 | TSIdleBuffer, |
| 1431 | MAX_TS_BUFFER_SIZE, 0); |
| 1432 | if (status) |
| 1433 | break; |
| 1434 | FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer, |
| 1435 | &dev->channel[i].TSRingBuffer); |
| 1436 | } |
| 1437 | } |
| 1438 | return status; |
| 1439 | } |
| 1440 | |
| 1441 | static void ngene_release_buffers(struct ngene *dev) |
| 1442 | { |
| 1443 | if (dev->iomem) |
| 1444 | iounmap(dev->iomem); |
| 1445 | free_common_buffers(dev); |
| 1446 | vfree(dev->tsout_buf); |
| 1447 | vfree(dev->ain_buf); |
| 1448 | vfree(dev->vin_buf); |
| 1449 | vfree(dev); |
| 1450 | } |
| 1451 | |
| 1452 | static int ngene_get_buffers(struct ngene *dev) |
| 1453 | { |
| 1454 | if (AllocCommonBuffers(dev)) |
| 1455 | return -ENOMEM; |
| 1456 | if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) { |
| 1457 | dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE); |
| 1458 | if (!dev->tsout_buf) |
| 1459 | return -ENOMEM; |
| 1460 | dvb_ringbuffer_init(&dev->tsout_rbuf, |
| 1461 | dev->tsout_buf, TSOUT_BUF_SIZE); |
| 1462 | } |
| 1463 | if (dev->card_info->io_type[2] & NGENE_IO_AIN) { |
| 1464 | dev->ain_buf = vmalloc(AIN_BUF_SIZE); |
| 1465 | if (!dev->ain_buf) |
| 1466 | return -ENOMEM; |
| 1467 | dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE); |
| 1468 | } |
| 1469 | if (dev->card_info->io_type[0] & NGENE_IO_HDTV) { |
| 1470 | dev->vin_buf = vmalloc(VIN_BUF_SIZE); |
| 1471 | if (!dev->vin_buf) |
| 1472 | return -ENOMEM; |
| 1473 | dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE); |
| 1474 | } |
| 1475 | dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0), |
| 1476 | pci_resource_len(dev->pci_dev, 0)); |
| 1477 | if (!dev->iomem) |
| 1478 | return -ENOMEM; |
| 1479 | |
| 1480 | return 0; |
| 1481 | } |
| 1482 | |
| 1483 | static void ngene_init(struct ngene *dev) |
| 1484 | { |
| 1485 | int i; |
| 1486 | |
| 1487 | tasklet_init(&dev->event_tasklet, event_tasklet, (unsigned long)dev); |
| 1488 | |
| 1489 | memset_io(dev->iomem + 0xc000, 0x00, 0x220); |
| 1490 | memset_io(dev->iomem + 0xc400, 0x00, 0x100); |
| 1491 | |
| 1492 | for (i = 0; i < MAX_STREAM; i++) { |
| 1493 | dev->channel[i].dev = dev; |
| 1494 | dev->channel[i].number = i; |
| 1495 | } |
| 1496 | |
| 1497 | dev->fw_interface_version = 0; |
| 1498 | |
| 1499 | ngwritel(0, NGENE_INT_ENABLE); |
| 1500 | |
| 1501 | dev->icounts = ngreadl(NGENE_INT_COUNTS); |
| 1502 | |
| 1503 | dev->device_version = ngreadl(DEV_VER) & 0x0f; |
| 1504 | printk(KERN_INFO DEVICE_NAME ": Device version %d\n", |
| 1505 | dev->device_version); |
| 1506 | } |
| 1507 | |
| 1508 | static int ngene_load_firm(struct ngene *dev) |
| 1509 | { |
| 1510 | u32 size; |
| 1511 | const struct firmware *fw = NULL; |
| 1512 | u8 *ngene_fw; |
| 1513 | char *fw_name; |
| 1514 | int err, version; |
| 1515 | |
| 1516 | version = dev->card_info->fw_version; |
| 1517 | |
| 1518 | switch (version) { |
| 1519 | default: |
| 1520 | case 15: |
| 1521 | version = 15; |
Oliver Endriss | 0027ebb | 2009-12-19 06:38:05 -0300 | [diff] [blame] | 1522 | size = 23466; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1523 | fw_name = "ngene_15.fw"; |
| 1524 | break; |
| 1525 | case 16: |
Oliver Endriss | 0027ebb | 2009-12-19 06:38:05 -0300 | [diff] [blame] | 1526 | size = 23498; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1527 | fw_name = "ngene_16.fw"; |
| 1528 | break; |
| 1529 | case 17: |
Oliver Endriss | 0027ebb | 2009-12-19 06:38:05 -0300 | [diff] [blame] | 1530 | size = 24446; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1531 | fw_name = "ngene_17.fw"; |
| 1532 | break; |
| 1533 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1534 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1535 | if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { |
| 1536 | printk(KERN_ERR DEVICE_NAME |
Oliver Endriss | 0027ebb | 2009-12-19 06:38:05 -0300 | [diff] [blame] | 1537 | ": Could not load firmware file %s.\n", fw_name); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1538 | printk(KERN_INFO DEVICE_NAME |
| 1539 | ": Copy %s to your hotplug directory!\n", fw_name); |
| 1540 | return -1; |
| 1541 | } |
Oliver Endriss | 0027ebb | 2009-12-19 06:38:05 -0300 | [diff] [blame] | 1542 | if (size != fw->size) { |
| 1543 | printk(KERN_ERR DEVICE_NAME |
| 1544 | ": Firmware %s has invalid size!", fw_name); |
| 1545 | err = -1; |
| 1546 | } else { |
| 1547 | printk(KERN_INFO DEVICE_NAME |
| 1548 | ": Loading firmware file %s.\n", fw_name); |
| 1549 | ngene_fw = (u8 *) fw->data; |
| 1550 | err = ngene_command_load_firmware(dev, ngene_fw, size); |
| 1551 | } |
| 1552 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1553 | release_firmware(fw); |
Oliver Endriss | 0027ebb | 2009-12-19 06:38:05 -0300 | [diff] [blame] | 1554 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1555 | return err; |
| 1556 | } |
| 1557 | |
| 1558 | static void ngene_stop(struct ngene *dev) |
| 1559 | { |
| 1560 | down(&dev->cmd_mutex); |
| 1561 | i2c_del_adapter(&(dev->channel[0].i2c_adapter)); |
| 1562 | i2c_del_adapter(&(dev->channel[1].i2c_adapter)); |
| 1563 | ngwritel(0, NGENE_INT_ENABLE); |
| 1564 | ngwritel(0, NGENE_COMMAND); |
| 1565 | ngwritel(0, NGENE_COMMAND_HI); |
| 1566 | ngwritel(0, NGENE_STATUS); |
| 1567 | ngwritel(0, NGENE_STATUS_HI); |
| 1568 | ngwritel(0, NGENE_EVENT); |
| 1569 | ngwritel(0, NGENE_EVENT_HI); |
| 1570 | free_irq(dev->pci_dev->irq, dev); |
| 1571 | } |
| 1572 | |
| 1573 | static int ngene_start(struct ngene *dev) |
| 1574 | { |
| 1575 | int stat; |
| 1576 | int i; |
| 1577 | |
| 1578 | pci_set_master(dev->pci_dev); |
| 1579 | ngene_init(dev); |
| 1580 | |
| 1581 | stat = request_irq(dev->pci_dev->irq, irq_handler, |
| 1582 | IRQF_SHARED, "nGene", |
| 1583 | (void *)dev); |
| 1584 | if (stat < 0) |
| 1585 | return stat; |
| 1586 | |
| 1587 | init_waitqueue_head(&dev->cmd_wq); |
| 1588 | init_waitqueue_head(&dev->tx_wq); |
| 1589 | init_waitqueue_head(&dev->rx_wq); |
| 1590 | sema_init(&dev->cmd_mutex, 1); |
| 1591 | sema_init(&dev->stream_mutex, 1); |
| 1592 | sema_init(&dev->pll_mutex, 1); |
| 1593 | sema_init(&dev->i2c_switch_mutex, 1); |
| 1594 | spin_lock_init(&dev->cmd_lock); |
| 1595 | for (i = 0; i < MAX_STREAM; i++) |
| 1596 | spin_lock_init(&dev->channel[i].state_lock); |
| 1597 | ngwritel(1, TIMESTAMPS); |
| 1598 | |
| 1599 | ngwritel(1, NGENE_INT_ENABLE); |
| 1600 | |
| 1601 | stat = ngene_load_firm(dev); |
| 1602 | if (stat < 0) |
| 1603 | goto fail; |
| 1604 | |
| 1605 | stat = ngene_i2c_init(dev, 0); |
| 1606 | if (stat < 0) |
| 1607 | goto fail; |
| 1608 | |
| 1609 | stat = ngene_i2c_init(dev, 1); |
| 1610 | if (stat < 0) |
| 1611 | goto fail; |
| 1612 | |
| 1613 | if (dev->card_info->fw_version == 17) { |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1614 | u8 tsin4_config[6] = |
| 1615 | {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0}; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1616 | u8 default_config[6] = |
| 1617 | {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0}; |
| 1618 | u8 *bconf = default_config; |
| 1619 | |
| 1620 | if (dev->card_info->io_type[3] == NGENE_IO_TSIN) |
| 1621 | bconf = tsin4_config; |
Oliver Endriss | 44cdd06 | 2009-12-20 02:30:52 -0300 | [diff] [blame] | 1622 | dprintk(KERN_DEBUG DEVICE_NAME ": FW 17 buffer config\n"); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1623 | stat = ngene_command_config_free_buf(dev, bconf); |
| 1624 | } else { |
| 1625 | int bconf = BUFFER_CONFIG_4422; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1626 | if (dev->card_info->io_type[3] == NGENE_IO_TSIN) |
| 1627 | bconf = BUFFER_CONFIG_3333; |
| 1628 | stat = ngene_command_config_buf(dev, bconf); |
| 1629 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1630 | return stat; |
| 1631 | fail: |
| 1632 | ngwritel(0, NGENE_INT_ENABLE); |
| 1633 | free_irq(dev->pci_dev->irq, dev); |
| 1634 | return stat; |
| 1635 | } |
| 1636 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1637 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1638 | |
| 1639 | /****************************************************************************/ |
| 1640 | /* Switch control (I2C gates, etc.) *****************************************/ |
| 1641 | /****************************************************************************/ |
| 1642 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1643 | |
| 1644 | /****************************************************************************/ |
| 1645 | /* Demod/tuner attachment ***************************************************/ |
| 1646 | /****************************************************************************/ |
| 1647 | |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1648 | static int tuner_attach_stv6110(struct ngene_channel *chan) |
| 1649 | { |
| 1650 | struct stv090x_config *feconf = (struct stv090x_config *) |
| 1651 | chan->dev->card_info->fe_config[chan->number]; |
| 1652 | struct stv6110x_config *tunerconf = (struct stv6110x_config *) |
| 1653 | chan->dev->card_info->tuner_config[chan->number]; |
| 1654 | struct stv6110x_devctl *ctl; |
| 1655 | |
| 1656 | ctl = dvb_attach(stv6110x_attach, chan->fe, tunerconf, |
| 1657 | &chan->i2c_adapter); |
| 1658 | if (ctl == NULL) { |
| 1659 | printk(KERN_ERR DEVICE_NAME ": No STV6110X found!\n"); |
| 1660 | return -ENODEV; |
| 1661 | } |
| 1662 | |
| 1663 | feconf->tuner_init = ctl->tuner_init; |
| 1664 | feconf->tuner_set_mode = ctl->tuner_set_mode; |
| 1665 | feconf->tuner_set_frequency = ctl->tuner_set_frequency; |
| 1666 | feconf->tuner_get_frequency = ctl->tuner_get_frequency; |
| 1667 | feconf->tuner_set_bandwidth = ctl->tuner_set_bandwidth; |
| 1668 | feconf->tuner_get_bandwidth = ctl->tuner_get_bandwidth; |
| 1669 | feconf->tuner_set_bbgain = ctl->tuner_set_bbgain; |
| 1670 | feconf->tuner_get_bbgain = ctl->tuner_get_bbgain; |
| 1671 | feconf->tuner_set_refclk = ctl->tuner_set_refclk; |
| 1672 | feconf->tuner_get_status = ctl->tuner_get_status; |
| 1673 | |
| 1674 | return 0; |
| 1675 | } |
| 1676 | |
| 1677 | |
| 1678 | static int demod_attach_stv0900(struct ngene_channel *chan) |
| 1679 | { |
| 1680 | struct stv090x_config *feconf = (struct stv090x_config *) |
| 1681 | chan->dev->card_info->fe_config[chan->number]; |
| 1682 | |
| 1683 | chan->fe = dvb_attach(stv090x_attach, |
| 1684 | feconf, |
| 1685 | &chan->i2c_adapter, |
| 1686 | chan->number == 0 ? STV090x_DEMODULATOR_0 : |
| 1687 | STV090x_DEMODULATOR_1); |
| 1688 | if (chan->fe == NULL) { |
| 1689 | printk(KERN_ERR DEVICE_NAME ": No STV0900 found!\n"); |
| 1690 | return -ENODEV; |
| 1691 | } |
| 1692 | |
| 1693 | if (!dvb_attach(lnbh24_attach, chan->fe, &chan->i2c_adapter, 0, |
| 1694 | 0, chan->dev->card_info->lnb[chan->number])) { |
| 1695 | printk(KERN_ERR DEVICE_NAME ": No LNBH24 found!\n"); |
| 1696 | dvb_frontend_detach(chan->fe); |
| 1697 | return -ENODEV; |
| 1698 | } |
| 1699 | |
| 1700 | return 0; |
| 1701 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1702 | |
| 1703 | /****************************************************************************/ |
| 1704 | /****************************************************************************/ |
| 1705 | /****************************************************************************/ |
| 1706 | |
| 1707 | static void release_channel(struct ngene_channel *chan) |
| 1708 | { |
| 1709 | struct dvb_demux *dvbdemux = &chan->demux; |
| 1710 | struct ngene *dev = chan->dev; |
| 1711 | struct ngene_info *ni = dev->card_info; |
| 1712 | int io = ni->io_type[chan->number]; |
| 1713 | |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 1714 | #ifdef COMMAND_TIMEOUT_WORKAROUND |
| 1715 | if (chan->running) |
| 1716 | set_transfer(chan, 0); |
| 1717 | #endif |
| 1718 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1719 | tasklet_kill(&chan->demux_tasklet); |
| 1720 | |
| 1721 | if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1722 | if (chan->fe) { |
| 1723 | dvb_unregister_frontend(chan->fe); |
Roland Praml | dc35c9a | 2009-12-19 22:48:14 -0300 | [diff] [blame] | 1724 | dvb_frontend_detach(chan->fe); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1725 | chan->fe = 0; |
| 1726 | } |
| 1727 | dvbdemux->dmx.close(&dvbdemux->dmx); |
| 1728 | dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, |
| 1729 | &chan->hw_frontend); |
| 1730 | dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, |
| 1731 | &chan->mem_frontend); |
| 1732 | dvb_dmxdev_release(&chan->dmxdev); |
| 1733 | dvb_dmx_release(&chan->demux); |
Matthias Benesch | cf1b12f | 2009-12-23 05:55:02 -0300 | [diff] [blame] | 1734 | |
| 1735 | if (chan->number == 0 || !one_adapter) |
| 1736 | dvb_unregister_adapter(&dev->adapter[chan->number]); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1737 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1738 | } |
| 1739 | |
| 1740 | static int init_channel(struct ngene_channel *chan) |
| 1741 | { |
| 1742 | int ret = 0, nr = chan->number; |
Oliver Endriss | 948a119 | 2009-12-22 03:34:29 -0300 | [diff] [blame] | 1743 | struct dvb_adapter *adapter = NULL; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1744 | struct dvb_demux *dvbdemux = &chan->demux; |
| 1745 | struct ngene *dev = chan->dev; |
| 1746 | struct ngene_info *ni = dev->card_info; |
| 1747 | int io = ni->io_type[nr]; |
| 1748 | |
| 1749 | tasklet_init(&chan->demux_tasklet, demux_tasklet, (unsigned long)chan); |
| 1750 | chan->users = 0; |
| 1751 | chan->type = io; |
| 1752 | chan->mode = chan->type; /* for now only one mode */ |
| 1753 | |
| 1754 | if (io & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { |
| 1755 | if (nr >= STREAM_AUDIOIN1) |
| 1756 | chan->DataFormatFlags = DF_SWAP32; |
Matthias Benesch | cf1b12f | 2009-12-23 05:55:02 -0300 | [diff] [blame] | 1757 | if (nr == 0 || !one_adapter) { |
| 1758 | adapter = &dev->adapter[nr]; |
| 1759 | ret = dvb_register_adapter(adapter, "nGene", |
| 1760 | THIS_MODULE, |
| 1761 | &chan->dev->pci_dev->dev, |
| 1762 | adapter_nr); |
| 1763 | if (ret < 0) |
| 1764 | return ret; |
| 1765 | } else { |
| 1766 | adapter = &dev->adapter[0]; |
| 1767 | } |
| 1768 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1769 | ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux", |
| 1770 | ngene_start_feed, |
| 1771 | ngene_stop_feed, chan); |
| 1772 | ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, |
| 1773 | &chan->hw_frontend, |
| 1774 | &chan->mem_frontend, adapter); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1775 | } |
| 1776 | |
| 1777 | if (io & NGENE_IO_TSIN) { |
| 1778 | chan->fe = NULL; |
| 1779 | if (ni->demod_attach[nr]) |
| 1780 | ni->demod_attach[nr](chan); |
| 1781 | if (chan->fe) { |
| 1782 | if (dvb_register_frontend(adapter, chan->fe) < 0) { |
| 1783 | if (chan->fe->ops.release) |
| 1784 | chan->fe->ops.release(chan->fe); |
| 1785 | chan->fe = NULL; |
| 1786 | } |
| 1787 | } |
| 1788 | if (chan->fe && ni->tuner_attach[nr]) |
| 1789 | if (ni->tuner_attach[nr] (chan) < 0) { |
| 1790 | printk(KERN_ERR DEVICE_NAME |
| 1791 | ": Tuner attach failed on channel %d!\n", |
| 1792 | nr); |
| 1793 | } |
| 1794 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1795 | return ret; |
| 1796 | } |
| 1797 | |
| 1798 | static int init_channels(struct ngene *dev) |
| 1799 | { |
| 1800 | int i, j; |
| 1801 | |
| 1802 | for (i = 0; i < MAX_STREAM; i++) { |
| 1803 | if (init_channel(&dev->channel[i]) < 0) { |
Matthias Benesch | cf1b12f | 2009-12-23 05:55:02 -0300 | [diff] [blame] | 1804 | for (j = i - 1; j >= 0; j--) |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1805 | release_channel(&dev->channel[j]); |
| 1806 | return -1; |
| 1807 | } |
| 1808 | } |
| 1809 | return 0; |
| 1810 | } |
| 1811 | |
| 1812 | /****************************************************************************/ |
| 1813 | /* device probe/remove calls ************************************************/ |
| 1814 | /****************************************************************************/ |
| 1815 | |
| 1816 | static void __devexit ngene_remove(struct pci_dev *pdev) |
| 1817 | { |
| 1818 | struct ngene *dev = (struct ngene *)pci_get_drvdata(pdev); |
| 1819 | int i; |
| 1820 | |
| 1821 | tasklet_kill(&dev->event_tasklet); |
Matthias Benesch | cf1b12f | 2009-12-23 05:55:02 -0300 | [diff] [blame] | 1822 | for (i = MAX_STREAM - 1; i >= 0; i--) |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1823 | release_channel(&dev->channel[i]); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1824 | ngene_stop(dev); |
| 1825 | ngene_release_buffers(dev); |
| 1826 | pci_set_drvdata(pdev, 0); |
| 1827 | pci_disable_device(pdev); |
| 1828 | } |
| 1829 | |
| 1830 | static int __devinit ngene_probe(struct pci_dev *pci_dev, |
| 1831 | const struct pci_device_id *id) |
| 1832 | { |
| 1833 | struct ngene *dev; |
| 1834 | int stat = 0; |
| 1835 | |
| 1836 | if (pci_enable_device(pci_dev) < 0) |
| 1837 | return -ENODEV; |
| 1838 | |
| 1839 | dev = vmalloc(sizeof(struct ngene)); |
Roland Praml | dc35c9a | 2009-12-19 22:48:14 -0300 | [diff] [blame] | 1840 | if (dev == NULL) { |
| 1841 | stat = -ENOMEM; |
| 1842 | goto fail0; |
| 1843 | } |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1844 | memset(dev, 0, sizeof(struct ngene)); |
| 1845 | |
| 1846 | dev->pci_dev = pci_dev; |
| 1847 | dev->card_info = (struct ngene_info *)id->driver_data; |
| 1848 | printk(KERN_INFO DEVICE_NAME ": Found %s\n", dev->card_info->name); |
| 1849 | |
| 1850 | pci_set_drvdata(pci_dev, dev); |
| 1851 | |
| 1852 | /* Alloc buffers and start nGene */ |
| 1853 | stat = ngene_get_buffers(dev); |
| 1854 | if (stat < 0) |
| 1855 | goto fail1; |
| 1856 | stat = ngene_start(dev); |
| 1857 | if (stat < 0) |
| 1858 | goto fail1; |
| 1859 | |
| 1860 | dev->i2c_current_bus = -1; |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1861 | |
| 1862 | /* Register DVB adapters and devices for both channels */ |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1863 | if (init_channels(dev) < 0) |
| 1864 | goto fail2; |
| 1865 | |
| 1866 | return 0; |
| 1867 | |
| 1868 | fail2: |
| 1869 | ngene_stop(dev); |
| 1870 | fail1: |
| 1871 | ngene_release_buffers(dev); |
Roland Praml | dc35c9a | 2009-12-19 22:48:14 -0300 | [diff] [blame] | 1872 | fail0: |
| 1873 | pci_disable_device(pci_dev); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1874 | pci_set_drvdata(pci_dev, 0); |
| 1875 | return stat; |
| 1876 | } |
| 1877 | |
| 1878 | /****************************************************************************/ |
| 1879 | /* Card configs *************************************************************/ |
| 1880 | /****************************************************************************/ |
| 1881 | |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1882 | static struct stv090x_config fe_cineS2 = { |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1883 | .device = STV0900, |
| 1884 | .demod_mode = STV090x_DUAL, |
| 1885 | .clk_mode = STV090x_CLK_EXT, |
| 1886 | |
| 1887 | .xtal = 27000000, |
| 1888 | .address = 0x68, |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1889 | |
| 1890 | .ts1_mode = STV090x_TSMODE_SERIAL_PUNCTURED, |
| 1891 | .ts2_mode = STV090x_TSMODE_SERIAL_PUNCTURED, |
| 1892 | |
| 1893 | .repeater_level = STV090x_RPTLEVEL_16, |
| 1894 | |
Oliver Endriss | 589816c | 2010-01-20 17:53:06 -0300 | [diff] [blame] | 1895 | .adc1_range = STV090x_ADC_1Vpp, |
| 1896 | .adc2_range = STV090x_ADC_1Vpp, |
| 1897 | |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1898 | .diseqc_envelope_mode = true, |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1899 | }; |
| 1900 | |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1901 | static struct stv6110x_config tuner_cineS2_0 = { |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1902 | .addr = 0x60, |
| 1903 | .refclk = 27000000, |
Oliver Endriss | 83e7455 | 2010-02-01 22:01:31 -0300 | [diff] [blame] | 1904 | .clk_div = 1, |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1905 | }; |
| 1906 | |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1907 | static struct stv6110x_config tuner_cineS2_1 = { |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1908 | .addr = 0x63, |
| 1909 | .refclk = 27000000, |
Oliver Endriss | 83e7455 | 2010-02-01 22:01:31 -0300 | [diff] [blame] | 1910 | .clk_div = 1, |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1911 | }; |
| 1912 | |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1913 | static struct ngene_info ngene_info_cineS2 = { |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1914 | .type = NGENE_SIDEWINDER, |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1915 | .name = "Linux4Media cineS2 DVB-S2 Twin Tuner", |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1916 | .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, |
| 1917 | .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, |
| 1918 | .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110}, |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1919 | .fe_config = {&fe_cineS2, &fe_cineS2}, |
| 1920 | .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1921 | .lnb = {0x0b, 0x08}, |
| 1922 | .tsf = {3, 3}, |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 1923 | .fw_version = 15, |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1924 | }; |
| 1925 | |
Matthias Benesch | edad22a | 2010-01-08 17:38:03 -0300 | [diff] [blame] | 1926 | static struct ngene_info ngene_info_satixs2 = { |
| 1927 | .type = NGENE_SIDEWINDER, |
| 1928 | .name = "Mystique SaTiX-S2 Dual", |
| 1929 | .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN}, |
| 1930 | .demod_attach = {demod_attach_stv0900, demod_attach_stv0900}, |
| 1931 | .tuner_attach = {tuner_attach_stv6110, tuner_attach_stv6110}, |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1932 | .fe_config = {&fe_cineS2, &fe_cineS2}, |
| 1933 | .tuner_config = {&tuner_cineS2_0, &tuner_cineS2_1}, |
Matthias Benesch | edad22a | 2010-01-08 17:38:03 -0300 | [diff] [blame] | 1934 | .lnb = {0x0b, 0x08}, |
| 1935 | .tsf = {3, 3}, |
Oliver Endriss | b1ec953 | 2010-01-20 18:06:51 -0300 | [diff] [blame] | 1936 | .fw_version = 15, |
Matthias Benesch | edad22a | 2010-01-08 17:38:03 -0300 | [diff] [blame] | 1937 | }; |
| 1938 | |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1939 | /****************************************************************************/ |
| 1940 | |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1941 | |
| 1942 | |
| 1943 | /****************************************************************************/ |
Matthias Benesch | edad22a | 2010-01-08 17:38:03 -0300 | [diff] [blame] | 1944 | /* PCI Subsystem ID *********************************************************/ |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1945 | /****************************************************************************/ |
| 1946 | |
| 1947 | #define NGENE_ID(_subvend, _subdev, _driverdata) { \ |
| 1948 | .vendor = NGENE_VID, .device = NGENE_PID, \ |
| 1949 | .subvendor = _subvend, .subdevice = _subdev, \ |
| 1950 | .driver_data = (unsigned long) &_driverdata } |
| 1951 | |
| 1952 | /****************************************************************************/ |
| 1953 | |
| 1954 | static const struct pci_device_id ngene_id_tbl[] __devinitdata = { |
Oliver Endriss | e890e7c | 2010-02-03 13:57:58 -0300 | [diff] [blame^] | 1955 | NGENE_ID(0x18c3, 0xabc3, ngene_info_cineS2), |
| 1956 | NGENE_ID(0x18c3, 0xabc4, ngene_info_cineS2), |
Matthias Benesch | edad22a | 2010-01-08 17:38:03 -0300 | [diff] [blame] | 1957 | NGENE_ID(0x18c3, 0xdb01, ngene_info_satixs2), |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1958 | {0} |
| 1959 | }; |
Matthias Benesch | 8bba260 | 2009-12-19 12:48:22 -0300 | [diff] [blame] | 1960 | MODULE_DEVICE_TABLE(pci, ngene_id_tbl); |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 1961 | |
| 1962 | /****************************************************************************/ |
| 1963 | /* Init/Exit ****************************************************************/ |
| 1964 | /****************************************************************************/ |
| 1965 | |
| 1966 | static pci_ers_result_t ngene_error_detected(struct pci_dev *dev, |
| 1967 | enum pci_channel_state state) |
| 1968 | { |
| 1969 | printk(KERN_ERR DEVICE_NAME ": PCI error\n"); |
| 1970 | if (state == pci_channel_io_perm_failure) |
| 1971 | return PCI_ERS_RESULT_DISCONNECT; |
| 1972 | if (state == pci_channel_io_frozen) |
| 1973 | return PCI_ERS_RESULT_NEED_RESET; |
| 1974 | return PCI_ERS_RESULT_CAN_RECOVER; |
| 1975 | } |
| 1976 | |
| 1977 | static pci_ers_result_t ngene_link_reset(struct pci_dev *dev) |
| 1978 | { |
| 1979 | printk(KERN_INFO DEVICE_NAME ": link reset\n"); |
| 1980 | return 0; |
| 1981 | } |
| 1982 | |
| 1983 | static pci_ers_result_t ngene_slot_reset(struct pci_dev *dev) |
| 1984 | { |
| 1985 | printk(KERN_INFO DEVICE_NAME ": slot reset\n"); |
| 1986 | return 0; |
| 1987 | } |
| 1988 | |
| 1989 | static void ngene_resume(struct pci_dev *dev) |
| 1990 | { |
| 1991 | printk(KERN_INFO DEVICE_NAME ": resume\n"); |
| 1992 | } |
| 1993 | |
| 1994 | static struct pci_error_handlers ngene_errors = { |
| 1995 | .error_detected = ngene_error_detected, |
| 1996 | .link_reset = ngene_link_reset, |
| 1997 | .slot_reset = ngene_slot_reset, |
| 1998 | .resume = ngene_resume, |
| 1999 | }; |
| 2000 | |
| 2001 | static struct pci_driver ngene_pci_driver = { |
| 2002 | .name = "ngene", |
| 2003 | .id_table = ngene_id_tbl, |
| 2004 | .probe = ngene_probe, |
Roland Praml | dc35c9a | 2009-12-19 22:48:14 -0300 | [diff] [blame] | 2005 | .remove = __devexit_p(ngene_remove), |
Matthias Benesch | dae52d0 | 2009-12-18 22:13:26 -0300 | [diff] [blame] | 2006 | .err_handler = &ngene_errors, |
| 2007 | }; |
| 2008 | |
| 2009 | static __init int module_init_ngene(void) |
| 2010 | { |
| 2011 | printk(KERN_INFO |
| 2012 | "nGene PCIE bridge driver, Copyright (C) 2005-2007 Micronas\n"); |
| 2013 | return pci_register_driver(&ngene_pci_driver); |
| 2014 | } |
| 2015 | |
| 2016 | static __exit void module_exit_ngene(void) |
| 2017 | { |
| 2018 | pci_unregister_driver(&ngene_pci_driver); |
| 2019 | } |
| 2020 | |
| 2021 | module_init(module_init_ngene); |
| 2022 | module_exit(module_exit_ngene); |
| 2023 | |
| 2024 | MODULE_DESCRIPTION("nGene"); |
| 2025 | MODULE_AUTHOR("Micronas, Ralph Metzler, Manfred Voelkel"); |
| 2026 | MODULE_LICENSE("GPL"); |