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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * SBC82XX platform support
3 *
4 * Author: Guy Streeter <streeter@redhat.com>
5 *
6 * Derived from: est8260_setup.c by Allen Curtis, ONZ
7 *
8 * Copyright 2004 Red Hat, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/stddef.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/init.h>
20#include <linux/pci.h>
21
22#include <asm/mpc8260.h>
23#include <asm/machdep.h>
24#include <asm/io.h>
25#include <asm/todc.h>
26#include <asm/immap_cpm2.h>
27#include <asm/pci.h>
28
29static void (*callback_init_IRQ)(void);
30
31extern unsigned char __res[sizeof(bd_t)];
32
33extern void (*late_time_init)(void);
34
35#ifdef CONFIG_GEN_RTC
36TODC_ALLOC();
37
38/*
39 * Timer init happens before mem_init but after paging init, so we cannot
40 * directly use ioremap() at that time.
41 * late_time_init() is call after paging init.
42 */
43
44static void sbc82xx_time_init(void)
45{
46 volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
47
48 /* Set up CS11 for RTC chip */
49 mc->memc_br11=0;
50 mc->memc_or11=0xffff0836;
51 mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
52
53 TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
54
55 todc_info->nvram_data =
56 (unsigned int)ioremap(todc_info->nvram_data, 0x2000);
57 BUG_ON(!todc_info->nvram_data);
58 ppc_md.get_rtc_time = todc_get_rtc_time;
59 ppc_md.set_rtc_time = todc_set_rtc_time;
60 ppc_md.nvram_read_val = todc_direct_read_val;
61 ppc_md.nvram_write_val = todc_direct_write_val;
62 todc_time_init();
63}
64#endif /* CONFIG_GEN_RTC */
65
66static volatile char *sbc82xx_i8259_map;
67static char sbc82xx_i8259_mask = 0xff;
68static DEFINE_SPINLOCK(sbc82xx_i8259_lock);
69
70static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
71{
72 unsigned long flags;
73
74 irq_nr -= NR_SIU_INTS;
75
76 spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
77 sbc82xx_i8259_mask |= 1 << irq_nr;
78 (void) sbc82xx_i8259_map[1]; /* Dummy read */
79 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
80 sbc82xx_i8259_map[0] = 0x20; /* OCW2: Non-specific EOI */
81 spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
82}
83
84static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
85{
86 unsigned long flags;
87
88 irq_nr -= NR_SIU_INTS;
89
90 spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
91 sbc82xx_i8259_mask |= 1 << irq_nr;
92 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
93 spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
94}
95
96static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
97{
98 unsigned long flags;
99
100 irq_nr -= NR_SIU_INTS;
101
102 spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
103 sbc82xx_i8259_mask &= ~(1 << irq_nr);
104 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
105 spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
106}
107
108static void sbc82xx_i8259_end_irq(unsigned int irq)
109{
110 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
111 && irq_desc[irq].action)
112 sbc82xx_i8259_unmask_irq(irq);
113}
114
115
116struct hw_interrupt_type sbc82xx_i8259_ic = {
117 .typename = " i8259 ",
118 .enable = sbc82xx_i8259_unmask_irq,
119 .disable = sbc82xx_i8259_mask_irq,
120 .ack = sbc82xx_i8259_mask_and_ack_irq,
121 .end = sbc82xx_i8259_end_irq,
122};
123
Jeff Garzike8f39542007-10-31 05:15:20 -0400124static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125{
Jeff Garzike8f39542007-10-31 05:15:20 -0400126 int irq;
127
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 spin_lock(&sbc82xx_i8259_lock);
129
130 sbc82xx_i8259_map[0] = 0x0c; /* OCW3: Read IR register on RD# pulse */
131 irq = sbc82xx_i8259_map[0] & 7; /* Read IRR */
132
133 if (irq == 7) {
134 /* Possible spurious interrupt */
135 int isr;
136 sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */
137 isr = sbc82xx_i8259_map[0]; /* Read ISR */
138
139 if (!(isr & 0x80)) {
140 printk(KERN_INFO "Spurious i8259 interrupt\n");
141 return IRQ_HANDLED;
142 }
143 }
Al Viro39e3eb72006-10-09 12:48:42 +0100144 __do_IRQ(NR_SIU_INTS + irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 return IRQ_HANDLED;
146}
147
148static struct irqaction sbc82xx_i8259_irqaction = {
149 .handler = sbc82xx_i8259_demux,
Thomas Gleixnerbc59d282006-07-01 19:29:22 -0700150 .flags = IRQF_DISABLED,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 .mask = CPU_MASK_NONE,
152 .name = "i8259 demux",
153};
154
155void __init sbc82xx_init_IRQ(void)
156{
157 volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
158 volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
159 int i;
160
161 callback_init_IRQ();
162
163 /* u-boot doesn't always set the board up correctly */
164 mc->memc_br5 = 0;
165 mc->memc_or5 = 0xfff00856;
166 mc->memc_br5 = 0x22000801;
167
168 sbc82xx_i8259_map = ioremap(0x22008000, 2);
169 if (!sbc82xx_i8259_map) {
170 printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
171 return;
172 }
173
174 /* Set up the interrupt handlers for the i8259 IRQs */
175 for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
Ingo Molnard1bef4e2006-06-29 02:24:36 -0700176 irq_desc[i].chip = &sbc82xx_i8259_ic;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 irq_desc[i].status |= IRQ_LEVEL;
178 }
179
180 /* make IRQ6 level sensitive */
181 ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
182 irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
183
184 /* Initialise the i8259 */
185 sbc82xx_i8259_map[0] = 0x1b; /* ICW1: Level, no cascade, ICW4 */
186 sbc82xx_i8259_map[1] = 0x00; /* ICW2: vector base */
187 /* No ICW3 (no cascade) */
188 sbc82xx_i8259_map[1] = 0x01; /* ICW4: 8086 mode, normal EOI */
189
190 sbc82xx_i8259_map[0] = 0x0b; /* OCW3: Read IS register on RD# pulse */
191
192 sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
193
194 /* Request cascade IRQ */
195 if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) {
196 printk("Installation of i8259 IRQ demultiplexer failed.\n");
197 }
198}
199
200static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
201 unsigned char pin)
202{
203 static char pci_irq_table[][4] = {
204 /*
205 * PCI IDSEL/INTPIN->INTLINE
206 * A B C D
207 */
208 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 16 - PMC slot */
209 { SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1, -1 }, /* IDSEL 17 - CardBus */
210 { SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
211 };
212
213 const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
214
215 return PCI_IRQ_TABLE_LOOKUP;
216}
217
218static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev)
219{
220 uint32_t ctrl;
221
222 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0))
223 return;
224
225 printk(KERN_INFO "Setting up CardBus controller\n");
226
227 /* Set P2CCLK bit in System Control Register */
228 pci_read_config_dword(pdev, 0x80, &ctrl);
229 ctrl |= (1<<27);
230 pci_write_config_dword(pdev, 0x80, ctrl);
231
232 /* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */
233 pci_write_config_dword(pdev, 0x8c, 0x00c01d22);
234
235}
236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus);
237
238void __init
239m82xx_board_init(void)
240{
241 /* u-boot may be using one of the FCC Ethernet devices.
242 Use the MAC address to the SCC. */
243 __res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
244
245 /* Anything special for this platform */
246 callback_init_IRQ = ppc_md.init_IRQ;
247
248 ppc_md.init_IRQ = sbc82xx_init_IRQ;
249 ppc_md.pci_map_irq = sbc82xx_pci_map_irq;
250#ifdef CONFIG_GEN_RTC
251 ppc_md.time_init = NULL;
252 ppc_md.get_rtc_time = NULL;
253 ppc_md.set_rtc_time = NULL;
254 ppc_md.nvram_read_val = NULL;
255 ppc_md.nvram_write_val = NULL;
256 late_time_init = sbc82xx_time_init;
257#endif /* CONFIG_GEN_RTC */
258}