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gerrit-public.fairphone.software / kernel / msm-4.9 / e9010e2fdfe68360da374e31f7008a6d9935c783 / . / drivers / net / wireless / ath5k / phy.c
blob: 890ecce8bedc5b775c108370cefd2e0091a31bc7 [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1/*
2 * PHY functions
3 *
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22#include <linux/delay.h>
23
24#include "ath5k.h"
25#include "reg.h"
26#include "base.h"
27
28/* Struct to hold initial RF register values (RF Banks) */
29struct ath5k_ini_rf {
30 u8 rf_bank; /* check out ath5k_reg.h */
31 u16 rf_register; /* register address */
32 u32 rf_value[5]; /* register value for different modes (above) */
33};
34
35/*
36 * Mode-specific RF Gain table (64bytes) for RF5111/5112
37 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
38 * RF Gain values are included in AR5K_AR5210_INI)
39 */
40struct ath5k_ini_rfgain {
41 u16 rfg_register; /* RF Gain register address */
42 u32 rfg_value[2]; /* [freq (see below)] */
43};
44
45struct ath5k_gain_opt {
46 u32 go_default;
47 u32 go_steps_count;
48 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
49};
50
51/* RF5111 mode-specific init registers */
52static const struct ath5k_ini_rf rfregs_5111[] = {
53 { 0, 0x989c,
54 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
55 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
56 { 0, 0x989c,
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
58 { 0, 0x989c,
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
60 { 0, 0x989c,
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
62 { 0, 0x989c,
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
64 { 0, 0x989c,
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
66 { 0, 0x989c,
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
68 { 0, 0x989c,
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
70 { 0, 0x989c,
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
72 { 0, 0x989c,
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
74 { 0, 0x989c,
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
76 { 0, 0x989c,
77 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
78 { 0, 0x989c,
79 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
80 { 0, 0x989c,
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
82 { 0, 0x989c,
83 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
84 { 0, 0x989c,
85 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
86 { 0, 0x98d4,
87 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
88 { 1, 0x98d4,
89 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
90 { 2, 0x98d4,
91 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
92 { 3, 0x98d8,
93 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
94 { 6, 0x989c,
95 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
96 { 6, 0x989c,
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
98 { 6, 0x989c,
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
100 { 6, 0x989c,
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
102 { 6, 0x989c,
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
104 { 6, 0x989c,
105 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
106 { 6, 0x989c,
107 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
108 { 6, 0x989c,
109 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
110 { 6, 0x989c,
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
112 { 6, 0x989c,
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
114 { 6, 0x989c,
115 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
116 { 6, 0x989c,
117 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
118 { 6, 0x989c,
119 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
120 { 6, 0x989c,
121 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
122 { 6, 0x989c,
123 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
124 { 6, 0x989c,
125 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
126 { 6, 0x98d4,
127 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
128 { 7, 0x989c,
129 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
130 { 7, 0x989c,
131 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
132 { 7, 0x989c,
133 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
134 { 7, 0x989c,
135 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
136 { 7, 0x989c,
137 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
138 { 7, 0x989c,
139 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
140 { 7, 0x989c,
141 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
142 { 7, 0x98cc,
143 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
144};
145
146/* Initial RF Gain settings for RF5111 */
147static const struct ath5k_ini_rfgain rfgain_5111[] = {
148 /* 5Ghz 2Ghz */
149 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
150 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
151 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
152 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
153 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
154 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
155 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
156 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
157 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
158 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
159 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
160 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
161 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
162 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
163 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
164 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
165 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
166 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
167 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
168 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
169 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
170 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
171 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
172 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
173 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
174 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
175 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
176 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
177 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
178 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
179 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
180 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
181 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
182 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
183 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
184 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
185 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
186 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
187 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
188 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
189 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
190 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
191 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
192 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
193 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
194 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
195 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
196 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
197 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
198 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
199 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
200 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
201 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
213};
214
215static const struct ath5k_gain_opt rfgain_opt_5111 = {
216 4,
217 9,
218 {
219 { { 4, 1, 1, 1 }, 6 },
220 { { 4, 0, 1, 1 }, 4 },
221 { { 3, 1, 1, 1 }, 3 },
222 { { 4, 0, 0, 1 }, 1 },
223 { { 4, 1, 1, 0 }, 0 },
224 { { 4, 0, 1, 0 }, -2 },
225 { { 3, 1, 1, 0 }, -3 },
226 { { 4, 0, 0, 0 }, -4 },
227 { { 2, 1, 1, 0 }, -6 }
228 }
229};
230
231/* RF5112 mode-specific init registers */
232static const struct ath5k_ini_rf rfregs_5112[] = {
233 { 1, 0x98d4,
234 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
235 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
236 { 2, 0x98d0,
237 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
238 { 3, 0x98dc,
239 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
240 { 6, 0x989c,
241 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
242 { 6, 0x989c,
243 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
244 { 6, 0x989c,
245 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
246 { 6, 0x989c,
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
248 { 6, 0x989c,
249 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
250 { 6, 0x989c,
251 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
252 { 6, 0x989c,
253 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
254 { 6, 0x989c,
255 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
256 { 6, 0x989c,
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
258 { 6, 0x989c,
259 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
260 { 6, 0x989c,
261 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
262 { 6, 0x989c,
263 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
264 { 6, 0x989c,
265 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
266 { 6, 0x989c,
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
268 { 6, 0x989c,
269 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
270 { 6, 0x989c,
271 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
272 { 6, 0x989c,
273 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
274 { 6, 0x989c,
275 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
276 { 6, 0x989c,
277 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
278 { 6, 0x989c,
279 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
280 { 6, 0x989c,
281 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
282 { 6, 0x989c,
283 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
284 { 6, 0x989c,
285 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
286 { 6, 0x989c,
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
288 { 6, 0x989c,
289 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
290 { 6, 0x989c,
291 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
292 { 6, 0x989c,
293 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
294 { 6, 0x989c,
295 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
296 { 6, 0x989c,
297 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
298 { 6, 0x989c,
299 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
300 { 6, 0x989c,
301 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
302 { 6, 0x989c,
303 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
304 { 6, 0x989c,
305 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
306 { 6, 0x989c,
307 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
308 { 6, 0x989c,
309 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
310 { 6, 0x989c,
311 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
312 { 6, 0x989c,
313 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
314 { 6, 0x98d0,
315 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
316 { 7, 0x989c,
317 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
318 { 7, 0x989c,
319 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
320 { 7, 0x989c,
321 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
322 { 7, 0x989c,
323 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
324 { 7, 0x989c,
325 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
326 { 7, 0x989c,
327 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
328 { 7, 0x989c,
329 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
330 { 7, 0x989c,
331 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
332 { 7, 0x989c,
333 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
334 { 7, 0x989c,
335 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
336 { 7, 0x989c,
337 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
338 { 7, 0x989c,
339 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
340 { 7, 0x98c4,
341 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
342};
343
344/* RF5112A mode-specific init registers */
345static const struct ath5k_ini_rf rfregs_5112a[] = {
346 { 1, 0x98d4,
347 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
348 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
349 { 2, 0x98d0,
350 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
351 { 3, 0x98dc,
352 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
353 { 6, 0x989c,
354 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
355 { 6, 0x989c,
356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
357 { 6, 0x989c,
358 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
359 { 6, 0x989c,
360 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
361 { 6, 0x989c,
362 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
363 { 6, 0x989c,
364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
365 { 6, 0x989c,
366 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
367 { 6, 0x989c,
368 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
369 { 6, 0x989c,
370 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
371 { 6, 0x989c,
372 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
373 { 6, 0x989c,
374 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
375 { 6, 0x989c,
376 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
377 { 6, 0x989c,
378 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
379 { 6, 0x989c,
380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
381 { 6, 0x989c,
382 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
383 { 6, 0x989c,
384 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
385 { 6, 0x989c,
386 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
387 { 6, 0x989c,
388 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
389 { 6, 0x989c,
390 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
391 { 6, 0x989c,
392 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
393 { 6, 0x989c,
394 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
395 { 6, 0x989c,
396 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
397 { 6, 0x989c,
398 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
399 { 6, 0x989c,
400 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
401 { 6, 0x989c,
402 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
403 { 6, 0x989c,
404 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
405 { 6, 0x989c,
406 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
407 { 6, 0x989c,
408 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
409 { 6, 0x989c,
410 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
411 { 6, 0x989c,
412 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
413 { 6, 0x989c,
414 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
415 { 6, 0x989c,
416 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
417 { 6, 0x989c,
418 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
419 { 6, 0x989c,
420 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
421 { 6, 0x989c,
422 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
423 { 6, 0x989c,
424 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
425 { 6, 0x989c,
426 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
427 { 6, 0x989c,
428 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
429 { 6, 0x989c,
430 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
431 { 6, 0x98d8,
432 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
433 { 7, 0x989c,
434 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
435 { 7, 0x989c,
436 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
437 { 7, 0x989c,
438 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
439 { 7, 0x989c,
440 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
441 { 7, 0x989c,
442 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
443 { 7, 0x989c,
444 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
445 { 7, 0x989c,
446 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
447 { 7, 0x989c,
448 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
449 { 7, 0x989c,
450 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
451 { 7, 0x989c,
452 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
453 { 7, 0x989c,
454 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
455 { 7, 0x989c,
456 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
457 { 7, 0x98c4,
458 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
459};
460
461
462static const struct ath5k_ini_rf rfregs_2112a[] = {
463 { 1, AR5K_RF_BUFFER_CONTROL_4,
464 /* mode b mode g mode gTurbo */
465 { 0x00000020, 0x00000020, 0x00000020 } },
466 { 2, AR5K_RF_BUFFER_CONTROL_3,
467 { 0x03060408, 0x03060408, 0x03070408 } },
468 { 3, AR5K_RF_BUFFER_CONTROL_6,
469 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
470 { 6, AR5K_RF_BUFFER,
471 { 0x0a000000, 0x0a000000, 0x0a000000 } },
472 { 6, AR5K_RF_BUFFER,
473 { 0x00000000, 0x00000000, 0x00000000 } },
474 { 6, AR5K_RF_BUFFER,
475 { 0x00800000, 0x00800000, 0x00800000 } },
476 { 6, AR5K_RF_BUFFER,
477 { 0x002a0000, 0x002a0000, 0x002a0000 } },
478 { 6, AR5K_RF_BUFFER,
479 { 0x00010000, 0x00010000, 0x00010000 } },
480 { 6, AR5K_RF_BUFFER,
481 { 0x00000000, 0x00000000, 0x00000000 } },
482 { 6, AR5K_RF_BUFFER,
483 { 0x00180000, 0x00180000, 0x00180000 } },
484 { 6, AR5K_RF_BUFFER,
485 { 0x006e0000, 0x006e0000, 0x006e0000 } },
486 { 6, AR5K_RF_BUFFER,
487 { 0x00c70000, 0x00c70000, 0x00c70000 } },
488 { 6, AR5K_RF_BUFFER,
489 { 0x004b0000, 0x004b0000, 0x004b0000 } },
490 { 6, AR5K_RF_BUFFER,
491 { 0x04480000, 0x04480000, 0x04480000 } },
492 { 6, AR5K_RF_BUFFER,
493 { 0x002a0000, 0x002a0000, 0x002a0000 } },
494 { 6, AR5K_RF_BUFFER,
495 { 0x00e40000, 0x00e40000, 0x00e40000 } },
496 { 6, AR5K_RF_BUFFER,
497 { 0x00000000, 0x00000000, 0x00000000 } },
498 { 6, AR5K_RF_BUFFER,
499 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
500 { 6, AR5K_RF_BUFFER,
501 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
502 { 6, AR5K_RF_BUFFER,
503 { 0x043f0000, 0x043f0000, 0x043f0000 } },
504 { 6, AR5K_RF_BUFFER,
505 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
506 { 6, AR5K_RF_BUFFER,
507 { 0x02190000, 0x02190000, 0x02190000 } },
508 { 6, AR5K_RF_BUFFER,
509 { 0x00240000, 0x00240000, 0x00240000 } },
510 { 6, AR5K_RF_BUFFER,
511 { 0x00b40000, 0x00b40000, 0x00b40000 } },
512 { 6, AR5K_RF_BUFFER,
513 { 0x00990000, 0x00990000, 0x00990000 } },
514 { 6, AR5K_RF_BUFFER,
515 { 0x00500000, 0x00500000, 0x00500000 } },
516 { 6, AR5K_RF_BUFFER,
517 { 0x002a0000, 0x002a0000, 0x002a0000 } },
518 { 6, AR5K_RF_BUFFER,
519 { 0x00120000, 0x00120000, 0x00120000 } },
520 { 6, AR5K_RF_BUFFER,
521 { 0xc0320000, 0xc0320000, 0xc0320000 } },
522 { 6, AR5K_RF_BUFFER,
523 { 0x01740000, 0x01740000, 0x01740000 } },
524 { 6, AR5K_RF_BUFFER,
525 { 0x00110000, 0x00110000, 0x00110000 } },
526 { 6, AR5K_RF_BUFFER,
527 { 0x86280000, 0x86280000, 0x86280000 } },
528 { 6, AR5K_RF_BUFFER,
529 { 0x31840000, 0x31840000, 0x31840000 } },
530 { 6, AR5K_RF_BUFFER,
531 { 0x00f20080, 0x00f20080, 0x00f20080 } },
532 { 6, AR5K_RF_BUFFER,
533 { 0x00070019, 0x00070019, 0x00070019 } },
534 { 6, AR5K_RF_BUFFER,
535 { 0x00000000, 0x00000000, 0x00000000 } },
536 { 6, AR5K_RF_BUFFER,
537 { 0x00000000, 0x00000000, 0x00000000 } },
538 { 6, AR5K_RF_BUFFER,
539 { 0x000000b2, 0x000000b2, 0x000000b2 } },
540 { 6, AR5K_RF_BUFFER,
541 { 0x00b02184, 0x00b02184, 0x00b02184 } },
542 { 6, AR5K_RF_BUFFER,
543 { 0x004125a4, 0x004125a4, 0x004125a4 } },
544 { 6, AR5K_RF_BUFFER,
545 { 0x00119220, 0x00119220, 0x00119220 } },
546 { 6, AR5K_RF_BUFFER,
547 { 0x001a4800, 0x001a4800, 0x001a4800 } },
548 { 6, AR5K_RF_BUFFER_CONTROL_5,
549 { 0x000b0230, 0x000b0230, 0x000b0230 } },
550 { 7, AR5K_RF_BUFFER,
551 { 0x00000094, 0x00000094, 0x00000094 } },
552 { 7, AR5K_RF_BUFFER,
553 { 0x00000091, 0x00000091, 0x00000091 } },
554 { 7, AR5K_RF_BUFFER,
555 { 0x00000012, 0x00000012, 0x00000012 } },
556 { 7, AR5K_RF_BUFFER,
557 { 0x00000080, 0x00000080, 0x00000080 } },
558 { 7, AR5K_RF_BUFFER,
559 { 0x000000d9, 0x000000d9, 0x000000d9 } },
560 { 7, AR5K_RF_BUFFER,
561 { 0x00000060, 0x00000060, 0x00000060 } },
562 { 7, AR5K_RF_BUFFER,
563 { 0x000000f0, 0x000000f0, 0x000000f0 } },
564 { 7, AR5K_RF_BUFFER,
565 { 0x000000a2, 0x000000a2, 0x000000a2 } },
566 { 7, AR5K_RF_BUFFER,
567 { 0x00000052, 0x00000052, 0x00000052 } },
568 { 7, AR5K_RF_BUFFER,
569 { 0x000000d4, 0x000000d4, 0x000000d4 } },
570 { 7, AR5K_RF_BUFFER,
571 { 0x000014cc, 0x000014cc, 0x000014cc } },
572 { 7, AR5K_RF_BUFFER,
573 { 0x0000048c, 0x0000048c, 0x0000048c } },
574 { 7, AR5K_RF_BUFFER_CONTROL_1,
575 { 0x00000003, 0x00000003, 0x00000003 } },
576};
577
578/* RF5413/5414 mode-specific init registers */
579static const struct ath5k_ini_rf rfregs_5413[] = {
580 { 1, 0x98d4,
581 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
582 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
583 { 2, 0x98d0,
584 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
585 { 3, 0x98dc,
586 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
587 { 6, 0x989c,
588 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
589 { 6, 0x989c,
590 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
591 { 6, 0x989c,
592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
593 { 6, 0x989c,
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
595 { 6, 0x989c,
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
597 { 6, 0x989c,
598 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
599 { 6, 0x989c,
600 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
601 { 6, 0x989c,
602 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
603 { 6, 0x989c,
604 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
605 { 6, 0x989c,
606 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
607 { 6, 0x989c,
608 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
609 { 6, 0x989c,
610 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
611 { 6, 0x989c,
612 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
613 { 6, 0x989c,
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
615 { 6, 0x989c,
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
617 { 6, 0x989c,
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
619 { 6, 0x989c,
620 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
621 { 6, 0x989c,
622 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
623 { 6, 0x989c,
624 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
625 { 6, 0x989c,
626 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
627 { 6, 0x989c,
628 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
629 { 6, 0x989c,
630 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
631 { 6, 0x989c,
632 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
633 { 6, 0x989c,
634 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
635 { 6, 0x989c,
636 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
637 { 6, 0x989c,
638 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
639 { 6, 0x989c,
640 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
641 { 6, 0x989c,
642 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
643 { 6, 0x989c,
644 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
645 { 6, 0x989c,
646 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
647 { 6, 0x989c,
648 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
649 { 6, 0x989c,
650 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
651 { 6, 0x989c,
652 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
653 { 6, 0x989c,
654 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
655 { 6, 0x989c,
656 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
657 { 6, 0x989c,
658 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
659 { 6, 0x98c8,
660 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
661 { 7, 0x989c,
662 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
663 { 7, 0x989c,
664 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
665 { 7, 0x98cc,
666 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
667};
668
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]669/* RF2413/2414 mode-specific init registers */
670static const struct ath5k_ini_rf rfregs_2413[] = {
671 { 1, AR5K_RF_BUFFER_CONTROL_4,
672 { 0x00000020, 0x00000020, 0x00000020 } },
673 { 2, AR5K_RF_BUFFER_CONTROL_3,
674 { 0x02001408, 0x02001408, 0x02001408 } },
675 { 3, AR5K_RF_BUFFER_CONTROL_6,
676 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
677 { 6, AR5K_RF_BUFFER,
678 { 0xf0000000, 0xf0000000, 0xf0000000 } },
679 { 6, AR5K_RF_BUFFER,
680 { 0x00000000, 0x00000000, 0x00000000 } },
681 { 6, AR5K_RF_BUFFER,
682 { 0x03000000, 0x03000000, 0x03000000 } },
683 { 6, AR5K_RF_BUFFER,
684 { 0x00000000, 0x00000000, 0x00000000 } },
685 { 6, AR5K_RF_BUFFER,
686 { 0x00000000, 0x00000000, 0x00000000 } },
687 { 6, AR5K_RF_BUFFER,
688 { 0x00000000, 0x00000000, 0x00000000 } },
689 { 6, AR5K_RF_BUFFER,
690 { 0x00000000, 0x00000000, 0x00000000 } },
691 { 6, AR5K_RF_BUFFER,
692 { 0x00000000, 0x00000000, 0x00000000 } },
693 { 6, AR5K_RF_BUFFER,
694 { 0x40400000, 0x40400000, 0x40400000 } },
695 { 6, AR5K_RF_BUFFER,
696 { 0x65050000, 0x65050000, 0x65050000 } },
697 { 6, AR5K_RF_BUFFER,
698 { 0x00000000, 0x00000000, 0x00000000 } },
699 { 6, AR5K_RF_BUFFER,
700 { 0x00000000, 0x00000000, 0x00000000 } },
701 { 6, AR5K_RF_BUFFER,
702 { 0x00420000, 0x00420000, 0x00420000 } },
703 { 6, AR5K_RF_BUFFER,
704 { 0x00b50000, 0x00b50000, 0x00b50000 } },
705 { 6, AR5K_RF_BUFFER,
706 { 0x00030000, 0x00030000, 0x00030000 } },
707 { 6, AR5K_RF_BUFFER,
708 { 0x00f70000, 0x00f70000, 0x00f70000 } },
709 { 6, AR5K_RF_BUFFER,
710 { 0x009d0000, 0x009d0000, 0x009d0000 } },
711 { 6, AR5K_RF_BUFFER,
712 { 0x00220000, 0x00220000, 0x00220000 } },
713 { 6, AR5K_RF_BUFFER,
714 { 0x04220000, 0x04220000, 0x04220000 } },
715 { 6, AR5K_RF_BUFFER,
716 { 0x00230018, 0x00230018, 0x00230018 } },
717 { 6, AR5K_RF_BUFFER,
718 { 0x00280050, 0x00280050, 0x00280050 } },
719 { 6, AR5K_RF_BUFFER,
720 { 0x005000c3, 0x005000c3, 0x005000c3 } },
721 { 6, AR5K_RF_BUFFER,
722 { 0x0004007f, 0x0004007f, 0x0004007f } },
723 { 6, AR5K_RF_BUFFER,
724 { 0x00000458, 0x00000458, 0x00000458 } },
725 { 6, AR5K_RF_BUFFER,
726 { 0x00000000, 0x00000000, 0x00000000 } },
727 { 6, AR5K_RF_BUFFER,
728 { 0x0000c000, 0x0000c000, 0x0000c000 } },
729 { 6, AR5K_RF_BUFFER_CONTROL_5,
730 { 0x00400230, 0x00400230, 0x00400230 } },
731 { 7, AR5K_RF_BUFFER,
732 { 0x00006400, 0x00006400, 0x00006400 } },
733 { 7, AR5K_RF_BUFFER,
734 { 0x00000800, 0x00000800, 0x00000800 } },
735 { 7, AR5K_RF_BUFFER_CONTROL_2,
736 { 0x0000000e, 0x0000000e, 0x0000000e } },
737};
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]738
739/* Initial RF Gain settings for RF5112 */
740static const struct ath5k_ini_rfgain rfgain_5112[] = {
741 /* 5Ghz 2Ghz */
742 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
743 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
744 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
745 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
746 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
747 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
748 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
749 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
750 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
751 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
752 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
753 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
754 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
755 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
756 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
757 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
758 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
759 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
760 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
761 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
762 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
763 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
764 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
765 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
766 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
767 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
768 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
769 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
770 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
771 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
772 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
773 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
774 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
775 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
776 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
777 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
778 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
779 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
780 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
781 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
782 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
783 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
784 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
785 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
786 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
787 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
788 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
789 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
790 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
791 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
792 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
793 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
794 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
795 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
796 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
797 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
798 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
799 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
800 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
801 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
802 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
803 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
804 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
805 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
806};
807
808/* Initial RF Gain settings for RF5413 */
809static const struct ath5k_ini_rfgain rfgain_5413[] = {
810 /* 5Ghz 2Ghz */
811 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
812 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
813 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
814 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
815 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
816 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
817 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
818 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
819 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
820 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
821 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
822 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
823 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
824 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
825 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
826 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
827 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
828 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
829 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
830 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
831 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
832 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
833 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
834 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
835 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
836 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
837 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
838 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
839 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
840 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
841 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
842 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
843 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
844 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
845 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
846 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
847 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
848 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
849 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
850 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
851 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
852 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
853 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
854 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
855 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
856 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
857 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
858 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
859 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
860 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
861 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
862 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
863 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
864 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
865 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
866 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
867 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
868 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
869 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
870 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
871 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
872 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
873 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
874 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
875};
876
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]877/* Initial RF Gain settings for RF2413 */
878static const struct ath5k_ini_rfgain rfgain_2413[] = {
879 { AR5K_RF_GAIN(0), { 0x00000000 } },
880 { AR5K_RF_GAIN(1), { 0x00000040 } },
881 { AR5K_RF_GAIN(2), { 0x00000080 } },
882 { AR5K_RF_GAIN(3), { 0x00000181 } },
883 { AR5K_RF_GAIN(4), { 0x000001c1 } },
884 { AR5K_RF_GAIN(5), { 0x00000001 } },
885 { AR5K_RF_GAIN(6), { 0x00000041 } },
886 { AR5K_RF_GAIN(7), { 0x00000081 } },
887 { AR5K_RF_GAIN(8), { 0x00000168 } },
888 { AR5K_RF_GAIN(9), { 0x000001a8 } },
889 { AR5K_RF_GAIN(10), { 0x000001e8 } },
890 { AR5K_RF_GAIN(11), { 0x00000028 } },
891 { AR5K_RF_GAIN(12), { 0x00000068 } },
892 { AR5K_RF_GAIN(13), { 0x00000189 } },
893 { AR5K_RF_GAIN(14), { 0x000001c9 } },
894 { AR5K_RF_GAIN(15), { 0x00000009 } },
895 { AR5K_RF_GAIN(16), { 0x00000049 } },
896 { AR5K_RF_GAIN(17), { 0x00000089 } },
897 { AR5K_RF_GAIN(18), { 0x00000190 } },
898 { AR5K_RF_GAIN(19), { 0x000001d0 } },
899 { AR5K_RF_GAIN(20), { 0x00000010 } },
900 { AR5K_RF_GAIN(21), { 0x00000050 } },
901 { AR5K_RF_GAIN(22), { 0x00000090 } },
902 { AR5K_RF_GAIN(23), { 0x00000191 } },
903 { AR5K_RF_GAIN(24), { 0x000001d1 } },
904 { AR5K_RF_GAIN(25), { 0x00000011 } },
905 { AR5K_RF_GAIN(26), { 0x00000051 } },
906 { AR5K_RF_GAIN(27), { 0x00000091 } },
907 { AR5K_RF_GAIN(28), { 0x00000178 } },
908 { AR5K_RF_GAIN(29), { 0x000001b8 } },
909 { AR5K_RF_GAIN(30), { 0x000001f8 } },
910 { AR5K_RF_GAIN(31), { 0x00000038 } },
911 { AR5K_RF_GAIN(32), { 0x00000078 } },
912 { AR5K_RF_GAIN(33), { 0x00000199 } },
913 { AR5K_RF_GAIN(34), { 0x000001d9 } },
914 { AR5K_RF_GAIN(35), { 0x00000019 } },
915 { AR5K_RF_GAIN(36), { 0x00000059 } },
916 { AR5K_RF_GAIN(37), { 0x00000099 } },
917 { AR5K_RF_GAIN(38), { 0x000000d9 } },
918 { AR5K_RF_GAIN(39), { 0x000000f9 } },
919 { AR5K_RF_GAIN(40), { 0x000000f9 } },
920 { AR5K_RF_GAIN(41), { 0x000000f9 } },
921 { AR5K_RF_GAIN(42), { 0x000000f9 } },
922 { AR5K_RF_GAIN(43), { 0x000000f9 } },
923 { AR5K_RF_GAIN(44), { 0x000000f9 } },
924 { AR5K_RF_GAIN(45), { 0x000000f9 } },
925 { AR5K_RF_GAIN(46), { 0x000000f9 } },
926 { AR5K_RF_GAIN(47), { 0x000000f9 } },
927 { AR5K_RF_GAIN(48), { 0x000000f9 } },
928 { AR5K_RF_GAIN(49), { 0x000000f9 } },
929 { AR5K_RF_GAIN(50), { 0x000000f9 } },
930 { AR5K_RF_GAIN(51), { 0x000000f9 } },
931 { AR5K_RF_GAIN(52), { 0x000000f9 } },
932 { AR5K_RF_GAIN(53), { 0x000000f9 } },
933 { AR5K_RF_GAIN(54), { 0x000000f9 } },
934 { AR5K_RF_GAIN(55), { 0x000000f9 } },
935 { AR5K_RF_GAIN(56), { 0x000000f9 } },
936 { AR5K_RF_GAIN(57), { 0x000000f9 } },
937 { AR5K_RF_GAIN(58), { 0x000000f9 } },
938 { AR5K_RF_GAIN(59), { 0x000000f9 } },
939 { AR5K_RF_GAIN(60), { 0x000000f9 } },
940 { AR5K_RF_GAIN(61), { 0x000000f9 } },
941 { AR5K_RF_GAIN(62), { 0x000000f9 } },
942 { AR5K_RF_GAIN(63), { 0x000000f9 } },
943};
944
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]945static const struct ath5k_gain_opt rfgain_opt_5112 = {
946 1,
947 8,
948 {
949 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
950 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
951 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
952 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
953 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
954 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
955 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
956 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
957 }
958};
959
960/*
961 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
962 */
963static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
964 u32 first, u32 col, bool set)
965{
966 u32 mask, entry, last, data, shift, position;
967 s32 left;
968 int i;
969
970 data = 0;
971
972 if (rf == NULL)
973 /* should not happen */
974 return 0;
975
976 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
977 ATH5K_PRINTF("invalid values at offset %u\n", offset);
978 return 0;
979 }
980
981 entry = ((first - 1) / 8) + offset;
982 position = (first - 1) % 8;
983
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame^]984 if (set)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]985 data = ath5k_hw_bitswap(reg, bits);
986
987 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
988 last = (position + left > 8) ? 8 : position + left;
989 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
990
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame^]991 if (set) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]992 rf[entry] &= ~mask;
993 rf[entry] |= ((data << position) << (col * 8)) & mask;
994 data >>= (8 - position);
995 } else {
996 data = (((rf[entry] & mask) >> (col * 8)) >> position)
997 << shift;
998 shift += last - position;
999 }
1000
1001 left -= 8 - position;
1002 }
1003
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame^]1004 data = set ? 1 : ath5k_hw_bitswap(data, bits);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1005
1006 return data;
1007}
1008
1009static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1010{
1011 u32 mix, step;
1012 u32 *rf;
1013
1014 if (ah->ah_rf_banks == NULL)
1015 return 0;
1016
1017 rf = ah->ah_rf_banks;
1018 ah->ah_gain.g_f_corr = 0;
1019
1020 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1021 return 0;
1022
1023 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1024 mix = ah->ah_gain.g_step->gos_param[0];
1025
1026 switch (mix) {
1027 case 3:
1028 ah->ah_gain.g_f_corr = step * 2;
1029 break;
1030 case 2:
1031 ah->ah_gain.g_f_corr = (step - 5) * 2;
1032 break;
1033 case 1:
1034 ah->ah_gain.g_f_corr = step;
1035 break;
1036 default:
1037 ah->ah_gain.g_f_corr = 0;
1038 break;
1039 }
1040
1041 return ah->ah_gain.g_f_corr;
1042}
1043
1044static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1045{
1046 u32 step, mix, level[4];
1047 u32 *rf;
1048
1049 if (ah->ah_rf_banks == NULL)
1050 return false;
1051
1052 rf = ah->ah_rf_banks;
1053
1054 if (ah->ah_radio == AR5K_RF5111) {
1055 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1056 false);
1057 level[0] = 0;
1058 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1059 level[2] = (step != 0x3f) ? 0x40 : level[0];
1060 level[3] = level[2] + 0x32;
1061
1062 ah->ah_gain.g_high = level[3] -
1063 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1064 ah->ah_gain.g_low = level[0] +
1065 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1066 } else {
1067 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1068 false);
1069 level[0] = level[2] = 0;
1070
1071 if (mix == 1) {
1072 level[1] = level[3] = 83;
1073 } else {
1074 level[1] = level[3] = 107;
1075 ah->ah_gain.g_high = 55;
1076 }
1077 }
1078
1079 return (ah->ah_gain.g_current >= level[0] &&
1080 ah->ah_gain.g_current <= level[1]) ||
1081 (ah->ah_gain.g_current >= level[2] &&
1082 ah->ah_gain.g_current <= level[3]);
1083}
1084
1085static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1086{
1087 const struct ath5k_gain_opt *go;
1088 int ret = 0;
1089
1090 switch (ah->ah_radio) {
1091 case AR5K_RF5111:
1092 go = &rfgain_opt_5111;
1093 break;
1094 case AR5K_RF5112:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1095 go = &rfgain_opt_5112;
1096 break;
1097 default:
1098 return 0;
1099 }
1100
1101 ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1102
1103 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1104 if (ah->ah_gain.g_step_idx == 0)
1105 return -1;
1106 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1107 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
1108 ah->ah_gain.g_step_idx > 0;
1109 ah->ah_gain.g_step =
1110 &go->go_step[ah->ah_gain.g_step_idx])
1111 ah->ah_gain.g_target -= 2 *
1112 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1113 ah->ah_gain.g_step->gos_gain);
1114
1115 ret = 1;
1116 goto done;
1117 }
1118
1119 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1120 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1121 return -2;
1122 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1123 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1124 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1125 ah->ah_gain.g_step =
1126 &go->go_step[ah->ah_gain.g_step_idx])
1127 ah->ah_gain.g_target -= 2 *
1128 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1129 ah->ah_gain.g_step->gos_gain);
1130
1131 ret = 2;
1132 goto done;
1133 }
1134
1135done:
1136 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1137 "ret %d, gain step %u, current gain %u, target gain %u\n",
1138 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1139 ah->ah_gain.g_target);
1140
1141 return ret;
1142}
1143
1144/*
1145 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1146 */
1147static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1148 struct ieee80211_channel *channel, unsigned int mode)
1149{
1150 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1151 u32 *rf;
1152 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1153 unsigned int i;
1154 int obdb = -1, bank = -1;
1155 u32 ee_mode;
1156
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1157 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1158
1159 rf = ah->ah_rf_banks;
1160
1161 /* Copy values to modify them */
1162 for (i = 0; i < rf_size; i++) {
1163 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1164 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1165 return -EINVAL;
1166 }
1167
1168 if (bank != rfregs_5111[i].rf_bank) {
1169 bank = rfregs_5111[i].rf_bank;
1170 ah->ah_offset[bank] = i;
1171 }
1172
1173 rf[i] = rfregs_5111[i].rf_value[mode];
1174 }
1175
1176 /* Modify bank 0 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1177 if (channel->hw_value & CHANNEL_2GHZ) {
1178 if (channel->hw_value & CHANNEL_CCK)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1179 ee_mode = AR5K_EEPROM_MODE_11B;
1180 else
1181 ee_mode = AR5K_EEPROM_MODE_11G;
1182 obdb = 0;
1183
1184 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1185 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1186 return -EINVAL;
1187
1188 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1189 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1190 return -EINVAL;
1191
1192 obdb = 1;
1193 /* Modify bank 6 */
1194 } else {
1195 /* For 11a, Turbo and XR */
1196 ee_mode = AR5K_EEPROM_MODE_11A;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1197 obdb = channel->center_freq >= 5725 ? 3 :
1198 (channel->center_freq >= 5500 ? 2 :
1199 (channel->center_freq >= 5260 ? 1 :
1200 (channel->center_freq > 4000 ? 0 : -1)));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1201
1202 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1203 ee->ee_pwd_84, 1, 51, 3, true))
1204 return -EINVAL;
1205
1206 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1207 ee->ee_pwd_90, 1, 45, 3, true))
1208 return -EINVAL;
1209 }
1210
1211 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1212 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1213 return -EINVAL;
1214
1215 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1216 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1217 return -EINVAL;
1218
1219 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1220 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1221 return -EINVAL;
1222
1223 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1224 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1225 return -EINVAL;
1226
1227 /* Modify bank 7 */
1228 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1229 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1230 return -EINVAL;
1231
1232 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1233 ee->ee_xpd[ee_mode], 1, 4, 0, true))
1234 return -EINVAL;
1235
1236 /* Write RF values */
1237 for (i = 0; i < rf_size; i++) {
1238 AR5K_REG_WAIT(i);
1239 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1240 }
1241
1242 return 0;
1243}
1244
1245/*
1246 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1247 */
1248static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1249 struct ieee80211_channel *channel, unsigned int mode)
1250{
1251 const struct ath5k_ini_rf *rf_ini;
1252 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1253 u32 *rf;
1254 unsigned int rf_size, i;
1255 int obdb = -1, bank = -1;
1256 u32 ee_mode;
1257
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1258 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1259
1260 rf = ah->ah_rf_banks;
1261
1262 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1263 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1264 rf_ini = rfregs_2112a;
1265 rf_size = ARRAY_SIZE(rfregs_5112a);
1266 if (mode < 2) {
1267 ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1268 return -EINVAL;
1269 }
1270 mode = mode - 2; /*no a/turboa modes for 2112*/
1271 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1272 rf_ini = rfregs_5112a;
1273 rf_size = ARRAY_SIZE(rfregs_5112a);
1274 } else {
1275 rf_ini = rfregs_5112;
1276 rf_size = ARRAY_SIZE(rfregs_5112);
1277 }
1278
1279 /* Copy values to modify them */
1280 for (i = 0; i < rf_size; i++) {
1281 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1282 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1283 return -EINVAL;
1284 }
1285
1286 if (bank != rf_ini[i].rf_bank) {
1287 bank = rf_ini[i].rf_bank;
1288 ah->ah_offset[bank] = i;
1289 }
1290
1291 rf[i] = rf_ini[i].rf_value[mode];
1292 }
1293
1294 /* Modify bank 6 */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1295 if (channel->hw_value & CHANNEL_2GHZ) {
1296 if (channel->hw_value & CHANNEL_OFDM)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1297 ee_mode = AR5K_EEPROM_MODE_11G;
1298 else
1299 ee_mode = AR5K_EEPROM_MODE_11B;
1300 obdb = 0;
1301
1302 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1303 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1304 return -EINVAL;
1305
1306 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1307 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1308 return -EINVAL;
1309 } else {
1310 /* For 11a, Turbo and XR */
1311 ee_mode = AR5K_EEPROM_MODE_11A;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1312 obdb = channel->center_freq >= 5725 ? 3 :
1313 (channel->center_freq >= 5500 ? 2 :
1314 (channel->center_freq >= 5260 ? 1 :
1315 (channel->center_freq > 4000 ? 0 : -1)));
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1316
Luis R. Rodrigueze71c9fa2008-02-03 21:53:51 -0500[diff] [blame]1317 if (obdb == -1)
1318 return -EINVAL;
1319
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1320 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1321 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1322 return -EINVAL;
1323
1324 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1325 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1326 return -EINVAL;
1327 }
1328
1329 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1330 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1331 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1332 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1333
1334 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1335 ee->ee_xpd[ee_mode], 1, 302, 0, true))
1336 return -EINVAL;
1337
1338 /* Modify bank 7 */
1339 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1340 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1341 return -EINVAL;
1342
1343 /* Write RF values */
1344 for (i = 0; i < rf_size; i++)
1345 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1346
1347 return 0;
1348}
1349
1350/*
1351 * Initialize RF5413/5414
1352 */
1353static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1354 struct ieee80211_channel *channel, unsigned int mode)
1355{
1356 const struct ath5k_ini_rf *rf_ini;
1357 u32 *rf;
1358 unsigned int rf_size, i;
1359 int bank = -1;
1360
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1361 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1362
1363 rf = ah->ah_rf_banks;
1364
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1365 if (ah->ah_radio == AR5K_RF5413) {
1366 rf_ini = rfregs_5413;
1367 rf_size = ARRAY_SIZE(rfregs_5413);
1368 } else if (ah->ah_radio == AR5K_RF2413) {
1369 rf_ini = rfregs_2413;
1370 rf_size = ARRAY_SIZE(rfregs_2413);
1371 if (mode < 2) {
1372 ATH5K_ERR(ah->ah_sc,
1373 "invalid channel mode: %i\n", mode);
1374 return -EINVAL;
1375 }
1376 mode = mode - 2;
1377 } else {
1378 return -EINVAL;
1379 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1380
1381 /* Copy values to modify them */
1382 for (i = 0; i < rf_size; i++) {
1383 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1384 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1385 return -EINVAL;
1386 }
1387
1388 if (bank != rf_ini[i].rf_bank) {
1389 bank = rf_ini[i].rf_bank;
1390 ah->ah_offset[bank] = i;
1391 }
1392
1393 rf[i] = rf_ini[i].rf_value[mode];
1394 }
1395
1396 /*
1397 * After compairing dumps from different cards
1398 * we get the same RF_BUFFER settings (diff returns
1399 * 0 lines). It seems that RF_BUFFER settings are static
1400 * and are written unmodified (no EEPROM stuff
1401 * is used because calibration data would be
1402 * different between different cards and would result
1403 * different RF_BUFFER settings)
1404 */
1405
1406 /* Write RF values */
1407 for (i = 0; i < rf_size; i++)
1408 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1409
1410 return 0;
1411}
1412
1413/*
1414 * Initialize RF
1415 */
1416int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1417 unsigned int mode)
1418{
1419 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1420 int ret;
1421
1422 switch (ah->ah_radio) {
1423 case AR5K_RF5111:
1424 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1425 func = ath5k_hw_rf5111_rfregs;
1426 break;
1427 case AR5K_RF5112:
1428 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1429 ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1430 else
1431 ah->ah_rf_banks_size = sizeof(rfregs_5112);
1432 func = ath5k_hw_rf5112_rfregs;
1433 break;
1434 case AR5K_RF5413:
1435 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1436 func = ath5k_hw_rf5413_rfregs;
1437 break;
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1438 case AR5K_RF2413:
1439 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1440 func = ath5k_hw_rf5413_rfregs;
1441 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1442 default:
1443 return -EINVAL;
1444 }
1445
1446 if (ah->ah_rf_banks == NULL) {
1447 /* XXX do extra checks? */
1448 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1449 if (ah->ah_rf_banks == NULL) {
1450 ATH5K_ERR(ah->ah_sc, "out of memory\n");
1451 return -ENOMEM;
1452 }
1453 }
1454
1455 ret = func(ah, channel, mode);
1456 if (!ret)
1457 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1458
1459 return ret;
1460}
1461
1462int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1463{
1464 const struct ath5k_ini_rfgain *ath5k_rfg;
1465 unsigned int i, size;
1466
1467 switch (ah->ah_radio) {
1468 case AR5K_RF5111:
1469 ath5k_rfg = rfgain_5111;
1470 size = ARRAY_SIZE(rfgain_5111);
1471 break;
1472 case AR5K_RF5112:
1473 ath5k_rfg = rfgain_5112;
1474 size = ARRAY_SIZE(rfgain_5112);
1475 break;
1476 case AR5K_RF5413:
1477 ath5k_rfg = rfgain_5413;
1478 size = ARRAY_SIZE(rfgain_5413);
1479 break;
Nick Kossifidisf714dd62008-02-28 14:43:51 -0500[diff] [blame]1480 case AR5K_RF2413:
1481 ath5k_rfg = rfgain_2413;
1482 size = ARRAY_SIZE(rfgain_2413);
1483 freq = 0; /* only 2Ghz */
1484 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1485 default:
1486 return -EINVAL;
1487 }
1488
1489 switch (freq) {
1490 case AR5K_INI_RFGAIN_2GHZ:
1491 case AR5K_INI_RFGAIN_5GHZ:
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496
1497 for (i = 0; i < size; i++) {
1498 AR5K_REG_WAIT(i);
1499 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1500 (u32)ath5k_rfg[i].rfg_register);
1501 }
1502
1503 return 0;
1504}
1505
1506enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1507{
1508 u32 data, type;
1509
1510 ATH5K_TRACE(ah->ah_sc);
1511
1512 if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1513 ah->ah_version <= AR5K_AR5211)
1514 return AR5K_RFGAIN_INACTIVE;
1515
1516 if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1517 goto done;
1518
1519 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1520
1521 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1522 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1523 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1524
1525 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1526 ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1527
1528 if (ah->ah_radio >= AR5K_RF5112) {
1529 ath5k_hw_rfregs_gainf_corr(ah);
1530 ah->ah_gain.g_current =
1531 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1532 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1533 0;
1534 }
1535
1536 if (ath5k_hw_rfregs_gain_readback(ah) &&
1537 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1538 ath5k_hw_rfregs_gain_adjust(ah))
1539 ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1540 }
1541
1542done:
1543 return ah->ah_rf_gain;
1544}
1545
1546int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1547{
1548 /* Initialize the gain optimization values */
1549 switch (ah->ah_radio) {
1550 case AR5K_RF5111:
1551 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1552 ah->ah_gain.g_step =
1553 &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1554 ah->ah_gain.g_low = 20;
1555 ah->ah_gain.g_high = 35;
1556 ah->ah_gain.g_active = 1;
1557 break;
1558 case AR5K_RF5112:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1559 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1560 ah->ah_gain.g_step =
1561 &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1562 ah->ah_gain.g_low = 20;
1563 ah->ah_gain.g_high = 85;
1564 ah->ah_gain.g_active = 1;
1565 break;
1566 default:
1567 return -EINVAL;
1568 }
1569
1570 return 0;
1571}
1572
1573/**************************\
1574 PHY/RF channel functions
1575\**************************/
1576
1577/*
1578 * Check if a channel is supported
1579 */
1580bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1581{
1582 /* Check if the channel is in our supported range */
1583 if (flags & CHANNEL_2GHZ) {
1584 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1585 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1586 return true;
1587 } else if (flags & CHANNEL_5GHZ)
1588 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1589 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1590 return true;
1591
1592 return false;
1593}
1594
1595/*
1596 * Convertion needed for RF5110
1597 */
1598static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1599{
1600 u32 athchan;
1601
1602 /*
1603 * Convert IEEE channel/MHz to an internal channel value used
1604 * by the AR5210 chipset. This has not been verified with
1605 * newer chipsets like the AR5212A who have a completely
1606 * different RF/PHY part.
1607 */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1608 athchan = (ath5k_hw_bitswap(
1609 (ieee80211_frequency_to_channel(
1610 channel->center_freq) - 24) / 2, 5)
1611 << 1) | (1 << 6) | 0x1;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1612 return athchan;
1613}
1614
1615/*
1616 * Set channel on RF5110
1617 */
1618static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1619 struct ieee80211_channel *channel)
1620{
1621 u32 data;
1622
1623 /*
1624 * Set the channel and wait
1625 */
1626 data = ath5k_hw_rf5110_chan2athchan(channel);
1627 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1628 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1629 mdelay(1);
1630
1631 return 0;
1632}
1633
1634/*
1635 * Convertion needed for 5111
1636 */
1637static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1638 struct ath5k_athchan_2ghz *athchan)
1639{
1640 int channel;
1641
1642 /* Cast this value to catch negative channel numbers (>= -19) */
1643 channel = (int)ieee;
1644
1645 /*
1646 * Map 2GHz IEEE channel to 5GHz Atheros channel
1647 */
1648 if (channel <= 13) {
1649 athchan->a2_athchan = 115 + channel;
1650 athchan->a2_flags = 0x46;
1651 } else if (channel == 14) {
1652 athchan->a2_athchan = 124;
1653 athchan->a2_flags = 0x44;
1654 } else if (channel >= 15 && channel <= 26) {
1655 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1656 athchan->a2_flags = 0x46;
1657 } else
1658 return -EINVAL;
1659
1660 return 0;
1661}
1662
1663/*
1664 * Set channel on 5111
1665 */
1666static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1667 struct ieee80211_channel *channel)
1668{
1669 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1670 unsigned int ath5k_channel =
1671 ieee80211_frequency_to_channel(channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1672 u32 data0, data1, clock;
1673 int ret;
1674
1675 /*
1676 * Set the channel on the RF5111 radio
1677 */
1678 data0 = data1 = 0;
1679
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1680 if (channel->hw_value & CHANNEL_2GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1681 /* Map 2GHz channel to 5GHz Atheros channel ID */
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1682 ret = ath5k_hw_rf5111_chan2athchan(
1683 ieee80211_frequency_to_channel(channel->center_freq),
1684 &ath5k_channel_2ghz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1685 if (ret)
1686 return ret;
1687
1688 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1689 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1690 << 5) | (1 << 4);
1691 }
1692
1693 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1694 clock = 1;
1695 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1696 (clock << 1) | (1 << 10) | 1;
1697 } else {
1698 clock = 0;
1699 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1700 << 2) | (clock << 1) | (1 << 10) | 1;
1701 }
1702
1703 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1704 AR5K_RF_BUFFER);
1705 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1706 AR5K_RF_BUFFER_CONTROL_3);
1707
1708 return 0;
1709}
1710
1711/*
1712 * Set channel on 5112 and newer
1713 */
1714static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1715 struct ieee80211_channel *channel)
1716{
1717 u32 data, data0, data1, data2;
1718 u16 c;
1719
1720 data = data0 = data1 = data2 = 0;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1721 c = channel->center_freq;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1722
1723 /*
1724 * Set the channel on the RF5112 or newer
1725 */
1726 if (c < 4800) {
1727 if (!((c - 2224) % 5)) {
1728 data0 = ((2 * (c - 704)) - 3040) / 10;
1729 data1 = 1;
1730 } else if (!((c - 2192) % 5)) {
1731 data0 = ((2 * (c - 672)) - 3040) / 10;
1732 data1 = 0;
1733 } else
1734 return -EINVAL;
1735
1736 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1737 } else {
1738 if (!(c % 20) && c >= 5120) {
1739 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1740 data2 = ath5k_hw_bitswap(3, 2);
1741 } else if (!(c % 10)) {
1742 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1743 data2 = ath5k_hw_bitswap(2, 2);
1744 } else if (!(c % 5)) {
1745 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1746 data2 = ath5k_hw_bitswap(1, 2);
1747 } else
1748 return -EINVAL;
1749 }
1750
1751 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1752
1753 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1754 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1755
1756 return 0;
1757}
1758
1759/*
1760 * Set a channel on the radio chip
1761 */
1762int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1763{
1764 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1765 /*
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1766 * Check bounds supported by the PHY (we don't care about regultory
1767 * restrictions at this point). Note: hw_value already has the band
1768 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1769 * of the band by that */
1770 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1771 ATH5K_ERR(ah->ah_sc,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1772 "channel frequency (%u MHz) out of supported "
1773 "band range\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1774 channel->center_freq);
Luis R. Rodriguez400ec452008-02-03 21:51:49 -0500[diff] [blame]1775 return -EINVAL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1776 }
1777
1778 /*
1779 * Set the channel and wait
1780 */
1781 switch (ah->ah_radio) {
1782 case AR5K_RF5110:
1783 ret = ath5k_hw_rf5110_channel(ah, channel);
1784 break;
1785 case AR5K_RF5111:
1786 ret = ath5k_hw_rf5111_channel(ah, channel);
1787 break;
1788 default:
1789 ret = ath5k_hw_rf5112_channel(ah, channel);
1790 break;
1791 }
1792
1793 if (ret)
1794 return ret;
1795
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1796 ah->ah_current_channel.center_freq = channel->center_freq;
1797 ah->ah_current_channel.hw_value = channel->hw_value;
1798 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1799
1800 return 0;
1801}
1802
1803/*****************\
1804 PHY calibration
1805\*****************/
1806
1807/**
1808 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1809 *
1810 * @ah: struct ath5k_hw pointer we are operating on
1811 * @freq: the channel frequency, just used for error logging
1812 *
1813 * This function performs a noise floor calibration of the PHY and waits for
1814 * it to complete. Then the noise floor value is compared to some maximum
1815 * noise floor we consider valid.
1816 *
1817 * Note that this is different from what the madwifi HAL does: it reads the
1818 * noise floor and afterwards initiates the calibration. Since the noise floor
1819 * calibration can take some time to finish, depending on the current channel
1820 * use, that avoids the occasional timeout warnings we are seeing now.
1821 *
1822 * See the following link for an Atheros patent on noise floor calibration:
1823 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1824 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1825 *
1826 */
1827int
1828ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1829{
1830 int ret;
1831 unsigned int i;
1832 s32 noise_floor;
1833
1834 /*
1835 * Enable noise floor calibration and wait until completion
1836 */
1837 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1838 AR5K_PHY_AGCCTL_NF);
1839
1840 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1841 AR5K_PHY_AGCCTL_NF, 0, false);
1842 if (ret) {
1843 ATH5K_ERR(ah->ah_sc,
1844 "noise floor calibration timeout (%uMHz)\n", freq);
1845 return ret;
1846 }
1847
1848 /* Wait until the noise floor is calibrated and read the value */
1849 for (i = 20; i > 0; i--) {
1850 mdelay(1);
1851 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1852 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1853 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1854 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1855
1856 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1857 break;
1858 }
1859 }
1860
1861 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1862 "noise floor %d\n", noise_floor);
1863
1864 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1865 ATH5K_ERR(ah->ah_sc,
1866 "noise floor calibration failed (%uMHz)\n", freq);
1867 return -EIO;
1868 }
1869
1870 ah->ah_noise_floor = noise_floor;
1871
1872 return 0;
1873}
1874
1875/*
1876 * Perform a PHY calibration on RF5110
1877 * -Fix BPSK/QAM Constellation (I/Q correction)
1878 * -Calculate Noise Floor
1879 */
1880static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1881 struct ieee80211_channel *channel)
1882{
1883 u32 phy_sig, phy_agc, phy_sat, beacon;
1884 int ret;
1885
1886 /*
1887 * Disable beacons and RX/TX queues, wait
1888 */
1889 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1890 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1891 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1892 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1893
1894 udelay(2300);
1895
1896 /*
1897 * Set the channel (with AGC turned off)
1898 */
1899 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1900 udelay(10);
1901 ret = ath5k_hw_channel(ah, channel);
1902
1903 /*
1904 * Activate PHY and wait
1905 */
1906 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1907 mdelay(1);
1908
1909 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1910
1911 if (ret)
1912 return ret;
1913
1914 /*
1915 * Calibrate the radio chip
1916 */
1917
1918 /* Remember normal state */
1919 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1920 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1921 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1922
1923 /* Update radio registers */
1924 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1925 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1926
1927 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1928 AR5K_PHY_AGCCOARSE_LO)) |
1929 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1930 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1931
1932 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1933 AR5K_PHY_ADCSAT_THR)) |
1934 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1935 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1936
1937 udelay(20);
1938
1939 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1940 udelay(10);
1941 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1942 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1943
1944 mdelay(1);
1945
1946 /*
1947 * Enable calibration and wait until completion
1948 */
1949 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1950
1951 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1952 AR5K_PHY_AGCCTL_CAL, 0, false);
1953
1954 /* Reset to normal state */
1955 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1956 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1957 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1958
1959 if (ret) {
1960 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1961 channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1962 return ret;
1963 }
1964
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]1965 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1966 if (ret)
1967 return ret;
1968
1969 /*
1970 * Re-enable RX/TX and beacons
1971 */
1972 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1973 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1974 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1975
1976 return 0;
1977}
1978
1979/*
1980 * Perform a PHY calibration on RF5111/5112
1981 */
1982static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1983 struct ieee80211_channel *channel)
1984{
1985 u32 i_pwr, q_pwr;
1986 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1987 ATH5K_TRACE(ah->ah_sc);
1988
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame^]1989 if (!ah->ah_calibration ||
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]1990 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1991 goto done;
1992
1993 ah->ah_calibration = false;
1994
1995 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1996 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1997 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1998 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1999 q_coffd = q_pwr >> 6;
2000
2001 if (i_coffd == 0 || q_coffd == 0)
2002 goto done;
2003
2004 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
2005 q_coff = (((s32)i_pwr / q_coffd) - 64) & 0x1f;
2006
2007 /* Commit new IQ value */
2008 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2009 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2010
2011done:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]2012 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2013
2014 /* Request RF gain */
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500[diff] [blame]2015 if (channel->hw_value & CHANNEL_5GHZ) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2016 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2017 AR5K_PHY_PAPD_PROBE_TXPOWER) |
2018 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2019 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2020 }
2021
2022 return 0;
2023}
2024
2025/*
2026 * Perform a PHY calibration
2027 */
2028int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2029 struct ieee80211_channel *channel)
2030{
2031 int ret;
2032
2033 if (ah->ah_radio == AR5K_RF5110)
2034 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2035 else
2036 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2037
2038 return ret;
2039}
2040
2041int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2042{
2043 ATH5K_TRACE(ah->ah_sc);
2044 /*Just a try M.F.*/
2045 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2046
2047 return 0;
2048}
2049
2050/********************\
2051 Misc PHY functions
2052\********************/
2053
2054/*
2055 * Get the PHY Chip revision
2056 */
2057u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2058{
2059 unsigned int i;
2060 u32 srev;
2061 u16 ret;
2062
2063 ATH5K_TRACE(ah->ah_sc);
2064
2065 /*
2066 * Set the radio chip access register
2067 */
2068 switch (chan) {
2069 case CHANNEL_2GHZ:
2070 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2071 break;
2072 case CHANNEL_5GHZ:
2073 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2074 break;
2075 default:
2076 return 0;
2077 }
2078
2079 mdelay(2);
2080
2081 /* ...wait until PHY is ready and read the selected radio revision */
2082 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2083
2084 for (i = 0; i < 8; i++)
2085 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2086
2087 if (ah->ah_version == AR5K_AR5210) {
2088 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2089 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2090 } else {
2091 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2092 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2093 ((srev & 0x0f) << 4), 8);
2094 }
2095
2096 /* Reset to the 5GHz mode */
2097 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2098
2099 return ret;
2100}
2101
2102void /*TODO:Boundary check*/
2103ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2104{
2105 ATH5K_TRACE(ah->ah_sc);
2106 /*Just a try M.F.*/
2107 if (ah->ah_version != AR5K_AR5210)
2108 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2109}
2110
2111unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2112{
2113 ATH5K_TRACE(ah->ah_sc);
2114 /*Just a try M.F.*/
2115 if (ah->ah_version != AR5K_AR5210)
2116 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2117
2118 return false; /*XXX: What do we return for 5210 ?*/
2119}
2120
2121/*
2122 * TX power setup
2123 */
2124
2125/*
2126 * Initialize the tx power table (not fully implemented)
2127 */
2128static void ath5k_txpower_table(struct ath5k_hw *ah,
2129 struct ieee80211_channel *channel, s16 max_power)
2130{
2131 unsigned int i, min, max, n;
2132 u16 txpower, *rates;
2133
2134 rates = ah->ah_txpower.txp_rates;
2135
2136 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2137 if (max_power > txpower)
2138 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2139 AR5K_TUNE_MAX_TXPOWER : max_power;
2140
2141 for (i = 0; i < AR5K_MAX_RATES; i++)
2142 rates[i] = txpower;
2143
2144 /* XXX setup target powers by rate */
2145
2146 ah->ah_txpower.txp_min = rates[7];
2147 ah->ah_txpower.txp_max = rates[0];
2148 ah->ah_txpower.txp_ofdm = rates[0];
2149
2150 /* Calculate the power table */
2151 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2152 min = AR5K_EEPROM_PCDAC_START;
2153 max = AR5K_EEPROM_PCDAC_STOP;
2154 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2155 ah->ah_txpower.txp_pcdac[i] =
2156#ifdef notyet
2157 min + ((i * (max - min)) / n);
2158#else
2159 min;
2160#endif
2161}
2162
2163/*
2164 * Set transmition power
2165 */
2166int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2167ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2168 unsigned int txpower)
2169{
2170 bool tpc = ah->ah_txpower.txp_tpc;
2171 unsigned int i;
2172
2173 ATH5K_TRACE(ah->ah_sc);
2174 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2175 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2176 return -EINVAL;
2177 }
2178
Nick Kossifidis903b4742008-02-28 14:50:50 -0500[diff] [blame]2179 /*
2180 * RF2413 for some reason can't
2181 * transmit anything if we call
2182 * this funtion, so we skip it
2183 * until we fix txpower.
2184 */
2185 if (ah->ah_radio == AR5K_RF2413)
2186 return 0;
2187
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2188 /* Reset TX power values */
2189 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2190 ah->ah_txpower.txp_tpc = tpc;
2191
2192 /* Initialize TX power table */
2193 ath5k_txpower_table(ah, channel, txpower);
2194
2195 /*
2196 * Write TX power values
2197 */
2198 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2199 ath5k_hw_reg_write(ah,
2200 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2201 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
2202 AR5K_PHY_PCDAC_TXPOWER(i));
2203 }
2204
2205 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2206 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2207 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2208
2209 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2210 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2211 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2212
2213 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2214 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2215 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2216
2217 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2218 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2219 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2220
Joe Perchese9010e22008-03-07 14:21:16 -0800[diff] [blame^]2221 if (ah->ah_txpower.txp_tpc)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200[diff] [blame]2222 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2223 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2224 else
2225 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2226 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2227
2228 return 0;
2229}
2230
2231int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2232{
2233 /*Just a try M.F.*/
2234 struct ieee80211_channel *channel = &ah->ah_current_channel;
2235
2236 ATH5K_TRACE(ah->ah_sc);
2237 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2238 "changing txpower to %d\n", power);
2239
2240 return ath5k_hw_txpower(ah, channel, power);
2241}