Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009 Texas Instruments. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; either version 2 of the License, or |
| 7 | * (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | */ |
| 18 | |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/gpio.h> |
| 22 | #include <linux/module.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/clk.h> |
| 27 | #include <linux/dma-mapping.h> |
| 28 | #include <linux/spi/spi.h> |
| 29 | #include <linux/spi/spi_bitbang.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 30 | #include <linux/slab.h> |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 31 | |
| 32 | #include <mach/spi.h> |
| 33 | #include <mach/edma.h> |
| 34 | |
| 35 | #define SPI_NO_RESOURCE ((resource_size_t)-1) |
| 36 | |
| 37 | #define SPI_MAX_CHIPSELECT 2 |
| 38 | |
| 39 | #define CS_DEFAULT 0xFF |
| 40 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 41 | #define SPIFMT_PHASE_MASK BIT(16) |
| 42 | #define SPIFMT_POLARITY_MASK BIT(17) |
| 43 | #define SPIFMT_DISTIMER_MASK BIT(18) |
| 44 | #define SPIFMT_SHIFTDIR_MASK BIT(20) |
| 45 | #define SPIFMT_WAITENA_MASK BIT(21) |
| 46 | #define SPIFMT_PARITYENA_MASK BIT(22) |
| 47 | #define SPIFMT_ODD_PARITY_MASK BIT(23) |
| 48 | #define SPIFMT_WDELAY_MASK 0x3f000000u |
| 49 | #define SPIFMT_WDELAY_SHIFT 24 |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 50 | #define SPIFMT_PRESCALE_SHIFT 8 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 51 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 52 | |
| 53 | /* SPIPC0 */ |
| 54 | #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */ |
| 55 | #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */ |
| 56 | #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */ |
| 57 | #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 58 | |
| 59 | #define SPIINT_MASKALL 0x0101035F |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 60 | #define SPIINT_MASKINT 0x0000015F |
| 61 | #define SPI_INTLVL_1 0x000001FF |
| 62 | #define SPI_INTLVL_0 0x00000000 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 63 | |
Brian Niebuhr | cfbc5d1 | 2010-08-12 12:27:33 +0530 | [diff] [blame] | 64 | /* SPIDAT1 (upper 16 bit defines) */ |
| 65 | #define SPIDAT1_CSHOLD_MASK BIT(12) |
| 66 | |
| 67 | /* SPIGCR1 */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 68 | #define SPIGCR1_CLKMOD_MASK BIT(1) |
| 69 | #define SPIGCR1_MASTER_MASK BIT(0) |
| 70 | #define SPIGCR1_LOOPBACK_MASK BIT(16) |
Sekhar Nori | 8e206f1 | 2010-08-20 16:20:49 +0530 | [diff] [blame] | 71 | #define SPIGCR1_SPIENA_MASK BIT(24) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 72 | |
| 73 | /* SPIBUF */ |
| 74 | #define SPIBUF_TXFULL_MASK BIT(29) |
| 75 | #define SPIBUF_RXEMPTY_MASK BIT(31) |
| 76 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 77 | /* SPIDELAY */ |
| 78 | #define SPIDELAY_C2TDELAY_SHIFT 24 |
| 79 | #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT) |
| 80 | #define SPIDELAY_T2CDELAY_SHIFT 16 |
| 81 | #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT) |
| 82 | #define SPIDELAY_T2EDELAY_SHIFT 8 |
| 83 | #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT) |
| 84 | #define SPIDELAY_C2EDELAY_SHIFT 0 |
| 85 | #define SPIDELAY_C2EDELAY_MASK 0xFF |
| 86 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 87 | /* Error Masks */ |
| 88 | #define SPIFLG_DLEN_ERR_MASK BIT(0) |
| 89 | #define SPIFLG_TIMEOUT_MASK BIT(1) |
| 90 | #define SPIFLG_PARERR_MASK BIT(2) |
| 91 | #define SPIFLG_DESYNC_MASK BIT(3) |
| 92 | #define SPIFLG_BITERR_MASK BIT(4) |
| 93 | #define SPIFLG_OVRRUN_MASK BIT(6) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 94 | #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24) |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 95 | #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \ |
| 96 | | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \ |
| 97 | | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \ |
| 98 | | SPIFLG_OVRRUN_MASK) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 99 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 100 | #define SPIINT_DMA_REQ_EN BIT(16) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 101 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 102 | /* SPI Controller registers */ |
| 103 | #define SPIGCR0 0x00 |
| 104 | #define SPIGCR1 0x04 |
| 105 | #define SPIINT 0x08 |
| 106 | #define SPILVL 0x0c |
| 107 | #define SPIFLG 0x10 |
| 108 | #define SPIPC0 0x14 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 109 | #define SPIDAT1 0x3c |
| 110 | #define SPIBUF 0x40 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 111 | #define SPIDELAY 0x48 |
| 112 | #define SPIDEF 0x4c |
| 113 | #define SPIFMT0 0x50 |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 114 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 115 | /* We have 2 DMA channels per CS, one for RX and one for TX */ |
| 116 | struct davinci_spi_dma { |
| 117 | int dma_tx_channel; |
| 118 | int dma_rx_channel; |
| 119 | int dma_tx_sync_dev; |
| 120 | int dma_rx_sync_dev; |
| 121 | enum dma_event_q eventq; |
| 122 | |
| 123 | struct completion dma_tx_completion; |
| 124 | struct completion dma_rx_completion; |
| 125 | }; |
| 126 | |
| 127 | /* SPI Controller driver's private data. */ |
| 128 | struct davinci_spi { |
| 129 | struct spi_bitbang bitbang; |
| 130 | struct clk *clk; |
| 131 | |
| 132 | u8 version; |
| 133 | resource_size_t pbase; |
| 134 | void __iomem *base; |
| 135 | size_t region_size; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 136 | u32 irq; |
| 137 | struct completion done; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 138 | |
| 139 | const void *tx; |
| 140 | void *rx; |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 141 | #define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1) |
| 142 | u8 rx_tmp_buf[SPI_TMP_BUFSZ]; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 143 | int rcount; |
| 144 | int wcount; |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 145 | struct davinci_spi_dma dma_channels; |
Brian Niebuhr | 778e261 | 2010-09-03 15:15:06 +0530 | [diff] [blame] | 146 | struct davinci_spi_platform_data *pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 147 | |
| 148 | void (*get_rx)(u32 rx_data, struct davinci_spi *); |
| 149 | u32 (*get_tx)(struct davinci_spi *); |
| 150 | |
Brian Niebuhr | cda987e | 2010-08-19 16:16:28 +0530 | [diff] [blame] | 151 | u8 bytes_per_word[SPI_MAX_CHIPSELECT]; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 152 | }; |
| 153 | |
Brian Niebuhr | 53a31b0 | 2010-08-16 15:05:51 +0530 | [diff] [blame] | 154 | static struct davinci_spi_config davinci_spi_default_cfg; |
| 155 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 156 | static unsigned use_dma; |
| 157 | |
| 158 | static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi) |
| 159 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 160 | if (davinci_spi->rx) { |
| 161 | u8 *rx = davinci_spi->rx; |
| 162 | *rx++ = (u8)data; |
| 163 | davinci_spi->rx = rx; |
| 164 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 165 | } |
| 166 | |
| 167 | static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi) |
| 168 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 169 | if (davinci_spi->rx) { |
| 170 | u16 *rx = davinci_spi->rx; |
| 171 | *rx++ = (u16)data; |
| 172 | davinci_spi->rx = rx; |
| 173 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 174 | } |
| 175 | |
| 176 | static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi) |
| 177 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 178 | u32 data = 0; |
| 179 | if (davinci_spi->tx) { |
| 180 | const u8 *tx = davinci_spi->tx; |
| 181 | data = *tx++; |
| 182 | davinci_spi->tx = tx; |
| 183 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 184 | return data; |
| 185 | } |
| 186 | |
| 187 | static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi) |
| 188 | { |
Brian Niebuhr | 53d454a | 2010-08-19 17:04:25 +0530 | [diff] [blame] | 189 | u32 data = 0; |
| 190 | if (davinci_spi->tx) { |
| 191 | const u16 *tx = davinci_spi->tx; |
| 192 | data = *tx++; |
| 193 | davinci_spi->tx = tx; |
| 194 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 195 | return data; |
| 196 | } |
| 197 | |
| 198 | static inline void set_io_bits(void __iomem *addr, u32 bits) |
| 199 | { |
| 200 | u32 v = ioread32(addr); |
| 201 | |
| 202 | v |= bits; |
| 203 | iowrite32(v, addr); |
| 204 | } |
| 205 | |
| 206 | static inline void clear_io_bits(void __iomem *addr, u32 bits) |
| 207 | { |
| 208 | u32 v = ioread32(addr); |
| 209 | |
| 210 | v &= ~bits; |
| 211 | iowrite32(v, addr); |
| 212 | } |
| 213 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 214 | static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable) |
| 215 | { |
| 216 | struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master); |
| 217 | |
| 218 | if (enable) |
| 219 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); |
| 220 | else |
| 221 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN); |
| 222 | } |
| 223 | |
| 224 | /* |
| 225 | * Interface to control the chip select signal |
| 226 | */ |
| 227 | static void davinci_spi_chipselect(struct spi_device *spi, int value) |
| 228 | { |
| 229 | struct davinci_spi *davinci_spi; |
| 230 | struct davinci_spi_platform_data *pdata; |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 231 | u8 chip_sel = spi->chip_select; |
Brian Niebuhr | cfbc5d1 | 2010-08-12 12:27:33 +0530 | [diff] [blame] | 232 | u16 spidat1_cfg = CS_DEFAULT; |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 233 | bool gpio_chipsel = false; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 234 | |
| 235 | davinci_spi = spi_master_get_devdata(spi->master); |
| 236 | pdata = davinci_spi->pdata; |
| 237 | |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 238 | if (pdata->chip_sel && chip_sel < pdata->num_chipselect && |
| 239 | pdata->chip_sel[chip_sel] != SPI_INTERN_CS) |
| 240 | gpio_chipsel = true; |
| 241 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 242 | /* |
| 243 | * Board specific chip select logic decides the polarity and cs |
| 244 | * line for the controller |
| 245 | */ |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 246 | if (gpio_chipsel) { |
| 247 | if (value == BITBANG_CS_ACTIVE) |
| 248 | gpio_set_value(pdata->chip_sel[chip_sel], 0); |
| 249 | else |
| 250 | gpio_set_value(pdata->chip_sel[chip_sel], 1); |
| 251 | } else { |
| 252 | if (value == BITBANG_CS_ACTIVE) { |
| 253 | spidat1_cfg |= SPIDAT1_CSHOLD_MASK; |
| 254 | spidat1_cfg &= ~(0x1 << chip_sel); |
| 255 | } |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 256 | |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 257 | iowrite16(spidat1_cfg, davinci_spi->base + SPIDAT1 + 2); |
| 258 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 259 | } |
| 260 | |
| 261 | /** |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 262 | * davinci_spi_get_prescale - Calculates the correct prescale value |
| 263 | * @maxspeed_hz: the maximum rate the SPI clock can run at |
| 264 | * |
| 265 | * This function calculates the prescale value that generates a clock rate |
| 266 | * less than or equal to the specified maximum. |
| 267 | * |
| 268 | * Returns: calculated prescale - 1 for easy programming into SPI registers |
| 269 | * or negative error number if valid prescalar cannot be updated. |
| 270 | */ |
| 271 | static inline int davinci_spi_get_prescale(struct davinci_spi *davinci_spi, |
| 272 | u32 max_speed_hz) |
| 273 | { |
| 274 | int ret; |
| 275 | |
| 276 | ret = DIV_ROUND_UP(clk_get_rate(davinci_spi->clk), max_speed_hz); |
| 277 | |
| 278 | if (ret < 3 || ret > 256) |
| 279 | return -EINVAL; |
| 280 | |
| 281 | return ret - 1; |
| 282 | } |
| 283 | |
| 284 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 285 | * davinci_spi_setup_transfer - This functions will determine transfer method |
| 286 | * @spi: spi device on which data transfer to be done |
| 287 | * @t: spi transfer in which transfer info is filled |
| 288 | * |
| 289 | * This function determines data transfer method (8/16/32 bit transfer). |
| 290 | * It will also set the SPI Clock Control register according to |
| 291 | * SPI slave device freq. |
| 292 | */ |
| 293 | static int davinci_spi_setup_transfer(struct spi_device *spi, |
| 294 | struct spi_transfer *t) |
| 295 | { |
| 296 | |
| 297 | struct davinci_spi *davinci_spi; |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 298 | struct davinci_spi_config *spicfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 299 | u8 bits_per_word = 0; |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 300 | u32 hz = 0, spifmt = 0, prescale = 0; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 301 | |
| 302 | davinci_spi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 303 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
| 304 | if (!spicfg) |
| 305 | spicfg = &davinci_spi_default_cfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 306 | |
| 307 | if (t) { |
| 308 | bits_per_word = t->bits_per_word; |
| 309 | hz = t->speed_hz; |
| 310 | } |
| 311 | |
| 312 | /* if bits_per_word is not set then set it default */ |
| 313 | if (!bits_per_word) |
| 314 | bits_per_word = spi->bits_per_word; |
| 315 | |
| 316 | /* |
| 317 | * Assign function pointer to appropriate transfer method |
| 318 | * 8bit, 16bit or 32bit transfer |
| 319 | */ |
| 320 | if (bits_per_word <= 8 && bits_per_word >= 2) { |
| 321 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; |
| 322 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; |
Brian Niebuhr | cda987e | 2010-08-19 16:16:28 +0530 | [diff] [blame] | 323 | davinci_spi->bytes_per_word[spi->chip_select] = 1; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 324 | } else if (bits_per_word <= 16 && bits_per_word >= 2) { |
| 325 | davinci_spi->get_rx = davinci_spi_rx_buf_u16; |
| 326 | davinci_spi->get_tx = davinci_spi_tx_buf_u16; |
Brian Niebuhr | cda987e | 2010-08-19 16:16:28 +0530 | [diff] [blame] | 327 | davinci_spi->bytes_per_word[spi->chip_select] = 2; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 328 | } else |
| 329 | return -EINVAL; |
| 330 | |
| 331 | if (!hz) |
| 332 | hz = spi->max_speed_hz; |
| 333 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 334 | /* Set up SPIFMTn register, unique to this chipselect. */ |
| 335 | |
Brian Niebuhr | 7fe0092 | 2010-08-13 13:27:23 +0530 | [diff] [blame] | 336 | prescale = davinci_spi_get_prescale(davinci_spi, hz); |
| 337 | if (prescale < 0) |
| 338 | return prescale; |
| 339 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 340 | spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 341 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 342 | if (spi->mode & SPI_LSB_FIRST) |
| 343 | spifmt |= SPIFMT_SHIFTDIR_MASK; |
| 344 | |
| 345 | if (spi->mode & SPI_CPOL) |
| 346 | spifmt |= SPIFMT_POLARITY_MASK; |
| 347 | |
| 348 | if (!(spi->mode & SPI_CPHA)) |
| 349 | spifmt |= SPIFMT_PHASE_MASK; |
| 350 | |
| 351 | /* |
| 352 | * Version 1 hardware supports two basic SPI modes: |
| 353 | * - Standard SPI mode uses 4 pins, with chipselect |
| 354 | * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) |
| 355 | * (distinct from SPI_3WIRE, with just one data wire; |
| 356 | * or similar variants without MOSI or without MISO) |
| 357 | * |
| 358 | * Version 2 hardware supports an optional handshaking signal, |
| 359 | * so it can support two more modes: |
| 360 | * - 5 pin SPI variant is standard SPI plus SPI_READY |
| 361 | * - 4 pin with enable is (SPI_READY | SPI_NO_CS) |
| 362 | */ |
| 363 | |
| 364 | if (davinci_spi->version == SPI_VERSION_2) { |
| 365 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 366 | u32 delay = 0; |
| 367 | |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 368 | spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT) |
| 369 | & SPIFMT_WDELAY_MASK); |
| 370 | |
| 371 | if (spicfg->odd_parity) |
| 372 | spifmt |= SPIFMT_ODD_PARITY_MASK; |
| 373 | |
| 374 | if (spicfg->parity_enable) |
| 375 | spifmt |= SPIFMT_PARITYENA_MASK; |
| 376 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 377 | if (spicfg->timer_disable) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 378 | spifmt |= SPIFMT_DISTIMER_MASK; |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 379 | } else { |
| 380 | delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT) |
| 381 | & SPIDELAY_C2TDELAY_MASK; |
| 382 | delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT) |
| 383 | & SPIDELAY_T2CDELAY_MASK; |
| 384 | } |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 385 | |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 386 | if (spi->mode & SPI_READY) { |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 387 | spifmt |= SPIFMT_WAITENA_MASK; |
Brian Niebuhr | 7abbf23 | 2010-08-19 15:07:38 +0530 | [diff] [blame] | 388 | delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT) |
| 389 | & SPIDELAY_T2EDELAY_MASK; |
| 390 | delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT) |
| 391 | & SPIDELAY_C2EDELAY_MASK; |
| 392 | } |
| 393 | |
| 394 | iowrite32(delay, davinci_spi->base + SPIDELAY); |
Brian Niebuhr | 25f3351 | 2010-08-19 12:15:22 +0530 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | iowrite32(spifmt, davinci_spi->base + SPIFMT0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 398 | |
| 399 | return 0; |
| 400 | } |
| 401 | |
| 402 | static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data) |
| 403 | { |
| 404 | struct spi_device *spi = (struct spi_device *)data; |
| 405 | struct davinci_spi *davinci_spi; |
| 406 | struct davinci_spi_dma *davinci_spi_dma; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 407 | |
| 408 | davinci_spi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 409 | davinci_spi_dma = &davinci_spi->dma_channels; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 410 | |
| 411 | if (ch_status == DMA_COMPLETE) |
| 412 | edma_stop(davinci_spi_dma->dma_rx_channel); |
| 413 | else |
| 414 | edma_clean_channel(davinci_spi_dma->dma_rx_channel); |
| 415 | |
| 416 | complete(&davinci_spi_dma->dma_rx_completion); |
| 417 | /* We must disable the DMA RX request */ |
| 418 | davinci_spi_set_dma_req(spi, 0); |
| 419 | } |
| 420 | |
| 421 | static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data) |
| 422 | { |
| 423 | struct spi_device *spi = (struct spi_device *)data; |
| 424 | struct davinci_spi *davinci_spi; |
| 425 | struct davinci_spi_dma *davinci_spi_dma; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 426 | |
| 427 | davinci_spi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 428 | davinci_spi_dma = &davinci_spi->dma_channels; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 429 | |
| 430 | if (ch_status == DMA_COMPLETE) |
| 431 | edma_stop(davinci_spi_dma->dma_tx_channel); |
| 432 | else |
| 433 | edma_clean_channel(davinci_spi_dma->dma_tx_channel); |
| 434 | |
| 435 | complete(&davinci_spi_dma->dma_tx_completion); |
| 436 | /* We must disable the DMA TX request */ |
| 437 | davinci_spi_set_dma_req(spi, 0); |
| 438 | } |
| 439 | |
| 440 | static int davinci_spi_request_dma(struct spi_device *spi) |
| 441 | { |
| 442 | struct davinci_spi *davinci_spi; |
| 443 | struct davinci_spi_dma *davinci_spi_dma; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 444 | struct device *sdev; |
| 445 | int r; |
| 446 | |
| 447 | davinci_spi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 448 | davinci_spi_dma = &davinci_spi->dma_channels; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 449 | sdev = davinci_spi->bitbang.master->dev.parent; |
| 450 | |
| 451 | r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev, |
| 452 | davinci_spi_dma_rx_callback, spi, |
| 453 | davinci_spi_dma->eventq); |
| 454 | if (r < 0) { |
| 455 | dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n"); |
| 456 | return -EAGAIN; |
| 457 | } |
| 458 | davinci_spi_dma->dma_rx_channel = r; |
| 459 | r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev, |
| 460 | davinci_spi_dma_tx_callback, spi, |
| 461 | davinci_spi_dma->eventq); |
| 462 | if (r < 0) { |
| 463 | edma_free_channel(davinci_spi_dma->dma_rx_channel); |
| 464 | davinci_spi_dma->dma_rx_channel = -1; |
| 465 | dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n"); |
| 466 | return -EAGAIN; |
| 467 | } |
| 468 | davinci_spi_dma->dma_tx_channel = r; |
| 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | /** |
| 474 | * davinci_spi_setup - This functions will set default transfer method |
| 475 | * @spi: spi device on which data transfer to be done |
| 476 | * |
| 477 | * This functions sets the default transfer method. |
| 478 | */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 479 | static int davinci_spi_setup(struct spi_device *spi) |
| 480 | { |
Brian Niebuhr | b23a5d4 | 2010-09-24 18:53:32 +0530 | [diff] [blame] | 481 | int retval = 0; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 482 | struct davinci_spi *davinci_spi; |
| 483 | struct davinci_spi_dma *davinci_spi_dma; |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 484 | struct davinci_spi_platform_data *pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 485 | |
| 486 | davinci_spi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 487 | pdata = davinci_spi->pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 488 | |
| 489 | /* if bits per word length is zero then set it default 8 */ |
| 490 | if (!spi->bits_per_word) |
| 491 | spi->bits_per_word = 8; |
| 492 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 493 | if (!(spi->mode & SPI_NO_CS)) { |
| 494 | if ((pdata->chip_sel == NULL) || |
| 495 | (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS)) |
| 496 | set_io_bits(davinci_spi->base + SPIPC0, |
| 497 | 1 << spi->chip_select); |
| 498 | |
| 499 | } |
| 500 | |
| 501 | if (spi->mode & SPI_READY) |
| 502 | set_io_bits(davinci_spi->base + SPIPC0, SPIPC0_SPIENA_MASK); |
| 503 | |
| 504 | if (spi->mode & SPI_LOOP) |
| 505 | set_io_bits(davinci_spi->base + SPIGCR1, |
| 506 | SPIGCR1_LOOPBACK_MASK); |
| 507 | else |
| 508 | clear_io_bits(davinci_spi->base + SPIGCR1, |
| 509 | SPIGCR1_LOOPBACK_MASK); |
| 510 | |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 511 | if (use_dma) { |
| 512 | davinci_spi_dma = &davinci_spi->dma_channels; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 513 | |
Brian Niebuhr | b23a5d4 | 2010-09-24 18:53:32 +0530 | [diff] [blame] | 514 | if ((davinci_spi_dma->dma_rx_channel == -1) || |
| 515 | (davinci_spi_dma->dma_tx_channel == -1)) |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 516 | retval = davinci_spi_request_dma(spi); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 517 | } |
| 518 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 519 | return retval; |
| 520 | } |
| 521 | |
| 522 | static void davinci_spi_cleanup(struct spi_device *spi) |
| 523 | { |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 524 | if (use_dma) { |
| 525 | struct davinci_spi *davinci_spi = |
| 526 | spi_master_get_devdata(spi->master); |
| 527 | struct davinci_spi_dma *davinci_spi_dma = |
| 528 | &davinci_spi->dma_channels; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 529 | |
| 530 | if ((davinci_spi_dma->dma_rx_channel != -1) |
| 531 | && (davinci_spi_dma->dma_tx_channel != -1)) { |
| 532 | edma_free_channel(davinci_spi_dma->dma_tx_channel); |
| 533 | edma_free_channel(davinci_spi_dma->dma_rx_channel); |
| 534 | } |
| 535 | } |
| 536 | } |
| 537 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 538 | static int davinci_spi_check_error(struct davinci_spi *davinci_spi, |
| 539 | int int_status) |
| 540 | { |
| 541 | struct device *sdev = davinci_spi->bitbang.master->dev.parent; |
| 542 | |
| 543 | if (int_status & SPIFLG_TIMEOUT_MASK) { |
| 544 | dev_dbg(sdev, "SPI Time-out Error\n"); |
| 545 | return -ETIMEDOUT; |
| 546 | } |
| 547 | if (int_status & SPIFLG_DESYNC_MASK) { |
| 548 | dev_dbg(sdev, "SPI Desynchronization Error\n"); |
| 549 | return -EIO; |
| 550 | } |
| 551 | if (int_status & SPIFLG_BITERR_MASK) { |
| 552 | dev_dbg(sdev, "SPI Bit error\n"); |
| 553 | return -EIO; |
| 554 | } |
| 555 | |
| 556 | if (davinci_spi->version == SPI_VERSION_2) { |
| 557 | if (int_status & SPIFLG_DLEN_ERR_MASK) { |
| 558 | dev_dbg(sdev, "SPI Data Length Error\n"); |
| 559 | return -EIO; |
| 560 | } |
| 561 | if (int_status & SPIFLG_PARERR_MASK) { |
| 562 | dev_dbg(sdev, "SPI Parity Error\n"); |
| 563 | return -EIO; |
| 564 | } |
| 565 | if (int_status & SPIFLG_OVRRUN_MASK) { |
| 566 | dev_dbg(sdev, "SPI Data Overrun error\n"); |
| 567 | return -EIO; |
| 568 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 569 | if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) { |
| 570 | dev_dbg(sdev, "SPI Buffer Init Active\n"); |
| 571 | return -EBUSY; |
| 572 | } |
| 573 | } |
| 574 | |
| 575 | return 0; |
| 576 | } |
| 577 | |
| 578 | /** |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 579 | * davinci_spi_process_events - check for and handle any SPI controller events |
| 580 | * @davinci_spi: the controller data |
| 581 | * |
| 582 | * This function will check the SPIFLG register and handle any events that are |
| 583 | * detected there |
| 584 | */ |
| 585 | static int davinci_spi_process_events(struct davinci_spi *davinci_spi) |
| 586 | { |
| 587 | u32 buf, status, errors = 0, data1_reg_val; |
| 588 | |
| 589 | buf = ioread32(davinci_spi->base + SPIBUF); |
| 590 | |
| 591 | if (davinci_spi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) { |
| 592 | davinci_spi->get_rx(buf & 0xFFFF, davinci_spi); |
| 593 | davinci_spi->rcount--; |
| 594 | } |
| 595 | |
| 596 | status = ioread32(davinci_spi->base + SPIFLG); |
| 597 | |
| 598 | if (unlikely(status & SPIFLG_ERROR_MASK)) { |
| 599 | errors = status & SPIFLG_ERROR_MASK; |
| 600 | goto out; |
| 601 | } |
| 602 | |
| 603 | if (davinci_spi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) { |
| 604 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
| 605 | davinci_spi->wcount--; |
| 606 | data1_reg_val &= ~0xFFFF; |
| 607 | data1_reg_val |= 0xFFFF & davinci_spi->get_tx(davinci_spi); |
| 608 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); |
| 609 | } |
| 610 | |
| 611 | out: |
| 612 | return errors; |
| 613 | } |
| 614 | |
| 615 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 616 | * davinci_spi_bufs - functions which will handle transfer data |
| 617 | * @spi: spi device on which data transfer to be done |
| 618 | * @t: spi transfer in which transfer info is filled |
| 619 | * |
| 620 | * This function will put data to be transferred into data register |
| 621 | * of SPI controller and then wait until the completion will be marked |
| 622 | * by the IRQ Handler. |
| 623 | */ |
| 624 | static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t) |
| 625 | { |
| 626 | struct davinci_spi *davinci_spi; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 627 | int ret; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 628 | u32 tx_data, data1_reg_val; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 629 | u32 errors = 0; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 630 | struct davinci_spi_config *spicfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 631 | struct davinci_spi_platform_data *pdata; |
| 632 | |
| 633 | davinci_spi = spi_master_get_devdata(spi->master); |
| 634 | pdata = davinci_spi->pdata; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 635 | spicfg = (struct davinci_spi_config *)spi->controller_data; |
| 636 | if (!spicfg) |
| 637 | spicfg = &davinci_spi_default_cfg; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 638 | |
| 639 | davinci_spi->tx = t->tx_buf; |
| 640 | davinci_spi->rx = t->rx_buf; |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 641 | davinci_spi->wcount = t->len / |
| 642 | davinci_spi->bytes_per_word[spi->chip_select]; |
| 643 | davinci_spi->rcount = davinci_spi->wcount; |
Brian Niebuhr | 7978b8c | 2010-08-13 10:11:03 +0530 | [diff] [blame] | 644 | |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 645 | data1_reg_val = ioread32(davinci_spi->base + SPIDAT1); |
| 646 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 647 | /* Enable SPI */ |
| 648 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
| 649 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 650 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { |
| 651 | set_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); |
| 652 | INIT_COMPLETION(davinci_spi->done); |
| 653 | } |
Brian Niebuhr | cf90fe7 | 2010-08-20 17:02:49 +0530 | [diff] [blame] | 654 | |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 655 | /* start the transfer */ |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 656 | davinci_spi->wcount--; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 657 | tx_data = davinci_spi->get_tx(davinci_spi); |
| 658 | data1_reg_val &= 0xFFFF0000; |
| 659 | data1_reg_val |= tx_data & 0xFFFF; |
| 660 | iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 661 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 662 | /* Wait for the transfer to complete */ |
| 663 | if (spicfg->io_type == SPI_IO_TYPE_INTR) { |
| 664 | wait_for_completion_interruptible(&(davinci_spi->done)); |
| 665 | } else { |
| 666 | while (davinci_spi->rcount > 0 || davinci_spi->wcount > 0) { |
| 667 | errors = davinci_spi_process_events(davinci_spi); |
| 668 | if (errors) |
| 669 | break; |
| 670 | cpu_relax(); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 671 | } |
| 672 | } |
| 673 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 674 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
| 675 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 676 | /* |
| 677 | * Check for bit error, desync error,parity error,timeout error and |
| 678 | * receive overflow errors |
| 679 | */ |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 680 | if (errors) { |
| 681 | ret = davinci_spi_check_error(davinci_spi, errors); |
| 682 | WARN(!ret, "%s: error reported but no error found!\n", |
| 683 | dev_name(&spi->dev)); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 684 | return ret; |
Brian Niebuhr | 839c996 | 2010-08-23 16:39:19 +0530 | [diff] [blame] | 685 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 686 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 687 | return t->len; |
| 688 | } |
| 689 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 690 | /** |
| 691 | * davinci_spi_irq - Interrupt handler for SPI Master Controller |
| 692 | * @irq: IRQ number for this SPI Master |
| 693 | * @context_data: structure for SPI Master controller davinci_spi |
| 694 | * |
| 695 | * ISR will determine that interrupt arrives either for READ or WRITE command. |
| 696 | * According to command it will do the appropriate action. It will check |
| 697 | * transfer length and if it is not zero then dispatch transfer command again. |
| 698 | * If transfer length is zero then it will indicate the COMPLETION so that |
| 699 | * davinci_spi_bufs function can go ahead. |
| 700 | */ |
| 701 | static irqreturn_t davinci_spi_irq(s32 irq, void *context_data) |
| 702 | { |
| 703 | struct davinci_spi *davinci_spi = context_data; |
| 704 | int status; |
| 705 | |
| 706 | status = davinci_spi_process_events(davinci_spi); |
| 707 | if (unlikely(status != 0)) |
| 708 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKINT); |
| 709 | |
| 710 | if ((!davinci_spi->rcount && !davinci_spi->wcount) || status) |
| 711 | complete(&davinci_spi->done); |
| 712 | |
| 713 | return IRQ_HANDLED; |
| 714 | } |
| 715 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 716 | static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t) |
| 717 | { |
| 718 | struct davinci_spi *davinci_spi; |
| 719 | int int_status = 0; |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 720 | int count; |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 721 | unsigned rx_buf_count; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 722 | struct davinci_spi_dma *davinci_spi_dma; |
Brian Niebuhr | b7ab24a | 2010-08-19 16:42:42 +0530 | [diff] [blame] | 723 | int data_type, ret; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 724 | unsigned long tx_reg, rx_reg; |
Brian Niebuhr | c29e3c6 | 2010-09-28 13:59:26 +0530 | [diff] [blame] | 725 | struct davinci_spi_platform_data *pdata; |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 726 | void *rx_buf; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 727 | struct device *sdev; |
| 728 | |
| 729 | davinci_spi = spi_master_get_devdata(spi->master); |
Brian Niebuhr | c29e3c6 | 2010-09-28 13:59:26 +0530 | [diff] [blame] | 730 | pdata = davinci_spi->pdata; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 731 | sdev = davinci_spi->bitbang.master->dev.parent; |
| 732 | |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 733 | davinci_spi_dma = &davinci_spi->dma_channels; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 734 | |
| 735 | tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1; |
| 736 | rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF; |
| 737 | |
| 738 | davinci_spi->tx = t->tx_buf; |
| 739 | davinci_spi->rx = t->rx_buf; |
| 740 | |
| 741 | /* convert len to words based on bits_per_word */ |
Brian Niebuhr | b7ab24a | 2010-08-19 16:42:42 +0530 | [diff] [blame] | 742 | data_type = davinci_spi->bytes_per_word[spi->chip_select]; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 743 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 744 | init_completion(&davinci_spi_dma->dma_rx_completion); |
| 745 | init_completion(&davinci_spi_dma->dma_tx_completion); |
| 746 | |
Brian Niebuhr | f2bf4e8 | 2010-08-20 15:28:23 +0530 | [diff] [blame] | 747 | count = t->len / data_type; /* the number of elements */ |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 748 | |
| 749 | /* disable all interrupts for dma transfers */ |
| 750 | clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 751 | /* Enable SPI */ |
| 752 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK); |
| 753 | |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 754 | /* |
| 755 | * Transmit DMA setup |
| 756 | * |
| 757 | * If there is transmit data, map the transmit buffer, set it as the |
| 758 | * source of data and set the source B index to data size. |
| 759 | * If there is no transmit data, set the transmit register as the |
| 760 | * source of data, and set the source B index to zero. |
| 761 | * |
| 762 | * The destination is always the transmit register itself. And the |
| 763 | * destination never increments. |
| 764 | */ |
| 765 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 766 | if (t->tx_buf) { |
| 767 | t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count, |
| 768 | DMA_TO_DEVICE); |
| 769 | if (dma_mapping_error(&spi->dev, t->tx_dma)) { |
| 770 | dev_dbg(sdev, "Unable to DMA map a %d bytes" |
| 771 | " TX buffer\n", count); |
| 772 | return -ENOMEM; |
| 773 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 774 | } |
| 775 | |
| 776 | edma_set_transfer_params(davinci_spi_dma->dma_tx_channel, |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 777 | data_type, count, 1, 0, ASYNC); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 778 | edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT); |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 779 | edma_set_src(davinci_spi_dma->dma_tx_channel, |
| 780 | t->tx_buf ? t->tx_dma : tx_reg, INCR, W8BIT); |
| 781 | edma_set_src_index(davinci_spi_dma->dma_tx_channel, |
| 782 | t->tx_buf ? data_type : 0, 0); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 783 | edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0); |
| 784 | |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 785 | /* |
| 786 | * Receive DMA setup |
| 787 | * |
| 788 | * If there is receive buffer, use it to receive data. If there |
| 789 | * is none provided, use a temporary receive buffer. Set the |
| 790 | * destination B index to 0 so effectively only one byte is used |
| 791 | * in the temporary buffer (address does not increment). |
| 792 | * |
| 793 | * The source of receive data is the receive data register. The |
| 794 | * source address never increments. |
| 795 | */ |
| 796 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 797 | if (t->rx_buf) { |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 798 | rx_buf = t->rx_buf; |
| 799 | rx_buf_count = count; |
| 800 | } else { |
| 801 | rx_buf = davinci_spi->rx_tmp_buf; |
| 802 | rx_buf_count = sizeof(davinci_spi->rx_tmp_buf); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 803 | } |
| 804 | |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 805 | t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count, |
| 806 | DMA_FROM_DEVICE); |
| 807 | if (dma_mapping_error(&spi->dev, t->rx_dma)) { |
| 808 | dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n", |
| 809 | rx_buf_count); |
| 810 | if (t->tx_buf) |
| 811 | dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE); |
| 812 | return -ENOMEM; |
| 813 | } |
| 814 | |
| 815 | edma_set_transfer_params(davinci_spi_dma->dma_rx_channel, data_type, |
| 816 | count, 1, 0, ASYNC); |
| 817 | edma_set_src(davinci_spi_dma->dma_rx_channel, rx_reg, INCR, W8BIT); |
| 818 | edma_set_dest(davinci_spi_dma->dma_rx_channel, t->rx_dma, INCR, W8BIT); |
| 819 | edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0); |
| 820 | edma_set_dest_index(davinci_spi_dma->dma_rx_channel, |
| 821 | t->rx_buf ? data_type : 0, 0); |
| 822 | |
Brian Niebuhr | c29e3c6 | 2010-09-28 13:59:26 +0530 | [diff] [blame] | 823 | if (pdata->cshold_bug) { |
| 824 | u16 spidat1 = ioread16(davinci_spi->base + SPIDAT1 + 2); |
| 825 | iowrite16(spidat1, davinci_spi->base + SPIDAT1 + 2); |
| 826 | } |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 827 | |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 828 | edma_start(davinci_spi_dma->dma_rx_channel); |
Brian Niebuhr | c29e3c6 | 2010-09-28 13:59:26 +0530 | [diff] [blame] | 829 | edma_start(davinci_spi_dma->dma_tx_channel); |
| 830 | davinci_spi_set_dma_req(spi, 1); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 831 | |
Brian Niebuhr | c29e3c6 | 2010-09-28 13:59:26 +0530 | [diff] [blame] | 832 | wait_for_completion_interruptible(&davinci_spi_dma->dma_tx_completion); |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 833 | wait_for_completion_interruptible(&davinci_spi_dma->dma_rx_completion); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 834 | |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 835 | if (t->tx_buf) |
| 836 | dma_unmap_single(NULL, t->tx_dma, count, DMA_TO_DEVICE); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 837 | |
Brian Niebuhr | e91c659 | 2010-10-01 10:29:29 +0530 | [diff] [blame^] | 838 | dma_unmap_single(NULL, t->rx_dma, rx_buf_count, DMA_FROM_DEVICE); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 839 | |
| 840 | /* |
| 841 | * Check for bit error, desync error,parity error,timeout error and |
| 842 | * receive overflow errors |
| 843 | */ |
| 844 | int_status = ioread32(davinci_spi->base + SPIFLG); |
| 845 | |
| 846 | ret = davinci_spi_check_error(davinci_spi, int_status); |
| 847 | if (ret != 0) |
| 848 | return ret; |
| 849 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 850 | return t->len; |
| 851 | } |
| 852 | |
| 853 | /** |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 854 | * davinci_spi_probe - probe function for SPI Master Controller |
| 855 | * @pdev: platform_device structure which contains plateform specific data |
| 856 | */ |
| 857 | static int davinci_spi_probe(struct platform_device *pdev) |
| 858 | { |
| 859 | struct spi_master *master; |
| 860 | struct davinci_spi *davinci_spi; |
| 861 | struct davinci_spi_platform_data *pdata; |
| 862 | struct resource *r, *mem; |
| 863 | resource_size_t dma_rx_chan = SPI_NO_RESOURCE; |
| 864 | resource_size_t dma_tx_chan = SPI_NO_RESOURCE; |
| 865 | resource_size_t dma_eventq = SPI_NO_RESOURCE; |
| 866 | int i = 0, ret = 0; |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 867 | u32 spipc0; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 868 | |
| 869 | pdata = pdev->dev.platform_data; |
| 870 | if (pdata == NULL) { |
| 871 | ret = -ENODEV; |
| 872 | goto err; |
| 873 | } |
| 874 | |
| 875 | master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi)); |
| 876 | if (master == NULL) { |
| 877 | ret = -ENOMEM; |
| 878 | goto err; |
| 879 | } |
| 880 | |
| 881 | dev_set_drvdata(&pdev->dev, master); |
| 882 | |
| 883 | davinci_spi = spi_master_get_devdata(master); |
| 884 | if (davinci_spi == NULL) { |
| 885 | ret = -ENOENT; |
| 886 | goto free_master; |
| 887 | } |
| 888 | |
| 889 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 890 | if (r == NULL) { |
| 891 | ret = -ENOENT; |
| 892 | goto free_master; |
| 893 | } |
| 894 | |
| 895 | davinci_spi->pbase = r->start; |
| 896 | davinci_spi->region_size = resource_size(r); |
| 897 | davinci_spi->pdata = pdata; |
| 898 | |
| 899 | mem = request_mem_region(r->start, davinci_spi->region_size, |
| 900 | pdev->name); |
| 901 | if (mem == NULL) { |
| 902 | ret = -EBUSY; |
| 903 | goto free_master; |
| 904 | } |
| 905 | |
Sekhar Nori | 50356dd | 2010-10-08 15:27:26 +0530 | [diff] [blame] | 906 | davinci_spi->base = ioremap(r->start, davinci_spi->region_size); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 907 | if (davinci_spi->base == NULL) { |
| 908 | ret = -ENOMEM; |
| 909 | goto release_region; |
| 910 | } |
| 911 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 912 | davinci_spi->irq = platform_get_irq(pdev, 0); |
| 913 | if (davinci_spi->irq <= 0) { |
| 914 | ret = -EINVAL; |
| 915 | goto unmap_io; |
| 916 | } |
| 917 | |
| 918 | ret = request_irq(davinci_spi->irq, davinci_spi_irq, 0, |
| 919 | dev_name(&pdev->dev), davinci_spi); |
| 920 | if (ret) |
| 921 | goto unmap_io; |
| 922 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 923 | davinci_spi->bitbang.master = spi_master_get(master); |
| 924 | if (davinci_spi->bitbang.master == NULL) { |
| 925 | ret = -ENODEV; |
Brian Niebuhr | d3f7141 | 2010-09-29 12:31:54 +0530 | [diff] [blame] | 926 | goto irq_free; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 927 | } |
| 928 | |
| 929 | davinci_spi->clk = clk_get(&pdev->dev, NULL); |
| 930 | if (IS_ERR(davinci_spi->clk)) { |
| 931 | ret = -ENODEV; |
| 932 | goto put_master; |
| 933 | } |
| 934 | clk_enable(davinci_spi->clk); |
| 935 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 936 | master->bus_num = pdev->id; |
| 937 | master->num_chipselect = pdata->num_chipselect; |
| 938 | master->setup = davinci_spi_setup; |
| 939 | master->cleanup = davinci_spi_cleanup; |
| 940 | |
| 941 | davinci_spi->bitbang.chipselect = davinci_spi_chipselect; |
| 942 | davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer; |
| 943 | |
| 944 | davinci_spi->version = pdata->version; |
| 945 | use_dma = pdata->use_dma; |
| 946 | |
| 947 | davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP; |
| 948 | if (davinci_spi->version == SPI_VERSION_2) |
| 949 | davinci_spi->bitbang.flags |= SPI_READY; |
| 950 | |
| 951 | if (use_dma) { |
Brian Niebuhr | 778e261 | 2010-09-03 15:15:06 +0530 | [diff] [blame] | 952 | r = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
| 953 | if (r) |
| 954 | dma_rx_chan = r->start; |
| 955 | r = platform_get_resource(pdev, IORESOURCE_DMA, 1); |
| 956 | if (r) |
| 957 | dma_tx_chan = r->start; |
| 958 | r = platform_get_resource(pdev, IORESOURCE_DMA, 2); |
| 959 | if (r) |
| 960 | dma_eventq = r->start; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 961 | } |
| 962 | |
| 963 | if (!use_dma || |
| 964 | dma_rx_chan == SPI_NO_RESOURCE || |
| 965 | dma_tx_chan == SPI_NO_RESOURCE || |
| 966 | dma_eventq == SPI_NO_RESOURCE) { |
| 967 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio; |
| 968 | use_dma = 0; |
| 969 | } else { |
| 970 | davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma; |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 971 | |
Brian Niebuhr | 96fd881 | 2010-09-27 22:23:23 +0530 | [diff] [blame] | 972 | davinci_spi->dma_channels.dma_rx_channel = -1; |
| 973 | davinci_spi->dma_channels.dma_rx_sync_dev = dma_rx_chan; |
| 974 | davinci_spi->dma_channels.dma_tx_channel = -1; |
| 975 | davinci_spi->dma_channels.dma_tx_sync_dev = dma_tx_chan; |
| 976 | davinci_spi->dma_channels.eventq = dma_eventq; |
| 977 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 978 | dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n" |
| 979 | "Using RX channel = %d , TX channel = %d and " |
| 980 | "event queue = %d", dma_rx_chan, dma_tx_chan, |
| 981 | dma_eventq); |
| 982 | } |
| 983 | |
| 984 | davinci_spi->get_rx = davinci_spi_rx_buf_u8; |
| 985 | davinci_spi->get_tx = davinci_spi_tx_buf_u8; |
| 986 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 987 | init_completion(&davinci_spi->done); |
| 988 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 989 | /* Reset In/OUT SPI module */ |
| 990 | iowrite32(0, davinci_spi->base + SPIGCR0); |
| 991 | udelay(100); |
| 992 | iowrite32(1, davinci_spi->base + SPIGCR0); |
| 993 | |
Brian Niebuhr | be88471 | 2010-09-03 12:15:28 +0530 | [diff] [blame] | 994 | /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ |
Brian Niebuhr | f34bd4c | 2010-09-03 11:56:35 +0530 | [diff] [blame] | 995 | spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK; |
| 996 | iowrite32(spipc0, davinci_spi->base + SPIPC0); |
| 997 | |
Brian Niebuhr | 2385397 | 2010-08-13 10:57:44 +0530 | [diff] [blame] | 998 | /* initialize chip selects */ |
| 999 | if (pdata->chip_sel) { |
| 1000 | for (i = 0; i < pdata->num_chipselect; i++) { |
| 1001 | if (pdata->chip_sel[i] != SPI_INTERN_CS) |
| 1002 | gpio_direction_output(pdata->chip_sel[i], 1); |
| 1003 | } |
| 1004 | } |
| 1005 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1006 | /* Clock internal */ |
| 1007 | if (davinci_spi->pdata->clk_internal) |
| 1008 | set_io_bits(davinci_spi->base + SPIGCR1, |
| 1009 | SPIGCR1_CLKMOD_MASK); |
| 1010 | else |
| 1011 | clear_io_bits(davinci_spi->base + SPIGCR1, |
| 1012 | SPIGCR1_CLKMOD_MASK); |
| 1013 | |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1014 | if (pdata->intr_line) |
| 1015 | iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL); |
| 1016 | else |
| 1017 | iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL); |
| 1018 | |
Brian Niebuhr | 843a713 | 2010-08-12 12:49:05 +0530 | [diff] [blame] | 1019 | iowrite32(CS_DEFAULT, davinci_spi->base + SPIDEF); |
| 1020 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1021 | /* master mode default */ |
| 1022 | set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK); |
| 1023 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1024 | ret = spi_bitbang_start(&davinci_spi->bitbang); |
| 1025 | if (ret) |
| 1026 | goto free_clk; |
| 1027 | |
Brian Niebuhr | 3b740b1 | 2010-09-03 14:50:07 +0530 | [diff] [blame] | 1028 | dev_info(&pdev->dev, "Controller at 0x%p\n", davinci_spi->base); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1029 | |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1030 | return ret; |
| 1031 | |
| 1032 | free_clk: |
| 1033 | clk_disable(davinci_spi->clk); |
| 1034 | clk_put(davinci_spi->clk); |
| 1035 | put_master: |
| 1036 | spi_master_put(master); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1037 | irq_free: |
| 1038 | free_irq(davinci_spi->irq, davinci_spi); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1039 | unmap_io: |
| 1040 | iounmap(davinci_spi->base); |
| 1041 | release_region: |
| 1042 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); |
| 1043 | free_master: |
| 1044 | kfree(master); |
| 1045 | err: |
| 1046 | return ret; |
| 1047 | } |
| 1048 | |
| 1049 | /** |
| 1050 | * davinci_spi_remove - remove function for SPI Master Controller |
| 1051 | * @pdev: platform_device structure which contains plateform specific data |
| 1052 | * |
| 1053 | * This function will do the reverse action of davinci_spi_probe function |
| 1054 | * It will free the IRQ and SPI controller's memory region. |
| 1055 | * It will also call spi_bitbang_stop to destroy the work queue which was |
| 1056 | * created by spi_bitbang_start. |
| 1057 | */ |
| 1058 | static int __exit davinci_spi_remove(struct platform_device *pdev) |
| 1059 | { |
| 1060 | struct davinci_spi *davinci_spi; |
| 1061 | struct spi_master *master; |
| 1062 | |
| 1063 | master = dev_get_drvdata(&pdev->dev); |
| 1064 | davinci_spi = spi_master_get_devdata(master); |
| 1065 | |
| 1066 | spi_bitbang_stop(&davinci_spi->bitbang); |
| 1067 | |
| 1068 | clk_disable(davinci_spi->clk); |
| 1069 | clk_put(davinci_spi->clk); |
| 1070 | spi_master_put(master); |
Brian Niebuhr | e0d205e | 2010-09-02 16:52:06 +0530 | [diff] [blame] | 1071 | free_irq(davinci_spi->irq, davinci_spi); |
Sandeep Paulraj | 358934a | 2009-12-16 22:02:18 +0000 | [diff] [blame] | 1072 | iounmap(davinci_spi->base); |
| 1073 | release_mem_region(davinci_spi->pbase, davinci_spi->region_size); |
| 1074 | |
| 1075 | return 0; |
| 1076 | } |
| 1077 | |
| 1078 | static struct platform_driver davinci_spi_driver = { |
| 1079 | .driver.name = "spi_davinci", |
| 1080 | .remove = __exit_p(davinci_spi_remove), |
| 1081 | }; |
| 1082 | |
| 1083 | static int __init davinci_spi_init(void) |
| 1084 | { |
| 1085 | return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe); |
| 1086 | } |
| 1087 | module_init(davinci_spi_init); |
| 1088 | |
| 1089 | static void __exit davinci_spi_exit(void) |
| 1090 | { |
| 1091 | platform_driver_unregister(&davinci_spi_driver); |
| 1092 | } |
| 1093 | module_exit(davinci_spi_exit); |
| 1094 | |
| 1095 | MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver"); |
| 1096 | MODULE_LICENSE("GPL"); |