Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_ASIC_H__ |
| 29 | #define __RADEON_ASIC_H__ |
| 30 | |
| 31 | /* |
| 32 | * common functions |
| 33 | */ |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 34 | uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
Rafał Miłecki | 5ea597f | 2009-12-17 13:50:09 +0100 | [diff] [blame] | 36 | uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| 38 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 39 | uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 40 | void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 41 | uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 42 | void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| 43 | void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
| 44 | |
| 45 | /* |
| 46 | * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
| 47 | */ |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 48 | extern int r100_init(struct radeon_device *rdev); |
| 49 | extern void r100_fini(struct radeon_device *rdev); |
| 50 | extern int r100_suspend(struct radeon_device *rdev); |
| 51 | extern int r100_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 52 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| 53 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 54 | void r100_vga_set_state(struct radeon_device *rdev, bool state); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 55 | int r100_gpu_reset(struct radeon_device *rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 56 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 57 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| 58 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 59 | void r100_cp_commit(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 60 | void r100_ring_start(struct radeon_device *rdev); |
| 61 | int r100_irq_set(struct radeon_device *rdev); |
| 62 | int r100_irq_process(struct radeon_device *rdev); |
| 63 | void r100_fence_ring_emit(struct radeon_device *rdev, |
| 64 | struct radeon_fence *fence); |
| 65 | int r100_cs_parse(struct radeon_cs_parser *p); |
| 66 | void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 67 | uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
| 68 | int r100_copy_blit(struct radeon_device *rdev, |
| 69 | uint64_t src_offset, |
| 70 | uint64_t dst_offset, |
| 71 | unsigned num_pages, |
| 72 | struct radeon_fence *fence); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 73 | int r100_set_surface_reg(struct radeon_device *rdev, int reg, |
| 74 | uint32_t tiling_flags, uint32_t pitch, |
| 75 | uint32_t offset, uint32_t obj_size); |
| 76 | int r100_clear_surface_reg(struct radeon_device *rdev, int reg); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 77 | void r100_bandwidth_update(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 78 | void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 79 | int r100_ring_test(struct radeon_device *rdev); |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 80 | void r100_hpd_init(struct radeon_device *rdev); |
| 81 | void r100_hpd_fini(struct radeon_device *rdev); |
| 82 | bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 83 | void r100_hpd_set_polarity(struct radeon_device *rdev, |
| 84 | enum radeon_hpd_id hpd); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 85 | |
| 86 | static struct radeon_asic r100_asic = { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 87 | .init = &r100_init, |
Jerome Glisse | d455090 | 2009-10-01 10:12:06 +0200 | [diff] [blame] | 88 | .fini = &r100_fini, |
| 89 | .suspend = &r100_suspend, |
| 90 | .resume = &r100_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 91 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 92 | .gpu_reset = &r100_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 93 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 94 | .gart_set_page = &r100_pci_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 95 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | .ring_start = &r100_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 97 | .ring_test = &r100_ring_test, |
| 98 | .ring_ib_execute = &r100_ring_ib_execute, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 99 | .irq_set = &r100_irq_set, |
| 100 | .irq_process = &r100_irq_process, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 101 | .get_vblank_counter = &r100_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 102 | .fence_ring_emit = &r100_fence_ring_emit, |
| 103 | .cs_parse = &r100_cs_parse, |
| 104 | .copy_blit = &r100_copy_blit, |
| 105 | .copy_dma = NULL, |
| 106 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 107 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
Rafał Miłecki | 5ea597f | 2009-12-17 13:50:09 +0100 | [diff] [blame] | 109 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 110 | .set_memory_clock = NULL, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 111 | .get_pcie_lanes = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 112 | .set_pcie_lanes = NULL, |
| 113 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 114 | .set_surface_reg = r100_set_surface_reg, |
| 115 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 116 | .bandwidth_update = &r100_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 117 | .hpd_init = &r100_hpd_init, |
| 118 | .hpd_fini = &r100_hpd_fini, |
| 119 | .hpd_sense = &r100_hpd_sense, |
| 120 | .hpd_set_polarity = &r100_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 121 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | |
| 125 | /* |
| 126 | * r300,r350,rv350,rv380 |
| 127 | */ |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 128 | extern int r300_init(struct radeon_device *rdev); |
| 129 | extern void r300_fini(struct radeon_device *rdev); |
| 130 | extern int r300_suspend(struct radeon_device *rdev); |
| 131 | extern int r300_resume(struct radeon_device *rdev); |
| 132 | extern int r300_gpu_reset(struct radeon_device *rdev); |
| 133 | extern void r300_ring_start(struct radeon_device *rdev); |
| 134 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
| 135 | struct radeon_fence *fence); |
| 136 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
| 137 | extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| 138 | extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 139 | extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| 140 | extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 141 | extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 142 | extern int rv370_get_pcie_lanes(struct radeon_device *rdev); |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 143 | extern int r300_copy_dma(struct radeon_device *rdev, |
| 144 | uint64_t src_offset, |
| 145 | uint64_t dst_offset, |
| 146 | unsigned num_pages, |
| 147 | struct radeon_fence *fence); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 148 | static struct radeon_asic r300_asic = { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 149 | .init = &r300_init, |
Jerome Glisse | 207bf9e | 2009-09-30 15:35:32 +0200 | [diff] [blame] | 150 | .fini = &r300_fini, |
| 151 | .suspend = &r300_suspend, |
| 152 | .resume = &r300_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 153 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 154 | .gpu_reset = &r300_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 155 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| 156 | .gart_set_page = &r100_pci_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 157 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 158 | .ring_start = &r300_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 159 | .ring_test = &r100_ring_test, |
| 160 | .ring_ib_execute = &r100_ring_ib_execute, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | .irq_set = &r100_irq_set, |
| 162 | .irq_process = &r100_irq_process, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 163 | .get_vblank_counter = &r100_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 164 | .fence_ring_emit = &r300_fence_ring_emit, |
| 165 | .cs_parse = &r300_cs_parse, |
| 166 | .copy_blit = &r100_copy_blit, |
| 167 | .copy_dma = &r300_copy_dma, |
| 168 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 169 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 170 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
Rafał Miłecki | 5ea597f | 2009-12-17 13:50:09 +0100 | [diff] [blame] | 171 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 172 | .set_memory_clock = NULL, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 173 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 174 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 175 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 176 | .set_surface_reg = r100_set_surface_reg, |
| 177 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 178 | .bandwidth_update = &r100_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 179 | .hpd_init = &r100_hpd_init, |
| 180 | .hpd_fini = &r100_hpd_fini, |
| 181 | .hpd_sense = &r100_hpd_sense, |
| 182 | .hpd_set_polarity = &r100_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 183 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 184 | }; |
| 185 | |
| 186 | /* |
| 187 | * r420,r423,rv410 |
| 188 | */ |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 189 | extern int r420_init(struct radeon_device *rdev); |
| 190 | extern void r420_fini(struct radeon_device *rdev); |
| 191 | extern int r420_suspend(struct radeon_device *rdev); |
| 192 | extern int r420_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 193 | static struct radeon_asic r420_asic = { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 194 | .init = &r420_init, |
| 195 | .fini = &r420_fini, |
| 196 | .suspend = &r420_suspend, |
| 197 | .resume = &r420_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 198 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 199 | .gpu_reset = &r300_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 200 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 201 | .gart_set_page = &rv370_pcie_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 202 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 203 | .ring_start = &r300_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 204 | .ring_test = &r100_ring_test, |
| 205 | .ring_ib_execute = &r100_ring_ib_execute, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 206 | .irq_set = &r100_irq_set, |
| 207 | .irq_process = &r100_irq_process, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 208 | .get_vblank_counter = &r100_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 209 | .fence_ring_emit = &r300_fence_ring_emit, |
| 210 | .cs_parse = &r300_cs_parse, |
| 211 | .copy_blit = &r100_copy_blit, |
| 212 | .copy_dma = &r300_copy_dma, |
| 213 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 214 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 215 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 216 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 217 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 218 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 219 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 220 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 221 | .set_surface_reg = r100_set_surface_reg, |
| 222 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 223 | .bandwidth_update = &r100_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 224 | .hpd_init = &r100_hpd_init, |
| 225 | .hpd_fini = &r100_hpd_fini, |
| 226 | .hpd_sense = &r100_hpd_sense, |
| 227 | .hpd_set_polarity = &r100_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 228 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 229 | }; |
| 230 | |
| 231 | |
| 232 | /* |
| 233 | * rs400,rs480 |
| 234 | */ |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 235 | extern int rs400_init(struct radeon_device *rdev); |
| 236 | extern void rs400_fini(struct radeon_device *rdev); |
| 237 | extern int rs400_suspend(struct radeon_device *rdev); |
| 238 | extern int rs400_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| 240 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 241 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 242 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 243 | static struct radeon_asic rs400_asic = { |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 244 | .init = &rs400_init, |
| 245 | .fini = &rs400_fini, |
| 246 | .suspend = &rs400_suspend, |
| 247 | .resume = &rs400_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 248 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 249 | .gpu_reset = &r300_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 251 | .gart_set_page = &rs400_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 252 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 253 | .ring_start = &r300_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 254 | .ring_test = &r100_ring_test, |
| 255 | .ring_ib_execute = &r100_ring_ib_execute, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | .irq_set = &r100_irq_set, |
| 257 | .irq_process = &r100_irq_process, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 258 | .get_vblank_counter = &r100_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 259 | .fence_ring_emit = &r300_fence_ring_emit, |
| 260 | .cs_parse = &r300_cs_parse, |
| 261 | .copy_blit = &r100_copy_blit, |
| 262 | .copy_dma = &r300_copy_dma, |
| 263 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 264 | .get_engine_clock = &radeon_legacy_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | .set_engine_clock = &radeon_legacy_set_engine_clock, |
Rafał Miłecki | 5ea597f | 2009-12-17 13:50:09 +0100 | [diff] [blame] | 266 | .get_memory_clock = &radeon_legacy_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 267 | .set_memory_clock = NULL, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 268 | .get_pcie_lanes = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 269 | .set_pcie_lanes = NULL, |
| 270 | .set_clock_gating = &radeon_legacy_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 271 | .set_surface_reg = r100_set_surface_reg, |
| 272 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 273 | .bandwidth_update = &r100_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 274 | .hpd_init = &r100_hpd_init, |
| 275 | .hpd_fini = &r100_hpd_fini, |
| 276 | .hpd_sense = &r100_hpd_sense, |
| 277 | .hpd_set_polarity = &r100_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 278 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | |
| 282 | /* |
| 283 | * rs600. |
| 284 | */ |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 285 | extern int rs600_init(struct radeon_device *rdev); |
| 286 | extern void rs600_fini(struct radeon_device *rdev); |
| 287 | extern int rs600_suspend(struct radeon_device *rdev); |
| 288 | extern int rs600_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 289 | int rs600_irq_set(struct radeon_device *rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 290 | int rs600_irq_process(struct radeon_device *rdev); |
| 291 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 292 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| 293 | int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| 294 | uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 295 | void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 296 | void rs600_bandwidth_update(struct radeon_device *rdev); |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 297 | void rs600_hpd_init(struct radeon_device *rdev); |
| 298 | void rs600_hpd_fini(struct radeon_device *rdev); |
| 299 | bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 300 | void rs600_hpd_set_polarity(struct radeon_device *rdev, |
| 301 | enum radeon_hpd_id hpd); |
| 302 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | static struct radeon_asic rs600_asic = { |
Dave Airlie | 3f7dc91a | 2009-08-27 11:10:15 +1000 | [diff] [blame] | 304 | .init = &rs600_init, |
Jerome Glisse | c010f80 | 2009-09-30 22:09:06 +0200 | [diff] [blame] | 305 | .fini = &rs600_fini, |
| 306 | .suspend = &rs600_suspend, |
| 307 | .resume = &rs600_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 308 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 309 | .gpu_reset = &r300_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
| 311 | .gart_set_page = &rs600_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 312 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 313 | .ring_start = &r300_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 314 | .ring_test = &r100_ring_test, |
| 315 | .ring_ib_execute = &r100_ring_ib_execute, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 316 | .irq_set = &rs600_irq_set, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 317 | .irq_process = &rs600_irq_process, |
| 318 | .get_vblank_counter = &rs600_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 319 | .fence_ring_emit = &r300_fence_ring_emit, |
| 320 | .cs_parse = &r300_cs_parse, |
| 321 | .copy_blit = &r100_copy_blit, |
| 322 | .copy_dma = &r300_copy_dma, |
| 323 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 324 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 325 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 326 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 327 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 328 | .get_pcie_lanes = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 329 | .set_pcie_lanes = NULL, |
| 330 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 331 | .bandwidth_update = &rs600_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 332 | .hpd_init = &rs600_hpd_init, |
| 333 | .hpd_fini = &rs600_hpd_fini, |
| 334 | .hpd_sense = &rs600_hpd_sense, |
| 335 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 336 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | |
| 340 | /* |
| 341 | * rs690,rs740 |
| 342 | */ |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 343 | int rs690_init(struct radeon_device *rdev); |
| 344 | void rs690_fini(struct radeon_device *rdev); |
| 345 | int rs690_resume(struct radeon_device *rdev); |
| 346 | int rs690_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 347 | uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 348 | void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 349 | void rs690_bandwidth_update(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 350 | static struct radeon_asic rs690_asic = { |
Jerome Glisse | 3bc6853 | 2009-10-01 09:39:24 +0200 | [diff] [blame] | 351 | .init = &rs690_init, |
| 352 | .fini = &rs690_fini, |
| 353 | .suspend = &rs690_suspend, |
| 354 | .resume = &rs690_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 355 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 356 | .gpu_reset = &r300_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 357 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
| 358 | .gart_set_page = &rs400_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 359 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 360 | .ring_start = &r300_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 361 | .ring_test = &r100_ring_test, |
| 362 | .ring_ib_execute = &r100_ring_ib_execute, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 363 | .irq_set = &rs600_irq_set, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 364 | .irq_process = &rs600_irq_process, |
| 365 | .get_vblank_counter = &rs600_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 366 | .fence_ring_emit = &r300_fence_ring_emit, |
| 367 | .cs_parse = &r300_cs_parse, |
| 368 | .copy_blit = &r100_copy_blit, |
| 369 | .copy_dma = &r300_copy_dma, |
| 370 | .copy = &r300_copy_dma, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 371 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 372 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 373 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 374 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 375 | .get_pcie_lanes = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 376 | .set_pcie_lanes = NULL, |
| 377 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 378 | .set_surface_reg = r100_set_surface_reg, |
| 379 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 380 | .bandwidth_update = &rs690_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 381 | .hpd_init = &rs600_hpd_init, |
| 382 | .hpd_fini = &rs600_hpd_fini, |
| 383 | .hpd_sense = &rs600_hpd_sense, |
| 384 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 385 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 386 | }; |
| 387 | |
| 388 | |
| 389 | /* |
| 390 | * rv515 |
| 391 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 392 | int rv515_init(struct radeon_device *rdev); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 393 | void rv515_fini(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 394 | int rv515_gpu_reset(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 395 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| 396 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 397 | void rv515_ring_start(struct radeon_device *rdev); |
| 398 | uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| 399 | void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 400 | void rv515_bandwidth_update(struct radeon_device *rdev); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 401 | int rv515_resume(struct radeon_device *rdev); |
| 402 | int rv515_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 403 | static struct radeon_asic rv515_asic = { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 404 | .init = &rv515_init, |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 405 | .fini = &rv515_fini, |
| 406 | .suspend = &rv515_suspend, |
| 407 | .resume = &rv515_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 408 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 409 | .gpu_reset = &rv515_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 410 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 411 | .gart_set_page = &rv370_pcie_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 412 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 413 | .ring_start = &rv515_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 414 | .ring_test = &r100_ring_test, |
| 415 | .ring_ib_execute = &r100_ring_ib_execute, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 416 | .irq_set = &rs600_irq_set, |
| 417 | .irq_process = &rs600_irq_process, |
| 418 | .get_vblank_counter = &rs600_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 419 | .fence_ring_emit = &r300_fence_ring_emit, |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 420 | .cs_parse = &r300_cs_parse, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 421 | .copy_blit = &r100_copy_blit, |
| 422 | .copy_dma = &r300_copy_dma, |
| 423 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 424 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 425 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 426 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 427 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 428 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 429 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 430 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 431 | .set_surface_reg = r100_set_surface_reg, |
| 432 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 433 | .bandwidth_update = &rv515_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 434 | .hpd_init = &rs600_hpd_init, |
| 435 | .hpd_fini = &rs600_hpd_fini, |
| 436 | .hpd_sense = &rs600_hpd_sense, |
| 437 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 438 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 439 | }; |
| 440 | |
| 441 | |
| 442 | /* |
| 443 | * r520,rv530,rv560,rv570,r580 |
| 444 | */ |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 445 | int r520_init(struct radeon_device *rdev); |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 446 | int r520_resume(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 447 | static struct radeon_asic r520_asic = { |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 448 | .init = &r520_init, |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 449 | .fini = &rv515_fini, |
| 450 | .suspend = &rv515_suspend, |
| 451 | .resume = &r520_resume, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 452 | .vga_set_state = &r100_vga_set_state, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 453 | .gpu_reset = &rv515_gpu_reset, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 454 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| 455 | .gart_set_page = &rv370_pcie_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 456 | .cp_commit = &r100_cp_commit, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 457 | .ring_start = &rv515_ring_start, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 458 | .ring_test = &r100_ring_test, |
| 459 | .ring_ib_execute = &r100_ring_ib_execute, |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 460 | .irq_set = &rs600_irq_set, |
| 461 | .irq_process = &rs600_irq_process, |
| 462 | .get_vblank_counter = &rs600_get_vblank_counter, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 463 | .fence_ring_emit = &r300_fence_ring_emit, |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 464 | .cs_parse = &r300_cs_parse, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 465 | .copy_blit = &r100_copy_blit, |
| 466 | .copy_dma = &r300_copy_dma, |
| 467 | .copy = &r100_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 468 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 469 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 470 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 471 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 472 | .get_pcie_lanes = &rv370_get_pcie_lanes, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 473 | .set_pcie_lanes = &rv370_set_pcie_lanes, |
| 474 | .set_clock_gating = &radeon_atom_set_clock_gating, |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 475 | .set_surface_reg = r100_set_surface_reg, |
| 476 | .clear_surface_reg = r100_clear_surface_reg, |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 477 | .bandwidth_update = &rv515_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 478 | .hpd_init = &rs600_hpd_init, |
| 479 | .hpd_fini = &rs600_hpd_fini, |
| 480 | .hpd_sense = &rs600_hpd_sense, |
| 481 | .hpd_set_polarity = &rs600_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 482 | .ioctl_wait_idle = NULL, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 483 | }; |
| 484 | |
| 485 | /* |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 486 | * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 487 | */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 488 | int r600_init(struct radeon_device *rdev); |
| 489 | void r600_fini(struct radeon_device *rdev); |
| 490 | int r600_suspend(struct radeon_device *rdev); |
| 491 | int r600_resume(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 492 | void r600_vga_set_state(struct radeon_device *rdev, bool state); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 493 | int r600_wb_init(struct radeon_device *rdev); |
| 494 | void r600_wb_fini(struct radeon_device *rdev); |
| 495 | void r600_cp_commit(struct radeon_device *rdev); |
| 496 | void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 497 | uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| 498 | void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 499 | int r600_cs_parse(struct radeon_cs_parser *p); |
| 500 | void r600_fence_ring_emit(struct radeon_device *rdev, |
| 501 | struct radeon_fence *fence); |
| 502 | int r600_copy_dma(struct radeon_device *rdev, |
| 503 | uint64_t src_offset, |
| 504 | uint64_t dst_offset, |
| 505 | unsigned num_pages, |
| 506 | struct radeon_fence *fence); |
| 507 | int r600_irq_process(struct radeon_device *rdev); |
| 508 | int r600_irq_set(struct radeon_device *rdev); |
| 509 | int r600_gpu_reset(struct radeon_device *rdev); |
| 510 | int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| 511 | uint32_t tiling_flags, uint32_t pitch, |
| 512 | uint32_t offset, uint32_t obj_size); |
| 513 | int r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
| 514 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 515 | int r600_ring_test(struct radeon_device *rdev); |
| 516 | int r600_copy_blit(struct radeon_device *rdev, |
| 517 | uint64_t src_offset, uint64_t dst_offset, |
| 518 | unsigned num_pages, struct radeon_fence *fence); |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 519 | void r600_hpd_init(struct radeon_device *rdev); |
| 520 | void r600_hpd_fini(struct radeon_device *rdev); |
| 521 | bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 522 | void r600_hpd_set_polarity(struct radeon_device *rdev, |
| 523 | enum radeon_hpd_id hpd); |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 524 | extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 525 | |
| 526 | static struct radeon_asic r600_asic = { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 527 | .init = &r600_init, |
| 528 | .fini = &r600_fini, |
| 529 | .suspend = &r600_suspend, |
| 530 | .resume = &r600_resume, |
| 531 | .cp_commit = &r600_cp_commit, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 532 | .vga_set_state = &r600_vga_set_state, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 533 | .gpu_reset = &r600_gpu_reset, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 534 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| 535 | .gart_set_page = &rs600_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 536 | .ring_test = &r600_ring_test, |
| 537 | .ring_ib_execute = &r600_ring_ib_execute, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 538 | .irq_set = &r600_irq_set, |
| 539 | .irq_process = &r600_irq_process, |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 540 | .get_vblank_counter = &rs600_get_vblank_counter, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 541 | .fence_ring_emit = &r600_fence_ring_emit, |
| 542 | .cs_parse = &r600_cs_parse, |
| 543 | .copy_blit = &r600_copy_blit, |
| 544 | .copy_dma = &r600_copy_blit, |
Alex Deucher | a381287 | 2009-09-10 15:54:35 -0400 | [diff] [blame] | 545 | .copy = &r600_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 546 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 547 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 548 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 549 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 550 | .get_pcie_lanes = NULL, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 551 | .set_pcie_lanes = NULL, |
Alex Deucher | 6d7f2d8 | 2010-02-05 00:55:32 -0500 | [diff] [blame] | 552 | .set_clock_gating = NULL, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 553 | .set_surface_reg = r600_set_surface_reg, |
| 554 | .clear_surface_reg = r600_clear_surface_reg, |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 555 | .bandwidth_update = &rv515_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 556 | .hpd_init = &r600_hpd_init, |
| 557 | .hpd_fini = &r600_hpd_fini, |
| 558 | .hpd_sense = &r600_hpd_sense, |
| 559 | .hpd_set_polarity = &r600_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 560 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 561 | }; |
| 562 | |
| 563 | /* |
| 564 | * rv770,rv730,rv710,rv740 |
| 565 | */ |
| 566 | int rv770_init(struct radeon_device *rdev); |
| 567 | void rv770_fini(struct radeon_device *rdev); |
| 568 | int rv770_suspend(struct radeon_device *rdev); |
| 569 | int rv770_resume(struct radeon_device *rdev); |
| 570 | int rv770_gpu_reset(struct radeon_device *rdev); |
| 571 | |
| 572 | static struct radeon_asic rv770_asic = { |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 573 | .init = &rv770_init, |
| 574 | .fini = &rv770_fini, |
| 575 | .suspend = &rv770_suspend, |
| 576 | .resume = &rv770_resume, |
| 577 | .cp_commit = &r600_cp_commit, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 578 | .gpu_reset = &rv770_gpu_reset, |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 579 | .vga_set_state = &r600_vga_set_state, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 580 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| 581 | .gart_set_page = &rs600_gart_set_page, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 582 | .ring_test = &r600_ring_test, |
| 583 | .ring_ib_execute = &r600_ring_ib_execute, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 584 | .irq_set = &r600_irq_set, |
| 585 | .irq_process = &r600_irq_process, |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 586 | .get_vblank_counter = &rs600_get_vblank_counter, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 587 | .fence_ring_emit = &r600_fence_ring_emit, |
| 588 | .cs_parse = &r600_cs_parse, |
| 589 | .copy_blit = &r600_copy_blit, |
| 590 | .copy_dma = &r600_copy_blit, |
Alex Deucher | a381287 | 2009-09-10 15:54:35 -0400 | [diff] [blame] | 591 | .copy = &r600_copy_blit, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 592 | .get_engine_clock = &radeon_atom_get_engine_clock, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 593 | .set_engine_clock = &radeon_atom_set_engine_clock, |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 594 | .get_memory_clock = &radeon_atom_get_memory_clock, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 595 | .set_memory_clock = &radeon_atom_set_memory_clock, |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 596 | .get_pcie_lanes = NULL, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 597 | .set_pcie_lanes = NULL, |
| 598 | .set_clock_gating = &radeon_atom_set_clock_gating, |
| 599 | .set_surface_reg = r600_set_surface_reg, |
| 600 | .clear_surface_reg = r600_clear_surface_reg, |
Jerome Glisse | f0ed1f6 | 2009-09-28 20:39:19 +0200 | [diff] [blame] | 601 | .bandwidth_update = &rv515_bandwidth_update, |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 602 | .hpd_init = &r600_hpd_init, |
| 603 | .hpd_fini = &r600_hpd_fini, |
| 604 | .hpd_sense = &r600_hpd_sense, |
| 605 | .hpd_set_polarity = &r600_hpd_set_polarity, |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 606 | .ioctl_wait_idle = r600_ioctl_wait_idle, |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 607 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 608 | |
| 609 | #endif |