Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1 | /* |
| 2 | * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx |
| 3 | * |
| 4 | * Copyright (C) 2011 Nokia Corporation |
| 5 | * Paul Walmsley |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #include <plat/omap_hwmod.h> |
| 12 | #include <plat/serial.h> |
Tony Lindgren | 4b25408 | 2012-08-30 15:37:24 -0700 | [diff] [blame] | 13 | #include <linux/platform_data/gpio-omap.h> |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 14 | #include <plat/dma.h> |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 15 | #include <plat/dmtimer.h> |
| 16 | #include <plat/mcspi.h> |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 17 | |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 18 | #include "omap_hwmod_common_data.h" |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 19 | #include "cm-regbits-24xx.h" |
| 20 | #include "prm-regbits-24xx.h" |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 21 | #include "wd_timer.h" |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 22 | |
| 23 | struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = { |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 24 | { .irq = 48 + OMAP_INTC_START, }, |
| 25 | { .irq = -1 }, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 26 | }; |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 27 | |
| 28 | struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = { |
| 29 | { .name = "dispc", .dma_req = 5 }, |
| 30 | { .dma_req = -1 } |
| 31 | }; |
Tomi Valkeinen | 1ac6d46 | 2012-01-23 14:15:28 +0200 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * 'dispc' class |
| 35 | * display controller |
| 36 | */ |
| 37 | |
| 38 | static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { |
| 39 | .rev_offs = 0x0000, |
| 40 | .sysc_offs = 0x0010, |
| 41 | .syss_offs = 0x0014, |
| 42 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
| 43 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 44 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 45 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 46 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 47 | }; |
| 48 | |
| 49 | struct omap_hwmod_class omap2_dispc_hwmod_class = { |
| 50 | .name = "dispc", |
| 51 | .sysc = &omap2_dispc_sysc, |
| 52 | }; |
| 53 | |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 54 | /* OMAP2xxx Timer Common */ |
| 55 | static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { |
| 56 | .rev_offs = 0x0000, |
| 57 | .sysc_offs = 0x0010, |
| 58 | .syss_offs = 0x0014, |
| 59 | .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
| 60 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 61 | SYSC_HAS_AUTOIDLE), |
| 62 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 63 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 64 | }; |
| 65 | |
| 66 | struct omap_hwmod_class omap2xxx_timer_hwmod_class = { |
| 67 | .name = "timer", |
| 68 | .sysc = &omap2xxx_timer_sysc, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 69 | }; |
| 70 | |
| 71 | /* |
| 72 | * 'wd_timer' class |
| 73 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 74 | * overflow condition |
| 75 | */ |
| 76 | |
| 77 | static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = { |
| 78 | .rev_offs = 0x0000, |
| 79 | .sysc_offs = 0x0010, |
| 80 | .syss_offs = 0x0014, |
| 81 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
| 82 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 83 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 84 | }; |
| 85 | |
| 86 | struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { |
| 87 | .name = "wd_timer", |
| 88 | .sysc = &omap2xxx_wd_timer_sysc, |
Kevin Hilman | 414e412 | 2012-05-08 11:34:30 -0600 | [diff] [blame] | 89 | .pre_shutdown = &omap2_wd_timer_disable, |
| 90 | .reset = &omap2_wd_timer_reset, |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | /* |
| 94 | * 'gpio' class |
| 95 | * general purpose io module |
| 96 | */ |
| 97 | static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = { |
| 98 | .rev_offs = 0x0000, |
| 99 | .sysc_offs = 0x0010, |
| 100 | .syss_offs = 0x0014, |
| 101 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 102 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 103 | SYSS_HAS_RESET_STATUS), |
| 104 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 105 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 106 | }; |
| 107 | |
| 108 | struct omap_hwmod_class omap2xxx_gpio_hwmod_class = { |
| 109 | .name = "gpio", |
| 110 | .sysc = &omap2xxx_gpio_sysc, |
| 111 | .rev = 0, |
| 112 | }; |
| 113 | |
| 114 | /* system dma */ |
| 115 | static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = { |
| 116 | .rev_offs = 0x0000, |
| 117 | .sysc_offs = 0x002c, |
| 118 | .syss_offs = 0x0028, |
| 119 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE | |
| 120 | SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE | |
| 121 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 122 | .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 123 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 124 | }; |
| 125 | |
| 126 | struct omap_hwmod_class omap2xxx_dma_hwmod_class = { |
| 127 | .name = "dma", |
| 128 | .sysc = &omap2xxx_dma_sysc, |
| 129 | }; |
| 130 | |
| 131 | /* |
| 132 | * 'mailbox' class |
| 133 | * mailbox module allowing communication between the on-chip processors |
| 134 | * using a queued mailbox-interrupt mechanism. |
| 135 | */ |
| 136 | |
| 137 | static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = { |
| 138 | .rev_offs = 0x000, |
| 139 | .sysc_offs = 0x010, |
| 140 | .syss_offs = 0x014, |
| 141 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 142 | SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
| 143 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 144 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 145 | }; |
| 146 | |
| 147 | struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = { |
| 148 | .name = "mailbox", |
| 149 | .sysc = &omap2xxx_mailbox_sysc, |
| 150 | }; |
| 151 | |
| 152 | /* |
| 153 | * 'mcspi' class |
| 154 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 155 | * bus |
| 156 | */ |
| 157 | |
| 158 | static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { |
| 159 | .rev_offs = 0x0000, |
| 160 | .sysc_offs = 0x0010, |
| 161 | .syss_offs = 0x0014, |
| 162 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 163 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 164 | SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
| 165 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 166 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 167 | }; |
| 168 | |
| 169 | struct omap_hwmod_class omap2xxx_mcspi_class = { |
| 170 | .name = "mcspi", |
| 171 | .sysc = &omap2xxx_mcspi_sysc, |
| 172 | .rev = OMAP2_MCSPI_REV, |
| 173 | }; |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 174 | |
| 175 | /* |
Afzal Mohammed | 49484a6 | 2012-09-23 17:28:24 -0600 | [diff] [blame] | 176 | * 'gpmc' class |
| 177 | * general purpose memory controller |
| 178 | */ |
| 179 | |
| 180 | static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = { |
| 181 | .rev_offs = 0x0000, |
| 182 | .sysc_offs = 0x0010, |
| 183 | .syss_offs = 0x0014, |
| 184 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | |
| 185 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 186 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 187 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 188 | }; |
| 189 | |
| 190 | static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = { |
| 191 | .name = "gpmc", |
| 192 | .sysc = &omap2xxx_gpmc_sysc, |
| 193 | }; |
| 194 | |
| 195 | /* |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 196 | * IP blocks |
| 197 | */ |
| 198 | |
| 199 | /* L3 */ |
| 200 | struct omap_hwmod omap2xxx_l3_main_hwmod = { |
| 201 | .name = "l3_main", |
| 202 | .class = &l3_hwmod_class, |
| 203 | .flags = HWMOD_NO_IDLEST, |
| 204 | }; |
| 205 | |
| 206 | /* L4 CORE */ |
| 207 | struct omap_hwmod omap2xxx_l4_core_hwmod = { |
| 208 | .name = "l4_core", |
| 209 | .class = &l4_hwmod_class, |
| 210 | .flags = HWMOD_NO_IDLEST, |
| 211 | }; |
| 212 | |
| 213 | /* L4 WKUP */ |
| 214 | struct omap_hwmod omap2xxx_l4_wkup_hwmod = { |
| 215 | .name = "l4_wkup", |
| 216 | .class = &l4_hwmod_class, |
| 217 | .flags = HWMOD_NO_IDLEST, |
| 218 | }; |
| 219 | |
| 220 | /* MPU */ |
| 221 | struct omap_hwmod omap2xxx_mpu_hwmod = { |
| 222 | .name = "mpu", |
| 223 | .class = &mpu_hwmod_class, |
| 224 | .main_clk = "mpu_ck", |
| 225 | }; |
| 226 | |
| 227 | /* IVA2 */ |
| 228 | struct omap_hwmod omap2xxx_iva_hwmod = { |
| 229 | .name = "iva", |
| 230 | .class = &iva_hwmod_class, |
| 231 | }; |
| 232 | |
| 233 | /* always-on timers dev attribute */ |
| 234 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { |
| 235 | .timer_capability = OMAP_TIMER_ALWON, |
| 236 | }; |
| 237 | |
| 238 | /* pwm timers dev attribute */ |
| 239 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { |
| 240 | .timer_capability = OMAP_TIMER_HAS_PWM, |
| 241 | }; |
| 242 | |
| 243 | /* timer1 */ |
| 244 | |
| 245 | struct omap_hwmod omap2xxx_timer1_hwmod = { |
| 246 | .name = "timer1", |
| 247 | .mpu_irqs = omap2_timer1_mpu_irqs, |
| 248 | .main_clk = "gpt1_fck", |
| 249 | .prcm = { |
| 250 | .omap2 = { |
| 251 | .prcm_reg_id = 1, |
| 252 | .module_bit = OMAP24XX_EN_GPT1_SHIFT, |
| 253 | .module_offs = WKUP_MOD, |
| 254 | .idlest_reg_id = 1, |
| 255 | .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT, |
| 256 | }, |
| 257 | }, |
| 258 | .dev_attr = &capability_alwon_dev_attr, |
| 259 | .class = &omap2xxx_timer_hwmod_class, |
| 260 | }; |
| 261 | |
| 262 | /* timer2 */ |
| 263 | |
| 264 | struct omap_hwmod omap2xxx_timer2_hwmod = { |
| 265 | .name = "timer2", |
| 266 | .mpu_irqs = omap2_timer2_mpu_irqs, |
| 267 | .main_clk = "gpt2_fck", |
| 268 | .prcm = { |
| 269 | .omap2 = { |
| 270 | .prcm_reg_id = 1, |
| 271 | .module_bit = OMAP24XX_EN_GPT2_SHIFT, |
| 272 | .module_offs = CORE_MOD, |
| 273 | .idlest_reg_id = 1, |
| 274 | .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT, |
| 275 | }, |
| 276 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 277 | .class = &omap2xxx_timer_hwmod_class, |
| 278 | }; |
| 279 | |
| 280 | /* timer3 */ |
| 281 | |
| 282 | struct omap_hwmod omap2xxx_timer3_hwmod = { |
| 283 | .name = "timer3", |
| 284 | .mpu_irqs = omap2_timer3_mpu_irqs, |
| 285 | .main_clk = "gpt3_fck", |
| 286 | .prcm = { |
| 287 | .omap2 = { |
| 288 | .prcm_reg_id = 1, |
| 289 | .module_bit = OMAP24XX_EN_GPT3_SHIFT, |
| 290 | .module_offs = CORE_MOD, |
| 291 | .idlest_reg_id = 1, |
| 292 | .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, |
| 293 | }, |
| 294 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 295 | .class = &omap2xxx_timer_hwmod_class, |
| 296 | }; |
| 297 | |
| 298 | /* timer4 */ |
| 299 | |
| 300 | struct omap_hwmod omap2xxx_timer4_hwmod = { |
| 301 | .name = "timer4", |
| 302 | .mpu_irqs = omap2_timer4_mpu_irqs, |
| 303 | .main_clk = "gpt4_fck", |
| 304 | .prcm = { |
| 305 | .omap2 = { |
| 306 | .prcm_reg_id = 1, |
| 307 | .module_bit = OMAP24XX_EN_GPT4_SHIFT, |
| 308 | .module_offs = CORE_MOD, |
| 309 | .idlest_reg_id = 1, |
| 310 | .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, |
| 311 | }, |
| 312 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 313 | .class = &omap2xxx_timer_hwmod_class, |
| 314 | }; |
| 315 | |
| 316 | /* timer5 */ |
| 317 | |
| 318 | struct omap_hwmod omap2xxx_timer5_hwmod = { |
| 319 | .name = "timer5", |
| 320 | .mpu_irqs = omap2_timer5_mpu_irqs, |
| 321 | .main_clk = "gpt5_fck", |
| 322 | .prcm = { |
| 323 | .omap2 = { |
| 324 | .prcm_reg_id = 1, |
| 325 | .module_bit = OMAP24XX_EN_GPT5_SHIFT, |
| 326 | .module_offs = CORE_MOD, |
| 327 | .idlest_reg_id = 1, |
| 328 | .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, |
| 329 | }, |
| 330 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 331 | .class = &omap2xxx_timer_hwmod_class, |
| 332 | }; |
| 333 | |
| 334 | /* timer6 */ |
| 335 | |
| 336 | struct omap_hwmod omap2xxx_timer6_hwmod = { |
| 337 | .name = "timer6", |
| 338 | .mpu_irqs = omap2_timer6_mpu_irqs, |
| 339 | .main_clk = "gpt6_fck", |
| 340 | .prcm = { |
| 341 | .omap2 = { |
| 342 | .prcm_reg_id = 1, |
| 343 | .module_bit = OMAP24XX_EN_GPT6_SHIFT, |
| 344 | .module_offs = CORE_MOD, |
| 345 | .idlest_reg_id = 1, |
| 346 | .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, |
| 347 | }, |
| 348 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 349 | .class = &omap2xxx_timer_hwmod_class, |
| 350 | }; |
| 351 | |
| 352 | /* timer7 */ |
| 353 | |
| 354 | struct omap_hwmod omap2xxx_timer7_hwmod = { |
| 355 | .name = "timer7", |
| 356 | .mpu_irqs = omap2_timer7_mpu_irqs, |
| 357 | .main_clk = "gpt7_fck", |
| 358 | .prcm = { |
| 359 | .omap2 = { |
| 360 | .prcm_reg_id = 1, |
| 361 | .module_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 362 | .module_offs = CORE_MOD, |
| 363 | .idlest_reg_id = 1, |
| 364 | .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, |
| 365 | }, |
| 366 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 367 | .class = &omap2xxx_timer_hwmod_class, |
| 368 | }; |
| 369 | |
| 370 | /* timer8 */ |
| 371 | |
| 372 | struct omap_hwmod omap2xxx_timer8_hwmod = { |
| 373 | .name = "timer8", |
| 374 | .mpu_irqs = omap2_timer8_mpu_irqs, |
| 375 | .main_clk = "gpt8_fck", |
| 376 | .prcm = { |
| 377 | .omap2 = { |
| 378 | .prcm_reg_id = 1, |
| 379 | .module_bit = OMAP24XX_EN_GPT8_SHIFT, |
| 380 | .module_offs = CORE_MOD, |
| 381 | .idlest_reg_id = 1, |
| 382 | .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, |
| 383 | }, |
| 384 | }, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 385 | .class = &omap2xxx_timer_hwmod_class, |
| 386 | }; |
| 387 | |
| 388 | /* timer9 */ |
| 389 | |
| 390 | struct omap_hwmod omap2xxx_timer9_hwmod = { |
| 391 | .name = "timer9", |
| 392 | .mpu_irqs = omap2_timer9_mpu_irqs, |
| 393 | .main_clk = "gpt9_fck", |
| 394 | .prcm = { |
| 395 | .omap2 = { |
| 396 | .prcm_reg_id = 1, |
| 397 | .module_bit = OMAP24XX_EN_GPT9_SHIFT, |
| 398 | .module_offs = CORE_MOD, |
| 399 | .idlest_reg_id = 1, |
| 400 | .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, |
| 401 | }, |
| 402 | }, |
| 403 | .dev_attr = &capability_pwm_dev_attr, |
| 404 | .class = &omap2xxx_timer_hwmod_class, |
| 405 | }; |
| 406 | |
| 407 | /* timer10 */ |
| 408 | |
| 409 | struct omap_hwmod omap2xxx_timer10_hwmod = { |
| 410 | .name = "timer10", |
| 411 | .mpu_irqs = omap2_timer10_mpu_irqs, |
| 412 | .main_clk = "gpt10_fck", |
| 413 | .prcm = { |
| 414 | .omap2 = { |
| 415 | .prcm_reg_id = 1, |
| 416 | .module_bit = OMAP24XX_EN_GPT10_SHIFT, |
| 417 | .module_offs = CORE_MOD, |
| 418 | .idlest_reg_id = 1, |
| 419 | .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, |
| 420 | }, |
| 421 | }, |
| 422 | .dev_attr = &capability_pwm_dev_attr, |
| 423 | .class = &omap2xxx_timer_hwmod_class, |
| 424 | }; |
| 425 | |
| 426 | /* timer11 */ |
| 427 | |
| 428 | struct omap_hwmod omap2xxx_timer11_hwmod = { |
| 429 | .name = "timer11", |
| 430 | .mpu_irqs = omap2_timer11_mpu_irqs, |
| 431 | .main_clk = "gpt11_fck", |
| 432 | .prcm = { |
| 433 | .omap2 = { |
| 434 | .prcm_reg_id = 1, |
| 435 | .module_bit = OMAP24XX_EN_GPT11_SHIFT, |
| 436 | .module_offs = CORE_MOD, |
| 437 | .idlest_reg_id = 1, |
| 438 | .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, |
| 439 | }, |
| 440 | }, |
| 441 | .dev_attr = &capability_pwm_dev_attr, |
| 442 | .class = &omap2xxx_timer_hwmod_class, |
| 443 | }; |
| 444 | |
| 445 | /* timer12 */ |
| 446 | |
| 447 | struct omap_hwmod omap2xxx_timer12_hwmod = { |
| 448 | .name = "timer12", |
| 449 | .mpu_irqs = omap2xxx_timer12_mpu_irqs, |
| 450 | .main_clk = "gpt12_fck", |
| 451 | .prcm = { |
| 452 | .omap2 = { |
| 453 | .prcm_reg_id = 1, |
| 454 | .module_bit = OMAP24XX_EN_GPT12_SHIFT, |
| 455 | .module_offs = CORE_MOD, |
| 456 | .idlest_reg_id = 1, |
| 457 | .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, |
| 458 | }, |
| 459 | }, |
| 460 | .dev_attr = &capability_pwm_dev_attr, |
| 461 | .class = &omap2xxx_timer_hwmod_class, |
| 462 | }; |
| 463 | |
| 464 | /* wd_timer2 */ |
| 465 | struct omap_hwmod omap2xxx_wd_timer2_hwmod = { |
| 466 | .name = "wd_timer2", |
| 467 | .class = &omap2xxx_wd_timer_hwmod_class, |
| 468 | .main_clk = "mpu_wdt_fck", |
| 469 | .prcm = { |
| 470 | .omap2 = { |
| 471 | .prcm_reg_id = 1, |
| 472 | .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| 473 | .module_offs = WKUP_MOD, |
| 474 | .idlest_reg_id = 1, |
| 475 | .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
| 476 | }, |
| 477 | }, |
| 478 | }; |
| 479 | |
| 480 | /* UART1 */ |
| 481 | |
| 482 | struct omap_hwmod omap2xxx_uart1_hwmod = { |
| 483 | .name = "uart1", |
| 484 | .mpu_irqs = omap2_uart1_mpu_irqs, |
| 485 | .sdma_reqs = omap2_uart1_sdma_reqs, |
| 486 | .main_clk = "uart1_fck", |
| 487 | .prcm = { |
| 488 | .omap2 = { |
| 489 | .module_offs = CORE_MOD, |
| 490 | .prcm_reg_id = 1, |
| 491 | .module_bit = OMAP24XX_EN_UART1_SHIFT, |
| 492 | .idlest_reg_id = 1, |
| 493 | .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
| 494 | }, |
| 495 | }, |
| 496 | .class = &omap2_uart_class, |
| 497 | }; |
| 498 | |
| 499 | /* UART2 */ |
| 500 | |
| 501 | struct omap_hwmod omap2xxx_uart2_hwmod = { |
| 502 | .name = "uart2", |
| 503 | .mpu_irqs = omap2_uart2_mpu_irqs, |
| 504 | .sdma_reqs = omap2_uart2_sdma_reqs, |
| 505 | .main_clk = "uart2_fck", |
| 506 | .prcm = { |
| 507 | .omap2 = { |
| 508 | .module_offs = CORE_MOD, |
| 509 | .prcm_reg_id = 1, |
| 510 | .module_bit = OMAP24XX_EN_UART2_SHIFT, |
| 511 | .idlest_reg_id = 1, |
| 512 | .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
| 513 | }, |
| 514 | }, |
| 515 | .class = &omap2_uart_class, |
| 516 | }; |
| 517 | |
| 518 | /* UART3 */ |
| 519 | |
| 520 | struct omap_hwmod omap2xxx_uart3_hwmod = { |
| 521 | .name = "uart3", |
| 522 | .mpu_irqs = omap2_uart3_mpu_irqs, |
| 523 | .sdma_reqs = omap2_uart3_sdma_reqs, |
| 524 | .main_clk = "uart3_fck", |
| 525 | .prcm = { |
| 526 | .omap2 = { |
| 527 | .module_offs = CORE_MOD, |
| 528 | .prcm_reg_id = 2, |
| 529 | .module_bit = OMAP24XX_EN_UART3_SHIFT, |
| 530 | .idlest_reg_id = 2, |
| 531 | .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
| 532 | }, |
| 533 | }, |
| 534 | .class = &omap2_uart_class, |
| 535 | }; |
| 536 | |
| 537 | /* dss */ |
| 538 | |
| 539 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
| 540 | /* |
| 541 | * The DSS HW needs all DSS clocks enabled during reset. The dss_core |
| 542 | * driver does not use these clocks. |
| 543 | */ |
| 544 | { .role = "tv_clk", .clk = "dss_54m_fck" }, |
| 545 | { .role = "sys_clk", .clk = "dss2_fck" }, |
| 546 | }; |
| 547 | |
| 548 | struct omap_hwmod omap2xxx_dss_core_hwmod = { |
| 549 | .name = "dss_core", |
| 550 | .class = &omap2_dss_hwmod_class, |
| 551 | .main_clk = "dss1_fck", /* instead of dss_fck */ |
| 552 | .sdma_reqs = omap2xxx_dss_sdma_chs, |
| 553 | .prcm = { |
| 554 | .omap2 = { |
| 555 | .prcm_reg_id = 1, |
| 556 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 557 | .module_offs = CORE_MOD, |
| 558 | .idlest_reg_id = 1, |
| 559 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 560 | }, |
| 561 | }, |
| 562 | .opt_clks = dss_opt_clks, |
| 563 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
| 564 | .flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 565 | }; |
| 566 | |
| 567 | struct omap_hwmod omap2xxx_dss_dispc_hwmod = { |
| 568 | .name = "dss_dispc", |
| 569 | .class = &omap2_dispc_hwmod_class, |
| 570 | .mpu_irqs = omap2_dispc_irqs, |
| 571 | .main_clk = "dss1_fck", |
| 572 | .prcm = { |
| 573 | .omap2 = { |
| 574 | .prcm_reg_id = 1, |
| 575 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 576 | .module_offs = CORE_MOD, |
| 577 | .idlest_reg_id = 1, |
| 578 | .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT, |
| 579 | }, |
| 580 | }, |
| 581 | .flags = HWMOD_NO_IDLEST, |
| 582 | .dev_attr = &omap2_3_dss_dispc_dev_attr |
| 583 | }; |
| 584 | |
| 585 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
| 586 | { .role = "ick", .clk = "dss_ick" }, |
| 587 | }; |
| 588 | |
| 589 | struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { |
| 590 | .name = "dss_rfbi", |
| 591 | .class = &omap2_rfbi_hwmod_class, |
| 592 | .main_clk = "dss1_fck", |
| 593 | .prcm = { |
| 594 | .omap2 = { |
| 595 | .prcm_reg_id = 1, |
| 596 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 597 | .module_offs = CORE_MOD, |
| 598 | }, |
| 599 | }, |
| 600 | .opt_clks = dss_rfbi_opt_clks, |
| 601 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), |
| 602 | .flags = HWMOD_NO_IDLEST, |
| 603 | }; |
| 604 | |
| 605 | struct omap_hwmod omap2xxx_dss_venc_hwmod = { |
| 606 | .name = "dss_venc", |
| 607 | .class = &omap2_venc_hwmod_class, |
| 608 | .main_clk = "dss_54m_fck", |
| 609 | .prcm = { |
| 610 | .omap2 = { |
| 611 | .prcm_reg_id = 1, |
| 612 | .module_bit = OMAP24XX_EN_DSS1_SHIFT, |
| 613 | .module_offs = CORE_MOD, |
| 614 | }, |
| 615 | }, |
| 616 | .flags = HWMOD_NO_IDLEST, |
| 617 | }; |
| 618 | |
| 619 | /* gpio dev_attr */ |
| 620 | struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = { |
| 621 | .bank_width = 32, |
| 622 | .dbck_flag = false, |
| 623 | }; |
| 624 | |
| 625 | /* gpio1 */ |
| 626 | struct omap_hwmod omap2xxx_gpio1_hwmod = { |
| 627 | .name = "gpio1", |
| 628 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 629 | .mpu_irqs = omap2_gpio1_irqs, |
| 630 | .main_clk = "gpios_fck", |
| 631 | .prcm = { |
| 632 | .omap2 = { |
| 633 | .prcm_reg_id = 1, |
| 634 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 635 | .module_offs = WKUP_MOD, |
| 636 | .idlest_reg_id = 1, |
| 637 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 638 | }, |
| 639 | }, |
| 640 | .class = &omap2xxx_gpio_hwmod_class, |
| 641 | .dev_attr = &omap2xxx_gpio_dev_attr, |
| 642 | }; |
| 643 | |
| 644 | /* gpio2 */ |
| 645 | struct omap_hwmod omap2xxx_gpio2_hwmod = { |
| 646 | .name = "gpio2", |
| 647 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 648 | .mpu_irqs = omap2_gpio2_irqs, |
| 649 | .main_clk = "gpios_fck", |
| 650 | .prcm = { |
| 651 | .omap2 = { |
| 652 | .prcm_reg_id = 1, |
| 653 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 654 | .module_offs = WKUP_MOD, |
| 655 | .idlest_reg_id = 1, |
| 656 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 657 | }, |
| 658 | }, |
| 659 | .class = &omap2xxx_gpio_hwmod_class, |
| 660 | .dev_attr = &omap2xxx_gpio_dev_attr, |
| 661 | }; |
| 662 | |
| 663 | /* gpio3 */ |
| 664 | struct omap_hwmod omap2xxx_gpio3_hwmod = { |
| 665 | .name = "gpio3", |
| 666 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 667 | .mpu_irqs = omap2_gpio3_irqs, |
| 668 | .main_clk = "gpios_fck", |
| 669 | .prcm = { |
| 670 | .omap2 = { |
| 671 | .prcm_reg_id = 1, |
| 672 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 673 | .module_offs = WKUP_MOD, |
| 674 | .idlest_reg_id = 1, |
| 675 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 676 | }, |
| 677 | }, |
| 678 | .class = &omap2xxx_gpio_hwmod_class, |
| 679 | .dev_attr = &omap2xxx_gpio_dev_attr, |
| 680 | }; |
| 681 | |
| 682 | /* gpio4 */ |
| 683 | struct omap_hwmod omap2xxx_gpio4_hwmod = { |
| 684 | .name = "gpio4", |
| 685 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
| 686 | .mpu_irqs = omap2_gpio4_irqs, |
| 687 | .main_clk = "gpios_fck", |
| 688 | .prcm = { |
| 689 | .omap2 = { |
| 690 | .prcm_reg_id = 1, |
| 691 | .module_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| 692 | .module_offs = WKUP_MOD, |
| 693 | .idlest_reg_id = 1, |
| 694 | .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
| 695 | }, |
| 696 | }, |
| 697 | .class = &omap2xxx_gpio_hwmod_class, |
| 698 | .dev_attr = &omap2xxx_gpio_dev_attr, |
| 699 | }; |
| 700 | |
| 701 | /* mcspi1 */ |
| 702 | static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = { |
| 703 | .num_chipselect = 4, |
| 704 | }; |
| 705 | |
| 706 | struct omap_hwmod omap2xxx_mcspi1_hwmod = { |
| 707 | .name = "mcspi1", |
| 708 | .mpu_irqs = omap2_mcspi1_mpu_irqs, |
| 709 | .sdma_reqs = omap2_mcspi1_sdma_reqs, |
| 710 | .main_clk = "mcspi1_fck", |
| 711 | .prcm = { |
| 712 | .omap2 = { |
| 713 | .module_offs = CORE_MOD, |
| 714 | .prcm_reg_id = 1, |
| 715 | .module_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 716 | .idlest_reg_id = 1, |
| 717 | .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
| 718 | }, |
| 719 | }, |
| 720 | .class = &omap2xxx_mcspi_class, |
| 721 | .dev_attr = &omap_mcspi1_dev_attr, |
| 722 | }; |
| 723 | |
| 724 | /* mcspi2 */ |
| 725 | static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = { |
| 726 | .num_chipselect = 2, |
| 727 | }; |
| 728 | |
| 729 | struct omap_hwmod omap2xxx_mcspi2_hwmod = { |
| 730 | .name = "mcspi2", |
| 731 | .mpu_irqs = omap2_mcspi2_mpu_irqs, |
| 732 | .sdma_reqs = omap2_mcspi2_sdma_reqs, |
| 733 | .main_clk = "mcspi2_fck", |
| 734 | .prcm = { |
| 735 | .omap2 = { |
| 736 | .module_offs = CORE_MOD, |
| 737 | .prcm_reg_id = 1, |
| 738 | .module_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| 739 | .idlest_reg_id = 1, |
| 740 | .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
| 741 | }, |
| 742 | }, |
| 743 | .class = &omap2xxx_mcspi_class, |
| 744 | .dev_attr = &omap_mcspi2_dev_attr, |
| 745 | }; |
Vaibhav Hiremath | c8d82ff | 2012-05-08 11:34:30 -0600 | [diff] [blame] | 746 | |
Vaibhav Hiremath | c8d82ff | 2012-05-08 11:34:30 -0600 | [diff] [blame] | 747 | static struct omap_hwmod_class omap2xxx_counter_hwmod_class = { |
| 748 | .name = "counter", |
| 749 | }; |
| 750 | |
| 751 | struct omap_hwmod omap2xxx_counter_32k_hwmod = { |
| 752 | .name = "counter_32k", |
| 753 | .main_clk = "func_32k_ck", |
| 754 | .prcm = { |
| 755 | .omap2 = { |
| 756 | .module_offs = WKUP_MOD, |
| 757 | .prcm_reg_id = 1, |
| 758 | .module_bit = OMAP24XX_ST_32KSYNC_SHIFT, |
| 759 | .idlest_reg_id = 1, |
| 760 | .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT, |
| 761 | }, |
| 762 | }, |
| 763 | .class = &omap2xxx_counter_hwmod_class, |
| 764 | }; |
Afzal Mohammed | 49484a6 | 2012-09-23 17:28:24 -0600 | [diff] [blame] | 765 | |
| 766 | /* gpmc */ |
| 767 | static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = { |
| 768 | { .irq = 20 }, |
| 769 | { .irq = -1 } |
| 770 | }; |
| 771 | |
| 772 | struct omap_hwmod omap2xxx_gpmc_hwmod = { |
| 773 | .name = "gpmc", |
| 774 | .class = &omap2xxx_gpmc_hwmod_class, |
| 775 | .mpu_irqs = omap2xxx_gpmc_irqs, |
| 776 | .main_clk = "gpmc_fck", |
| 777 | /* |
| 778 | * XXX HWMOD_INIT_NO_RESET should not be needed for this IP |
| 779 | * block. It is not being added due to any known bugs with |
| 780 | * resetting the GPMC IP block, but rather because any timings |
| 781 | * set by the bootloader are not being correctly programmed by |
| 782 | * the kernel from the board file or DT data. |
| 783 | * HWMOD_INIT_NO_RESET should be removed ASAP. |
| 784 | */ |
| 785 | .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET | |
| 786 | HWMOD_NO_IDLEST), |
| 787 | .prcm = { |
| 788 | .omap2 = { |
| 789 | .prcm_reg_id = 3, |
| 790 | .module_bit = OMAP24XX_EN_GPMC_MASK, |
| 791 | .module_offs = CORE_MOD, |
| 792 | }, |
| 793 | }, |
| 794 | }; |
Paul Walmsley | e9b0a2f | 2012-09-23 17:28:25 -0600 | [diff] [blame^] | 795 | |
| 796 | /* RNG */ |
| 797 | |
| 798 | static struct omap_hwmod_class_sysconfig omap2_rng_sysc = { |
| 799 | .rev_offs = 0x3c, |
| 800 | .sysc_offs = 0x40, |
| 801 | .syss_offs = 0x44, |
| 802 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
| 803 | SYSS_HAS_RESET_STATUS), |
| 804 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 805 | }; |
| 806 | |
| 807 | static struct omap_hwmod_class omap2_rng_hwmod_class = { |
| 808 | .name = "rng", |
| 809 | .sysc = &omap2_rng_sysc, |
| 810 | }; |
| 811 | |
| 812 | static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = { |
| 813 | { .irq = 52 }, |
| 814 | { .irq = -1 } |
| 815 | }; |
| 816 | |
| 817 | struct omap_hwmod omap2xxx_rng_hwmod = { |
| 818 | .name = "rng", |
| 819 | .mpu_irqs = omap2_rng_mpu_irqs, |
| 820 | .main_clk = "l4_ck", |
| 821 | .prcm = { |
| 822 | .omap2 = { |
| 823 | .module_offs = CORE_MOD, |
| 824 | .prcm_reg_id = 4, |
| 825 | .module_bit = OMAP24XX_EN_RNG_SHIFT, |
| 826 | .idlest_reg_id = 4, |
| 827 | .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT, |
| 828 | }, |
| 829 | }, |
| 830 | /* |
| 831 | * XXX The first read from the SYSSTATUS register of the RNG |
| 832 | * after the SYSCONFIG SOFTRESET bit is set triggers an |
| 833 | * imprecise external abort. It's unclear why this happens. |
| 834 | * Until this is analyzed, skip the IP block reset. |
| 835 | */ |
| 836 | .flags = HWMOD_INIT_NO_RESET, |
| 837 | .class = &omap2_rng_hwmod_class, |
| 838 | }; |