Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 1 | /* |
| 2 | * LIRC SIR driver, (C) 2000 Milan Pikula <www@fornax.sk> |
| 3 | * |
| 4 | * lirc_sir - Device driver for use with SIR (serial infra red) |
| 5 | * mode of IrDA on many notebooks. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | * |
| 21 | * |
| 22 | * 2000/09/16 Frank Przybylski <mail@frankprzybylski.de> : |
| 23 | * added timeout and relaxed pulse detection, removed gap bug |
| 24 | * |
| 25 | * 2000/12/15 Christoph Bartelmus <lirc@bartelmus.de> : |
| 26 | * added support for Tekram Irmate 210 (sending does not work yet, |
| 27 | * kind of disappointing that nobody was able to implement that |
| 28 | * before), |
| 29 | * major clean-up |
| 30 | * |
| 31 | * 2001/02/27 Christoph Bartelmus <lirc@bartelmus.de> : |
| 32 | * added support for StrongARM SA1100 embedded microprocessor |
| 33 | * parts cut'n'pasted from sa1100_ir.c (C) 2000 Russell King |
| 34 | */ |
| 35 | |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/sched.h> |
| 38 | #include <linux/errno.h> |
| 39 | #include <linux/signal.h> |
| 40 | #include <linux/fs.h> |
| 41 | #include <linux/interrupt.h> |
| 42 | #include <linux/ioport.h> |
| 43 | #include <linux/kernel.h> |
| 44 | #include <linux/serial_reg.h> |
| 45 | #include <linux/time.h> |
| 46 | #include <linux/string.h> |
| 47 | #include <linux/types.h> |
| 48 | #include <linux/wait.h> |
| 49 | #include <linux/mm.h> |
| 50 | #include <linux/delay.h> |
| 51 | #include <linux/poll.h> |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 52 | #include <linux/io.h> |
| 53 | #include <asm/irq.h> |
| 54 | #include <linux/fcntl.h> |
| 55 | #ifdef LIRC_ON_SA1100 |
| 56 | #include <asm/hardware.h> |
| 57 | #ifdef CONFIG_SA1100_COLLIE |
| 58 | #include <asm/arch/tc35143.h> |
| 59 | #include <asm/ucb1200.h> |
| 60 | #endif |
| 61 | #endif |
| 62 | |
| 63 | #include <linux/timer.h> |
| 64 | |
| 65 | #include <media/lirc.h> |
| 66 | #include <media/lirc_dev.h> |
| 67 | |
| 68 | /* SECTION: Definitions */ |
| 69 | |
| 70 | /*** Tekram dongle ***/ |
| 71 | #ifdef LIRC_SIR_TEKRAM |
| 72 | /* stolen from kernel source */ |
| 73 | /* definitions for Tekram dongle */ |
| 74 | #define TEKRAM_115200 0x00 |
| 75 | #define TEKRAM_57600 0x01 |
| 76 | #define TEKRAM_38400 0x02 |
| 77 | #define TEKRAM_19200 0x03 |
| 78 | #define TEKRAM_9600 0x04 |
| 79 | #define TEKRAM_2400 0x08 |
| 80 | |
| 81 | #define TEKRAM_PW 0x10 /* Pulse select bit */ |
| 82 | |
| 83 | /* 10bit * 1s/115200bit in milliseconds = 87ms*/ |
| 84 | #define TIME_CONST (10000000ul/115200ul) |
| 85 | |
| 86 | #endif |
| 87 | |
| 88 | #ifdef LIRC_SIR_ACTISYS_ACT200L |
| 89 | static void init_act200(void); |
| 90 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) |
| 91 | static void init_act220(void); |
| 92 | #endif |
| 93 | |
| 94 | /*** SA1100 ***/ |
| 95 | #ifdef LIRC_ON_SA1100 |
| 96 | struct sa1100_ser2_registers { |
| 97 | /* HSSP control register */ |
| 98 | unsigned char hscr0; |
| 99 | /* UART registers */ |
| 100 | unsigned char utcr0; |
| 101 | unsigned char utcr1; |
| 102 | unsigned char utcr2; |
| 103 | unsigned char utcr3; |
| 104 | unsigned char utcr4; |
| 105 | unsigned char utdr; |
| 106 | unsigned char utsr0; |
| 107 | unsigned char utsr1; |
| 108 | } sr; |
| 109 | |
| 110 | static int irq = IRQ_Ser2ICP; |
| 111 | |
| 112 | #define LIRC_ON_SA1100_TRANSMITTER_LATENCY 0 |
| 113 | |
| 114 | /* pulse/space ratio of 50/50 */ |
| 115 | static unsigned long pulse_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); |
| 116 | /* 1000000/freq-pulse_width */ |
| 117 | static unsigned long space_width = (13-LIRC_ON_SA1100_TRANSMITTER_LATENCY); |
| 118 | static unsigned int freq = 38000; /* modulation frequency */ |
| 119 | static unsigned int duty_cycle = 50; /* duty cycle of 50% */ |
| 120 | |
| 121 | #endif |
| 122 | |
| 123 | #define RBUF_LEN 1024 |
| 124 | #define WBUF_LEN 1024 |
| 125 | |
| 126 | #define LIRC_DRIVER_NAME "lirc_sir" |
| 127 | |
| 128 | #define PULSE '[' |
| 129 | |
| 130 | #ifndef LIRC_SIR_TEKRAM |
| 131 | /* 9bit * 1s/115200bit in milli seconds = 78.125ms*/ |
| 132 | #define TIME_CONST (9000000ul/115200ul) |
| 133 | #endif |
| 134 | |
| 135 | |
| 136 | /* timeout for sequences in jiffies (=5/100s), must be longer than TIME_CONST */ |
| 137 | #define SIR_TIMEOUT (HZ*5/100) |
| 138 | |
| 139 | #ifndef LIRC_ON_SA1100 |
| 140 | #ifndef LIRC_IRQ |
| 141 | #define LIRC_IRQ 4 |
| 142 | #endif |
| 143 | #ifndef LIRC_PORT |
| 144 | /* for external dongles, default to com1 */ |
Greg Dietsche | d713680 | 2011-04-30 15:03:20 -0500 | [diff] [blame] | 145 | #if defined(LIRC_SIR_ACTISYS_ACT200L) || \ |
| 146 | defined(LIRC_SIR_ACTISYS_ACT220L) || \ |
| 147 | defined(LIRC_SIR_TEKRAM) |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 148 | #define LIRC_PORT 0x3f8 |
| 149 | #else |
| 150 | /* onboard sir ports are typically com3 */ |
| 151 | #define LIRC_PORT 0x3e8 |
| 152 | #endif |
| 153 | #endif |
| 154 | |
| 155 | static int io = LIRC_PORT; |
| 156 | static int irq = LIRC_IRQ; |
| 157 | static int threshold = 3; |
| 158 | #endif |
| 159 | |
| 160 | static DEFINE_SPINLOCK(timer_lock); |
| 161 | static struct timer_list timerlist; |
| 162 | /* time of last signal change detected */ |
| 163 | static struct timeval last_tv = {0, 0}; |
| 164 | /* time of last UART data ready interrupt */ |
| 165 | static struct timeval last_intr_tv = {0, 0}; |
| 166 | static int last_value; |
| 167 | |
| 168 | static DECLARE_WAIT_QUEUE_HEAD(lirc_read_queue); |
| 169 | |
| 170 | static DEFINE_SPINLOCK(hardware_lock); |
| 171 | |
| 172 | static int rx_buf[RBUF_LEN]; |
| 173 | static unsigned int rx_tail, rx_head; |
| 174 | |
Rusty Russell | 90ab5ee | 2012-01-13 09:32:20 +1030 | [diff] [blame] | 175 | static bool debug; |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 176 | #define dprintk(fmt, args...) \ |
| 177 | do { \ |
| 178 | if (debug) \ |
| 179 | printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ |
| 180 | fmt, ## args); \ |
| 181 | } while (0) |
| 182 | |
| 183 | /* SECTION: Prototypes */ |
| 184 | |
| 185 | /* Communication with user-space */ |
| 186 | static unsigned int lirc_poll(struct file *file, poll_table *wait); |
| 187 | static ssize_t lirc_read(struct file *file, char *buf, size_t count, |
| 188 | loff_t *ppos); |
| 189 | static ssize_t lirc_write(struct file *file, const char *buf, size_t n, |
| 190 | loff_t *pos); |
| 191 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); |
| 192 | static void add_read_queue(int flag, unsigned long val); |
| 193 | static int init_chrdev(void); |
| 194 | static void drop_chrdev(void); |
| 195 | /* Hardware */ |
| 196 | static irqreturn_t sir_interrupt(int irq, void *dev_id); |
| 197 | static void send_space(unsigned long len); |
| 198 | static void send_pulse(unsigned long len); |
| 199 | static int init_hardware(void); |
| 200 | static void drop_hardware(void); |
| 201 | /* Initialisation */ |
| 202 | static int init_port(void); |
| 203 | static void drop_port(void); |
| 204 | |
| 205 | #ifdef LIRC_ON_SA1100 |
| 206 | static void on(void) |
| 207 | { |
| 208 | PPSR |= PPC_TXD2; |
| 209 | } |
| 210 | |
| 211 | static void off(void) |
| 212 | { |
| 213 | PPSR &= ~PPC_TXD2; |
| 214 | } |
| 215 | #else |
| 216 | static inline unsigned int sinp(int offset) |
| 217 | { |
| 218 | return inb(io + offset); |
| 219 | } |
| 220 | |
| 221 | static inline void soutp(int offset, int value) |
| 222 | { |
| 223 | outb(value, io + offset); |
| 224 | } |
| 225 | #endif |
| 226 | |
| 227 | #ifndef MAX_UDELAY_MS |
| 228 | #define MAX_UDELAY_US 5000 |
| 229 | #else |
| 230 | #define MAX_UDELAY_US (MAX_UDELAY_MS*1000) |
| 231 | #endif |
| 232 | |
| 233 | static void safe_udelay(unsigned long usecs) |
| 234 | { |
| 235 | while (usecs > MAX_UDELAY_US) { |
| 236 | udelay(MAX_UDELAY_US); |
| 237 | usecs -= MAX_UDELAY_US; |
| 238 | } |
| 239 | udelay(usecs); |
| 240 | } |
| 241 | |
| 242 | /* SECTION: Communication with user-space */ |
| 243 | |
| 244 | static unsigned int lirc_poll(struct file *file, poll_table *wait) |
| 245 | { |
| 246 | poll_wait(file, &lirc_read_queue, wait); |
| 247 | if (rx_head != rx_tail) |
| 248 | return POLLIN | POLLRDNORM; |
| 249 | return 0; |
| 250 | } |
| 251 | |
| 252 | static ssize_t lirc_read(struct file *file, char *buf, size_t count, |
| 253 | loff_t *ppos) |
| 254 | { |
| 255 | int n = 0; |
| 256 | int retval = 0; |
| 257 | DECLARE_WAITQUEUE(wait, current); |
| 258 | |
| 259 | if (count % sizeof(int)) |
| 260 | return -EINVAL; |
| 261 | |
| 262 | add_wait_queue(&lirc_read_queue, &wait); |
| 263 | set_current_state(TASK_INTERRUPTIBLE); |
| 264 | while (n < count) { |
| 265 | if (rx_head != rx_tail) { |
| 266 | if (copy_to_user((void *) buf + n, |
| 267 | (void *) (rx_buf + rx_head), |
| 268 | sizeof(int))) { |
| 269 | retval = -EFAULT; |
| 270 | break; |
| 271 | } |
| 272 | rx_head = (rx_head + 1) & (RBUF_LEN - 1); |
| 273 | n += sizeof(int); |
| 274 | } else { |
| 275 | if (file->f_flags & O_NONBLOCK) { |
| 276 | retval = -EAGAIN; |
| 277 | break; |
| 278 | } |
| 279 | if (signal_pending(current)) { |
| 280 | retval = -ERESTARTSYS; |
| 281 | break; |
| 282 | } |
| 283 | schedule(); |
| 284 | set_current_state(TASK_INTERRUPTIBLE); |
| 285 | } |
| 286 | } |
| 287 | remove_wait_queue(&lirc_read_queue, &wait); |
| 288 | set_current_state(TASK_RUNNING); |
| 289 | return n ? n : retval; |
| 290 | } |
| 291 | static ssize_t lirc_write(struct file *file, const char *buf, size_t n, |
| 292 | loff_t *pos) |
| 293 | { |
| 294 | unsigned long flags; |
| 295 | int i, count; |
| 296 | int *tx_buf; |
| 297 | |
| 298 | count = n / sizeof(int); |
| 299 | if (n % sizeof(int) || count % 2 == 0) |
| 300 | return -EINVAL; |
| 301 | tx_buf = memdup_user(buf, n); |
| 302 | if (IS_ERR(tx_buf)) |
| 303 | return PTR_ERR(tx_buf); |
| 304 | i = 0; |
| 305 | #ifdef LIRC_ON_SA1100 |
| 306 | /* disable receiver */ |
| 307 | Ser2UTCR3 = 0; |
| 308 | #endif |
| 309 | local_irq_save(flags); |
| 310 | while (1) { |
| 311 | if (i >= count) |
| 312 | break; |
| 313 | if (tx_buf[i]) |
| 314 | send_pulse(tx_buf[i]); |
| 315 | i++; |
| 316 | if (i >= count) |
| 317 | break; |
| 318 | if (tx_buf[i]) |
| 319 | send_space(tx_buf[i]); |
| 320 | i++; |
| 321 | } |
| 322 | local_irq_restore(flags); |
| 323 | #ifdef LIRC_ON_SA1100 |
| 324 | off(); |
| 325 | udelay(1000); /* wait 1ms for IR diode to recover */ |
| 326 | Ser2UTCR3 = 0; |
| 327 | /* clear status register to prevent unwanted interrupts */ |
| 328 | Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); |
| 329 | /* enable receiver */ |
| 330 | Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; |
| 331 | #endif |
Jarod Wilson | 88914bd | 2011-01-17 16:02:00 -0300 | [diff] [blame] | 332 | kfree(tx_buf); |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 333 | return count; |
| 334 | } |
| 335 | |
| 336 | static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) |
| 337 | { |
| 338 | int retval = 0; |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 339 | __u32 value = 0; |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 340 | #ifdef LIRC_ON_SA1100 |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 341 | |
| 342 | if (cmd == LIRC_GET_FEATURES) |
| 343 | value = LIRC_CAN_SEND_PULSE | |
| 344 | LIRC_CAN_SET_SEND_DUTY_CYCLE | |
| 345 | LIRC_CAN_SET_SEND_CARRIER | |
| 346 | LIRC_CAN_REC_MODE2; |
| 347 | else if (cmd == LIRC_GET_SEND_MODE) |
| 348 | value = LIRC_MODE_PULSE; |
| 349 | else if (cmd == LIRC_GET_REC_MODE) |
| 350 | value = LIRC_MODE_MODE2; |
| 351 | #else |
| 352 | if (cmd == LIRC_GET_FEATURES) |
| 353 | value = LIRC_CAN_SEND_PULSE | LIRC_CAN_REC_MODE2; |
| 354 | else if (cmd == LIRC_GET_SEND_MODE) |
| 355 | value = LIRC_MODE_PULSE; |
| 356 | else if (cmd == LIRC_GET_REC_MODE) |
| 357 | value = LIRC_MODE_MODE2; |
| 358 | #endif |
| 359 | |
| 360 | switch (cmd) { |
| 361 | case LIRC_GET_FEATURES: |
| 362 | case LIRC_GET_SEND_MODE: |
| 363 | case LIRC_GET_REC_MODE: |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 364 | retval = put_user(value, (__u32 *) arg); |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 365 | break; |
| 366 | |
| 367 | case LIRC_SET_SEND_MODE: |
| 368 | case LIRC_SET_REC_MODE: |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 369 | retval = get_user(value, (__u32 *) arg); |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 370 | break; |
| 371 | #ifdef LIRC_ON_SA1100 |
| 372 | case LIRC_SET_SEND_DUTY_CYCLE: |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 373 | retval = get_user(value, (__u32 *) arg); |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 374 | if (retval) |
| 375 | return retval; |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 376 | if (value <= 0 || value > 100) |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 377 | return -EINVAL; |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 378 | /* (value/100)*(1000000/freq) */ |
| 379 | duty_cycle = value; |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 380 | pulse_width = (unsigned long) duty_cycle*10000/freq; |
| 381 | space_width = (unsigned long) 1000000L/freq-pulse_width; |
| 382 | if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) |
| 383 | pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; |
| 384 | if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) |
| 385 | space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; |
| 386 | break; |
| 387 | case LIRC_SET_SEND_CARRIER: |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 388 | retval = get_user(value, (__u32 *) arg); |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 389 | if (retval) |
| 390 | return retval; |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 391 | if (value > 500000 || value < 20000) |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 392 | return -EINVAL; |
Jarod Wilson | a126681 | 2010-10-08 17:35:09 -0300 | [diff] [blame] | 393 | freq = value; |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 394 | pulse_width = (unsigned long) duty_cycle*10000/freq; |
| 395 | space_width = (unsigned long) 1000000L/freq-pulse_width; |
| 396 | if (pulse_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) |
| 397 | pulse_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; |
| 398 | if (space_width >= LIRC_ON_SA1100_TRANSMITTER_LATENCY) |
| 399 | space_width -= LIRC_ON_SA1100_TRANSMITTER_LATENCY; |
| 400 | break; |
| 401 | #endif |
| 402 | default: |
| 403 | retval = -ENOIOCTLCMD; |
| 404 | |
| 405 | } |
| 406 | |
| 407 | if (retval) |
| 408 | return retval; |
| 409 | if (cmd == LIRC_SET_REC_MODE) { |
| 410 | if (value != LIRC_MODE_MODE2) |
| 411 | retval = -ENOSYS; |
| 412 | } else if (cmd == LIRC_SET_SEND_MODE) { |
| 413 | if (value != LIRC_MODE_PULSE) |
| 414 | retval = -ENOSYS; |
| 415 | } |
| 416 | |
| 417 | return retval; |
| 418 | } |
| 419 | |
| 420 | static void add_read_queue(int flag, unsigned long val) |
| 421 | { |
| 422 | unsigned int new_rx_tail; |
| 423 | int newval; |
| 424 | |
| 425 | dprintk("add flag %d with val %lu\n", flag, val); |
| 426 | |
| 427 | newval = val & PULSE_MASK; |
| 428 | |
| 429 | /* |
| 430 | * statistically, pulses are ~TIME_CONST/2 too long. we could |
| 431 | * maybe make this more exact, but this is good enough |
| 432 | */ |
| 433 | if (flag) { |
| 434 | /* pulse */ |
| 435 | if (newval > TIME_CONST/2) |
| 436 | newval -= TIME_CONST/2; |
| 437 | else /* should not ever happen */ |
| 438 | newval = 1; |
| 439 | newval |= PULSE_BIT; |
| 440 | } else { |
| 441 | newval += TIME_CONST/2; |
| 442 | } |
| 443 | new_rx_tail = (rx_tail + 1) & (RBUF_LEN - 1); |
| 444 | if (new_rx_tail == rx_head) { |
| 445 | dprintk("Buffer overrun.\n"); |
| 446 | return; |
| 447 | } |
| 448 | rx_buf[rx_tail] = newval; |
| 449 | rx_tail = new_rx_tail; |
| 450 | wake_up_interruptible(&lirc_read_queue); |
| 451 | } |
| 452 | |
Mauro Carvalho Chehab | 0f9313a | 2010-07-27 18:44:45 -0300 | [diff] [blame] | 453 | static const struct file_operations lirc_fops = { |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 454 | .owner = THIS_MODULE, |
| 455 | .read = lirc_read, |
| 456 | .write = lirc_write, |
| 457 | .poll = lirc_poll, |
| 458 | .unlocked_ioctl = lirc_ioctl, |
Jarod Wilson | 8be292c | 2010-10-09 15:07:06 -0300 | [diff] [blame] | 459 | #ifdef CONFIG_COMPAT |
| 460 | .compat_ioctl = lirc_ioctl, |
| 461 | #endif |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 462 | .open = lirc_dev_fop_open, |
| 463 | .release = lirc_dev_fop_close, |
Arnd Bergmann | d9d2e9d | 2010-08-15 18:51:56 +0200 | [diff] [blame] | 464 | .llseek = no_llseek, |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 465 | }; |
| 466 | |
| 467 | static int set_use_inc(void *data) |
| 468 | { |
Greg Dietsche | d713680 | 2011-04-30 15:03:20 -0500 | [diff] [blame] | 469 | return 0; |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 470 | } |
| 471 | |
| 472 | static void set_use_dec(void *data) |
| 473 | { |
| 474 | } |
| 475 | |
| 476 | static struct lirc_driver driver = { |
Greg Dietsche | d713680 | 2011-04-30 15:03:20 -0500 | [diff] [blame] | 477 | .name = LIRC_DRIVER_NAME, |
| 478 | .minor = -1, |
| 479 | .code_length = 1, |
| 480 | .sample_rate = 0, |
| 481 | .data = NULL, |
| 482 | .add_to_buf = NULL, |
| 483 | .set_use_inc = set_use_inc, |
| 484 | .set_use_dec = set_use_dec, |
| 485 | .fops = &lirc_fops, |
| 486 | .dev = NULL, |
| 487 | .owner = THIS_MODULE, |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 488 | }; |
| 489 | |
| 490 | |
| 491 | static int init_chrdev(void) |
| 492 | { |
| 493 | driver.minor = lirc_register_driver(&driver); |
| 494 | if (driver.minor < 0) { |
| 495 | printk(KERN_ERR LIRC_DRIVER_NAME ": init_chrdev() failed.\n"); |
| 496 | return -EIO; |
| 497 | } |
| 498 | return 0; |
| 499 | } |
| 500 | |
| 501 | static void drop_chrdev(void) |
| 502 | { |
| 503 | lirc_unregister_driver(driver.minor); |
| 504 | } |
| 505 | |
| 506 | /* SECTION: Hardware */ |
| 507 | static long delta(struct timeval *tv1, struct timeval *tv2) |
| 508 | { |
| 509 | unsigned long deltv; |
| 510 | |
| 511 | deltv = tv2->tv_sec - tv1->tv_sec; |
| 512 | if (deltv > 15) |
| 513 | deltv = 0xFFFFFF; |
| 514 | else |
| 515 | deltv = deltv*1000000 + |
| 516 | tv2->tv_usec - |
| 517 | tv1->tv_usec; |
| 518 | return deltv; |
| 519 | } |
| 520 | |
| 521 | static void sir_timeout(unsigned long data) |
| 522 | { |
| 523 | /* |
| 524 | * if last received signal was a pulse, but receiving stopped |
| 525 | * within the 9 bit frame, we need to finish this pulse and |
| 526 | * simulate a signal change to from pulse to space. Otherwise |
| 527 | * upper layers will receive two sequences next time. |
| 528 | */ |
| 529 | |
| 530 | unsigned long flags; |
| 531 | unsigned long pulse_end; |
| 532 | |
| 533 | /* avoid interference with interrupt */ |
| 534 | spin_lock_irqsave(&timer_lock, flags); |
| 535 | if (last_value) { |
| 536 | #ifndef LIRC_ON_SA1100 |
| 537 | /* clear unread bits in UART and restart */ |
| 538 | outb(UART_FCR_CLEAR_RCVR, io + UART_FCR); |
| 539 | #endif |
| 540 | /* determine 'virtual' pulse end: */ |
| 541 | pulse_end = delta(&last_tv, &last_intr_tv); |
| 542 | dprintk("timeout add %d for %lu usec\n", last_value, pulse_end); |
| 543 | add_read_queue(last_value, pulse_end); |
| 544 | last_value = 0; |
| 545 | last_tv = last_intr_tv; |
| 546 | } |
| 547 | spin_unlock_irqrestore(&timer_lock, flags); |
| 548 | } |
| 549 | |
| 550 | static irqreturn_t sir_interrupt(int irq, void *dev_id) |
| 551 | { |
| 552 | unsigned char data; |
| 553 | struct timeval curr_tv; |
| 554 | static unsigned long deltv; |
| 555 | #ifdef LIRC_ON_SA1100 |
| 556 | int status; |
| 557 | static int n; |
| 558 | |
| 559 | status = Ser2UTSR0; |
| 560 | /* |
| 561 | * Deal with any receive errors first. The bytes in error may be |
| 562 | * the only bytes in the receive FIFO, so we do this first. |
| 563 | */ |
| 564 | while (status & UTSR0_EIF) { |
| 565 | int bstat; |
| 566 | |
| 567 | if (debug) { |
| 568 | dprintk("EIF\n"); |
| 569 | bstat = Ser2UTSR1; |
| 570 | |
| 571 | if (bstat & UTSR1_FRE) |
| 572 | dprintk("frame error\n"); |
| 573 | if (bstat & UTSR1_ROR) |
| 574 | dprintk("receive fifo overrun\n"); |
| 575 | if (bstat & UTSR1_PRE) |
| 576 | dprintk("parity error\n"); |
| 577 | } |
| 578 | |
| 579 | bstat = Ser2UTDR; |
| 580 | n++; |
| 581 | status = Ser2UTSR0; |
| 582 | } |
| 583 | |
| 584 | if (status & (UTSR0_RFS | UTSR0_RID)) { |
| 585 | do_gettimeofday(&curr_tv); |
| 586 | deltv = delta(&last_tv, &curr_tv); |
| 587 | do { |
| 588 | data = Ser2UTDR; |
| 589 | dprintk("%d data: %u\n", n, (unsigned int) data); |
| 590 | n++; |
| 591 | } while (status & UTSR0_RID && /* do not empty fifo in order to |
| 592 | * get UTSR0_RID in any case */ |
| 593 | Ser2UTSR1 & UTSR1_RNE); /* data ready */ |
| 594 | |
| 595 | if (status&UTSR0_RID) { |
| 596 | add_read_queue(0 , deltv - n * TIME_CONST); /*space*/ |
| 597 | add_read_queue(1, n * TIME_CONST); /*pulse*/ |
| 598 | n = 0; |
| 599 | last_tv = curr_tv; |
| 600 | } |
| 601 | } |
| 602 | |
| 603 | if (status & UTSR0_TFS) |
| 604 | printk(KERN_ERR "transmit fifo not full, shouldn't happen\n"); |
| 605 | |
| 606 | /* We must clear certain bits. */ |
| 607 | status &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); |
| 608 | if (status) |
| 609 | Ser2UTSR0 = status; |
| 610 | #else |
| 611 | unsigned long deltintrtv; |
| 612 | unsigned long flags; |
| 613 | int iir, lsr; |
| 614 | |
| 615 | while ((iir = inb(io + UART_IIR) & UART_IIR_ID)) { |
| 616 | switch (iir&UART_IIR_ID) { /* FIXME toto treba preriedit */ |
| 617 | case UART_IIR_MSI: |
| 618 | (void) inb(io + UART_MSR); |
| 619 | break; |
| 620 | case UART_IIR_RLSI: |
| 621 | (void) inb(io + UART_LSR); |
| 622 | break; |
| 623 | case UART_IIR_THRI: |
| 624 | #if 0 |
| 625 | if (lsr & UART_LSR_THRE) /* FIFO is empty */ |
| 626 | outb(data, io + UART_TX) |
| 627 | #endif |
| 628 | break; |
| 629 | case UART_IIR_RDI: |
| 630 | /* avoid interference with timer */ |
| 631 | spin_lock_irqsave(&timer_lock, flags); |
| 632 | do { |
| 633 | del_timer(&timerlist); |
| 634 | data = inb(io + UART_RX); |
| 635 | do_gettimeofday(&curr_tv); |
| 636 | deltv = delta(&last_tv, &curr_tv); |
| 637 | deltintrtv = delta(&last_intr_tv, &curr_tv); |
| 638 | dprintk("t %lu, d %d\n", deltintrtv, (int)data); |
| 639 | /* |
| 640 | * if nothing came in last X cycles, |
| 641 | * it was gap |
| 642 | */ |
| 643 | if (deltintrtv > TIME_CONST * threshold) { |
| 644 | if (last_value) { |
| 645 | dprintk("GAP\n"); |
| 646 | /* simulate signal change */ |
| 647 | add_read_queue(last_value, |
| 648 | deltv - |
| 649 | deltintrtv); |
| 650 | last_value = 0; |
| 651 | last_tv.tv_sec = |
| 652 | last_intr_tv.tv_sec; |
| 653 | last_tv.tv_usec = |
| 654 | last_intr_tv.tv_usec; |
| 655 | deltv = deltintrtv; |
| 656 | } |
| 657 | } |
| 658 | data = 1; |
| 659 | if (data ^ last_value) { |
| 660 | /* |
| 661 | * deltintrtv > 2*TIME_CONST, remember? |
| 662 | * the other case is timeout |
| 663 | */ |
| 664 | add_read_queue(last_value, |
| 665 | deltv-TIME_CONST); |
| 666 | last_value = data; |
| 667 | last_tv = curr_tv; |
| 668 | if (last_tv.tv_usec >= TIME_CONST) { |
| 669 | last_tv.tv_usec -= TIME_CONST; |
| 670 | } else { |
| 671 | last_tv.tv_sec--; |
| 672 | last_tv.tv_usec += 1000000 - |
| 673 | TIME_CONST; |
| 674 | } |
| 675 | } |
| 676 | last_intr_tv = curr_tv; |
| 677 | if (data) { |
| 678 | /* |
| 679 | * start timer for end of |
| 680 | * sequence detection |
| 681 | */ |
| 682 | timerlist.expires = jiffies + |
| 683 | SIR_TIMEOUT; |
| 684 | add_timer(&timerlist); |
| 685 | } |
| 686 | |
| 687 | lsr = inb(io + UART_LSR); |
| 688 | } while (lsr & UART_LSR_DR); /* data ready */ |
| 689 | spin_unlock_irqrestore(&timer_lock, flags); |
| 690 | break; |
| 691 | default: |
| 692 | break; |
| 693 | } |
| 694 | } |
| 695 | #endif |
| 696 | return IRQ_RETVAL(IRQ_HANDLED); |
| 697 | } |
| 698 | |
| 699 | #ifdef LIRC_ON_SA1100 |
| 700 | static void send_pulse(unsigned long length) |
| 701 | { |
| 702 | unsigned long k, delay; |
| 703 | int flag; |
| 704 | |
| 705 | if (length == 0) |
| 706 | return; |
| 707 | /* |
| 708 | * this won't give us the carrier frequency we really want |
| 709 | * due to integer arithmetic, but we can accept this inaccuracy |
| 710 | */ |
| 711 | |
| 712 | for (k = flag = 0; k < length; k += delay, flag = !flag) { |
| 713 | if (flag) { |
| 714 | off(); |
| 715 | delay = space_width; |
| 716 | } else { |
| 717 | on(); |
| 718 | delay = pulse_width; |
| 719 | } |
| 720 | safe_udelay(delay); |
| 721 | } |
| 722 | off(); |
| 723 | } |
| 724 | |
| 725 | static void send_space(unsigned long length) |
| 726 | { |
| 727 | if (length == 0) |
| 728 | return; |
| 729 | off(); |
| 730 | safe_udelay(length); |
| 731 | } |
| 732 | #else |
| 733 | static void send_space(unsigned long len) |
| 734 | { |
| 735 | safe_udelay(len); |
| 736 | } |
| 737 | |
| 738 | static void send_pulse(unsigned long len) |
| 739 | { |
| 740 | long bytes_out = len / TIME_CONST; |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 741 | |
Jarod Wilson | 04f561f | 2011-05-27 15:46:19 -0300 | [diff] [blame] | 742 | if (bytes_out == 0) |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 743 | bytes_out++; |
Jarod Wilson | 04f561f | 2011-05-27 15:46:19 -0300 | [diff] [blame] | 744 | |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 745 | while (bytes_out--) { |
| 746 | outb(PULSE, io + UART_TX); |
| 747 | /* FIXME treba seriozne cakanie z char/serial.c */ |
| 748 | while (!(inb(io + UART_LSR) & UART_LSR_THRE)) |
| 749 | ; |
| 750 | } |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 751 | } |
| 752 | #endif |
| 753 | |
| 754 | #ifdef CONFIG_SA1100_COLLIE |
| 755 | static int sa1100_irda_set_power_collie(int state) |
| 756 | { |
| 757 | if (state) { |
| 758 | /* |
| 759 | * 0 - off |
| 760 | * 1 - short range, lowest power |
| 761 | * 2 - medium range, medium power |
| 762 | * 3 - maximum range, high power |
| 763 | */ |
| 764 | ucb1200_set_io_direction(TC35143_GPIO_IR_ON, |
| 765 | TC35143_IODIR_OUTPUT); |
| 766 | ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_LOW); |
| 767 | udelay(100); |
| 768 | } else { |
| 769 | /* OFF */ |
| 770 | ucb1200_set_io_direction(TC35143_GPIO_IR_ON, |
| 771 | TC35143_IODIR_OUTPUT); |
| 772 | ucb1200_set_io(TC35143_GPIO_IR_ON, TC35143_IODAT_HIGH); |
| 773 | } |
| 774 | return 0; |
| 775 | } |
| 776 | #endif |
| 777 | |
| 778 | static int init_hardware(void) |
| 779 | { |
| 780 | unsigned long flags; |
| 781 | |
| 782 | spin_lock_irqsave(&hardware_lock, flags); |
| 783 | /* reset UART */ |
| 784 | #ifdef LIRC_ON_SA1100 |
| 785 | #ifdef CONFIG_SA1100_BITSY |
| 786 | if (machine_is_bitsy()) { |
| 787 | printk(KERN_INFO "Power on IR module\n"); |
| 788 | set_bitsy_egpio(EGPIO_BITSY_IR_ON); |
| 789 | } |
| 790 | #endif |
| 791 | #ifdef CONFIG_SA1100_COLLIE |
| 792 | sa1100_irda_set_power_collie(3); /* power on */ |
| 793 | #endif |
| 794 | sr.hscr0 = Ser2HSCR0; |
| 795 | |
| 796 | sr.utcr0 = Ser2UTCR0; |
| 797 | sr.utcr1 = Ser2UTCR1; |
| 798 | sr.utcr2 = Ser2UTCR2; |
| 799 | sr.utcr3 = Ser2UTCR3; |
| 800 | sr.utcr4 = Ser2UTCR4; |
| 801 | |
| 802 | sr.utdr = Ser2UTDR; |
| 803 | sr.utsr0 = Ser2UTSR0; |
| 804 | sr.utsr1 = Ser2UTSR1; |
| 805 | |
| 806 | /* configure GPIO */ |
| 807 | /* output */ |
| 808 | PPDR |= PPC_TXD2; |
| 809 | PSDR |= PPC_TXD2; |
| 810 | /* set output to 0 */ |
| 811 | off(); |
| 812 | |
| 813 | /* Enable HP-SIR modulation, and ensure that the port is disabled. */ |
| 814 | Ser2UTCR3 = 0; |
| 815 | Ser2HSCR0 = sr.hscr0 & (~HSCR0_HSSP); |
| 816 | |
| 817 | /* clear status register to prevent unwanted interrupts */ |
| 818 | Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); |
| 819 | |
| 820 | /* 7N1 */ |
| 821 | Ser2UTCR0 = UTCR0_1StpBit|UTCR0_7BitData; |
| 822 | /* 115200 */ |
| 823 | Ser2UTCR1 = 0; |
| 824 | Ser2UTCR2 = 1; |
| 825 | /* use HPSIR, 1.6 usec pulses */ |
| 826 | Ser2UTCR4 = UTCR4_HPSIR|UTCR4_Z1_6us; |
| 827 | |
| 828 | /* enable receiver, receive fifo interrupt */ |
| 829 | Ser2UTCR3 = UTCR3_RXE|UTCR3_RIE; |
| 830 | |
| 831 | /* clear status register to prevent unwanted interrupts */ |
| 832 | Ser2UTSR0 &= (UTSR0_RID | UTSR0_RBB | UTSR0_REB); |
| 833 | |
| 834 | #elif defined(LIRC_SIR_TEKRAM) |
| 835 | /* disable FIFO */ |
| 836 | soutp(UART_FCR, |
| 837 | UART_FCR_CLEAR_RCVR| |
| 838 | UART_FCR_CLEAR_XMIT| |
| 839 | UART_FCR_TRIGGER_1); |
| 840 | |
| 841 | /* Set DLAB 0. */ |
| 842 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); |
| 843 | |
| 844 | /* First of all, disable all interrupts */ |
| 845 | soutp(UART_IER, sinp(UART_IER) & |
| 846 | (~(UART_IER_MSI|UART_IER_RLSI|UART_IER_THRI|UART_IER_RDI))); |
| 847 | |
| 848 | /* Set DLAB 1. */ |
| 849 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); |
| 850 | |
| 851 | /* Set divisor to 12 => 9600 Baud */ |
| 852 | soutp(UART_DLM, 0); |
| 853 | soutp(UART_DLL, 12); |
| 854 | |
| 855 | /* Set DLAB 0. */ |
| 856 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); |
| 857 | |
| 858 | /* power supply */ |
| 859 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 860 | safe_udelay(50*1000); |
| 861 | |
| 862 | /* -DTR low -> reset PIC */ |
| 863 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); |
| 864 | udelay(1*1000); |
| 865 | |
| 866 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 867 | udelay(100); |
| 868 | |
| 869 | |
| 870 | /* -RTS low -> send control byte */ |
| 871 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); |
| 872 | udelay(7); |
| 873 | soutp(UART_TX, TEKRAM_115200|TEKRAM_PW); |
| 874 | |
| 875 | /* one byte takes ~1042 usec to transmit at 9600,8N1 */ |
| 876 | udelay(1500); |
| 877 | |
| 878 | /* back to normal operation */ |
| 879 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 880 | udelay(50); |
| 881 | |
| 882 | udelay(1500); |
| 883 | |
| 884 | /* read previous control byte */ |
| 885 | printk(KERN_INFO LIRC_DRIVER_NAME |
| 886 | ": 0x%02x\n", sinp(UART_RX)); |
| 887 | |
| 888 | /* Set DLAB 1. */ |
| 889 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); |
| 890 | |
| 891 | /* Set divisor to 1 => 115200 Baud */ |
| 892 | soutp(UART_DLM, 0); |
| 893 | soutp(UART_DLL, 1); |
| 894 | |
| 895 | /* Set DLAB 0, 8 Bit */ |
| 896 | soutp(UART_LCR, UART_LCR_WLEN8); |
| 897 | /* enable interrupts */ |
| 898 | soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); |
| 899 | #else |
| 900 | outb(0, io + UART_MCR); |
| 901 | outb(0, io + UART_IER); |
| 902 | /* init UART */ |
| 903 | /* set DLAB, speed = 115200 */ |
| 904 | outb(UART_LCR_DLAB | UART_LCR_WLEN7, io + UART_LCR); |
| 905 | outb(1, io + UART_DLL); outb(0, io + UART_DLM); |
| 906 | /* 7N1+start = 9 bits at 115200 ~ 3 bits at 44000 */ |
| 907 | outb(UART_LCR_WLEN7, io + UART_LCR); |
| 908 | /* FIFO operation */ |
| 909 | outb(UART_FCR_ENABLE_FIFO, io + UART_FCR); |
| 910 | /* interrupts */ |
| 911 | /* outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, io + UART_IER); */ |
| 912 | outb(UART_IER_RDI, io + UART_IER); |
| 913 | /* turn on UART */ |
| 914 | outb(UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2, io + UART_MCR); |
| 915 | #ifdef LIRC_SIR_ACTISYS_ACT200L |
| 916 | init_act200(); |
| 917 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) |
| 918 | init_act220(); |
| 919 | #endif |
| 920 | #endif |
| 921 | spin_unlock_irqrestore(&hardware_lock, flags); |
| 922 | return 0; |
| 923 | } |
| 924 | |
| 925 | static void drop_hardware(void) |
| 926 | { |
| 927 | unsigned long flags; |
| 928 | |
| 929 | spin_lock_irqsave(&hardware_lock, flags); |
| 930 | |
| 931 | #ifdef LIRC_ON_SA1100 |
| 932 | Ser2UTCR3 = 0; |
| 933 | |
| 934 | Ser2UTCR0 = sr.utcr0; |
| 935 | Ser2UTCR1 = sr.utcr1; |
| 936 | Ser2UTCR2 = sr.utcr2; |
| 937 | Ser2UTCR4 = sr.utcr4; |
| 938 | Ser2UTCR3 = sr.utcr3; |
| 939 | |
| 940 | Ser2HSCR0 = sr.hscr0; |
| 941 | #ifdef CONFIG_SA1100_BITSY |
| 942 | if (machine_is_bitsy()) |
| 943 | clr_bitsy_egpio(EGPIO_BITSY_IR_ON); |
| 944 | #endif |
| 945 | #ifdef CONFIG_SA1100_COLLIE |
| 946 | sa1100_irda_set_power_collie(0); /* power off */ |
| 947 | #endif |
| 948 | #else |
| 949 | /* turn off interrupts */ |
| 950 | outb(0, io + UART_IER); |
| 951 | #endif |
| 952 | spin_unlock_irqrestore(&hardware_lock, flags); |
| 953 | } |
| 954 | |
| 955 | /* SECTION: Initialisation */ |
| 956 | |
| 957 | static int init_port(void) |
| 958 | { |
| 959 | int retval; |
| 960 | |
| 961 | /* get I/O port access and IRQ line */ |
| 962 | #ifndef LIRC_ON_SA1100 |
| 963 | if (request_region(io, 8, LIRC_DRIVER_NAME) == NULL) { |
| 964 | printk(KERN_ERR LIRC_DRIVER_NAME |
| 965 | ": i/o port 0x%.4x already in use.\n", io); |
| 966 | return -EBUSY; |
| 967 | } |
| 968 | #endif |
Yong Zhang | 18e9351 | 2011-09-07 16:10:22 +0800 | [diff] [blame] | 969 | retval = request_irq(irq, sir_interrupt, 0, |
Jarod Wilson | 404f3e9 | 2010-07-26 20:32:03 -0300 | [diff] [blame] | 970 | LIRC_DRIVER_NAME, NULL); |
| 971 | if (retval < 0) { |
| 972 | # ifndef LIRC_ON_SA1100 |
| 973 | release_region(io, 8); |
| 974 | # endif |
| 975 | printk(KERN_ERR LIRC_DRIVER_NAME |
| 976 | ": IRQ %d already in use.\n", |
| 977 | irq); |
| 978 | return retval; |
| 979 | } |
| 980 | #ifndef LIRC_ON_SA1100 |
| 981 | printk(KERN_INFO LIRC_DRIVER_NAME |
| 982 | ": I/O port 0x%.4x, IRQ %d.\n", |
| 983 | io, irq); |
| 984 | #endif |
| 985 | |
| 986 | init_timer(&timerlist); |
| 987 | timerlist.function = sir_timeout; |
| 988 | timerlist.data = 0xabadcafe; |
| 989 | |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | static void drop_port(void) |
| 994 | { |
| 995 | free_irq(irq, NULL); |
| 996 | del_timer_sync(&timerlist); |
| 997 | #ifndef LIRC_ON_SA1100 |
| 998 | release_region(io, 8); |
| 999 | #endif |
| 1000 | } |
| 1001 | |
| 1002 | #ifdef LIRC_SIR_ACTISYS_ACT200L |
| 1003 | /* Crystal/Cirrus CS8130 IR transceiver, used in Actisys Act200L dongle */ |
| 1004 | /* some code borrowed from Linux IRDA driver */ |
| 1005 | |
| 1006 | /* Register 0: Control register #1 */ |
| 1007 | #define ACT200L_REG0 0x00 |
| 1008 | #define ACT200L_TXEN 0x01 /* Enable transmitter */ |
| 1009 | #define ACT200L_RXEN 0x02 /* Enable receiver */ |
| 1010 | #define ACT200L_ECHO 0x08 /* Echo control chars */ |
| 1011 | |
| 1012 | /* Register 1: Control register #2 */ |
| 1013 | #define ACT200L_REG1 0x10 |
| 1014 | #define ACT200L_LODB 0x01 /* Load new baud rate count value */ |
| 1015 | #define ACT200L_WIDE 0x04 /* Expand the maximum allowable pulse */ |
| 1016 | |
| 1017 | /* Register 3: Transmit mode register #2 */ |
| 1018 | #define ACT200L_REG3 0x30 |
| 1019 | #define ACT200L_B0 0x01 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ |
| 1020 | #define ACT200L_B1 0x02 /* DataBits, 0=6, 1=7, 2=8, 3=9(8P) */ |
| 1021 | #define ACT200L_CHSY 0x04 /* StartBit Synced 0=bittime, 1=startbit */ |
| 1022 | |
| 1023 | /* Register 4: Output Power register */ |
| 1024 | #define ACT200L_REG4 0x40 |
| 1025 | #define ACT200L_OP0 0x01 /* Enable LED1C output */ |
| 1026 | #define ACT200L_OP1 0x02 /* Enable LED2C output */ |
| 1027 | #define ACT200L_BLKR 0x04 |
| 1028 | |
| 1029 | /* Register 5: Receive Mode register */ |
| 1030 | #define ACT200L_REG5 0x50 |
| 1031 | #define ACT200L_RWIDL 0x01 /* fixed 1.6us pulse mode */ |
| 1032 | /*.. other various IRDA bit modes, and TV remote modes..*/ |
| 1033 | |
| 1034 | /* Register 6: Receive Sensitivity register #1 */ |
| 1035 | #define ACT200L_REG6 0x60 |
| 1036 | #define ACT200L_RS0 0x01 /* receive threshold bit 0 */ |
| 1037 | #define ACT200L_RS1 0x02 /* receive threshold bit 1 */ |
| 1038 | |
| 1039 | /* Register 7: Receive Sensitivity register #2 */ |
| 1040 | #define ACT200L_REG7 0x70 |
| 1041 | #define ACT200L_ENPOS 0x04 /* Ignore the falling edge */ |
| 1042 | |
| 1043 | /* Register 8,9: Baud Rate Divider register #1,#2 */ |
| 1044 | #define ACT200L_REG8 0x80 |
| 1045 | #define ACT200L_REG9 0x90 |
| 1046 | |
| 1047 | #define ACT200L_2400 0x5f |
| 1048 | #define ACT200L_9600 0x17 |
| 1049 | #define ACT200L_19200 0x0b |
| 1050 | #define ACT200L_38400 0x05 |
| 1051 | #define ACT200L_57600 0x03 |
| 1052 | #define ACT200L_115200 0x01 |
| 1053 | |
| 1054 | /* Register 13: Control register #3 */ |
| 1055 | #define ACT200L_REG13 0xd0 |
| 1056 | #define ACT200L_SHDW 0x01 /* Enable access to shadow registers */ |
| 1057 | |
| 1058 | /* Register 15: Status register */ |
| 1059 | #define ACT200L_REG15 0xf0 |
| 1060 | |
| 1061 | /* Register 21: Control register #4 */ |
| 1062 | #define ACT200L_REG21 0x50 |
| 1063 | #define ACT200L_EXCK 0x02 /* Disable clock output driver */ |
| 1064 | #define ACT200L_OSCL 0x04 /* oscillator in low power, medium accuracy mode */ |
| 1065 | |
| 1066 | static void init_act200(void) |
| 1067 | { |
| 1068 | int i; |
| 1069 | __u8 control[] = { |
| 1070 | ACT200L_REG15, |
| 1071 | ACT200L_REG13 | ACT200L_SHDW, |
| 1072 | ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL, |
| 1073 | ACT200L_REG13, |
| 1074 | ACT200L_REG7 | ACT200L_ENPOS, |
| 1075 | ACT200L_REG6 | ACT200L_RS0 | ACT200L_RS1, |
| 1076 | ACT200L_REG5 | ACT200L_RWIDL, |
| 1077 | ACT200L_REG4 | ACT200L_OP0 | ACT200L_OP1 | ACT200L_BLKR, |
| 1078 | ACT200L_REG3 | ACT200L_B0, |
| 1079 | ACT200L_REG0 | ACT200L_TXEN | ACT200L_RXEN, |
| 1080 | ACT200L_REG8 | (ACT200L_115200 & 0x0f), |
| 1081 | ACT200L_REG9 | ((ACT200L_115200 >> 4) & 0x0f), |
| 1082 | ACT200L_REG1 | ACT200L_LODB | ACT200L_WIDE |
| 1083 | }; |
| 1084 | |
| 1085 | /* Set DLAB 1. */ |
| 1086 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); |
| 1087 | |
| 1088 | /* Set divisor to 12 => 9600 Baud */ |
| 1089 | soutp(UART_DLM, 0); |
| 1090 | soutp(UART_DLL, 12); |
| 1091 | |
| 1092 | /* Set DLAB 0. */ |
| 1093 | soutp(UART_LCR, UART_LCR_WLEN8); |
| 1094 | /* Set divisor to 12 => 9600 Baud */ |
| 1095 | |
| 1096 | /* power supply */ |
| 1097 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 1098 | for (i = 0; i < 50; i++) |
| 1099 | safe_udelay(1000); |
| 1100 | |
| 1101 | /* Reset the dongle : set RTS low for 25 ms */ |
| 1102 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); |
| 1103 | for (i = 0; i < 25; i++) |
| 1104 | udelay(1000); |
| 1105 | |
| 1106 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 1107 | udelay(100); |
| 1108 | |
| 1109 | /* Clear DTR and set RTS to enter command mode */ |
| 1110 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); |
| 1111 | udelay(7); |
| 1112 | |
| 1113 | /* send out the control register settings for 115K 7N1 SIR operation */ |
| 1114 | for (i = 0; i < sizeof(control); i++) { |
| 1115 | soutp(UART_TX, control[i]); |
| 1116 | /* one byte takes ~1042 usec to transmit at 9600,8N1 */ |
| 1117 | udelay(1500); |
| 1118 | } |
| 1119 | |
| 1120 | /* back to normal operation */ |
| 1121 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 1122 | udelay(50); |
| 1123 | |
| 1124 | udelay(1500); |
| 1125 | soutp(UART_LCR, sinp(UART_LCR) | UART_LCR_DLAB); |
| 1126 | |
| 1127 | /* Set DLAB 1. */ |
| 1128 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); |
| 1129 | |
| 1130 | /* Set divisor to 1 => 115200 Baud */ |
| 1131 | soutp(UART_DLM, 0); |
| 1132 | soutp(UART_DLL, 1); |
| 1133 | |
| 1134 | /* Set DLAB 0. */ |
| 1135 | soutp(UART_LCR, sinp(UART_LCR) & (~UART_LCR_DLAB)); |
| 1136 | |
| 1137 | /* Set DLAB 0, 7 Bit */ |
| 1138 | soutp(UART_LCR, UART_LCR_WLEN7); |
| 1139 | |
| 1140 | /* enable interrupts */ |
| 1141 | soutp(UART_IER, sinp(UART_IER)|UART_IER_RDI); |
| 1142 | } |
| 1143 | #endif |
| 1144 | |
| 1145 | #ifdef LIRC_SIR_ACTISYS_ACT220L |
| 1146 | /* |
| 1147 | * Derived from linux IrDA driver (net/irda/actisys.c) |
| 1148 | * Drop me a mail for any kind of comment: maxx@spaceboyz.net |
| 1149 | */ |
| 1150 | |
| 1151 | void init_act220(void) |
| 1152 | { |
| 1153 | int i; |
| 1154 | |
| 1155 | /* DLAB 1 */ |
| 1156 | soutp(UART_LCR, UART_LCR_DLAB|UART_LCR_WLEN7); |
| 1157 | |
| 1158 | /* 9600 baud */ |
| 1159 | soutp(UART_DLM, 0); |
| 1160 | soutp(UART_DLL, 12); |
| 1161 | |
| 1162 | /* DLAB 0 */ |
| 1163 | soutp(UART_LCR, UART_LCR_WLEN7); |
| 1164 | |
| 1165 | /* reset the dongle, set DTR low for 10us */ |
| 1166 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_OUT2); |
| 1167 | udelay(10); |
| 1168 | |
| 1169 | /* back to normal (still 9600) */ |
| 1170 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_RTS|UART_MCR_OUT2); |
| 1171 | |
| 1172 | /* |
| 1173 | * send RTS pulses until we reach 115200 |
| 1174 | * i hope this is really the same for act220l/act220l+ |
| 1175 | */ |
| 1176 | for (i = 0; i < 3; i++) { |
| 1177 | udelay(10); |
| 1178 | /* set RTS low for 10 us */ |
| 1179 | soutp(UART_MCR, UART_MCR_DTR|UART_MCR_OUT2); |
| 1180 | udelay(10); |
| 1181 | /* set RTS high for 10 us */ |
| 1182 | soutp(UART_MCR, UART_MCR_RTS|UART_MCR_DTR|UART_MCR_OUT2); |
| 1183 | } |
| 1184 | |
| 1185 | /* back to normal operation */ |
| 1186 | udelay(1500); /* better safe than sorry ;) */ |
| 1187 | |
| 1188 | /* Set DLAB 1. */ |
| 1189 | soutp(UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN7); |
| 1190 | |
| 1191 | /* Set divisor to 1 => 115200 Baud */ |
| 1192 | soutp(UART_DLM, 0); |
| 1193 | soutp(UART_DLL, 1); |
| 1194 | |
| 1195 | /* Set DLAB 0, 7 Bit */ |
| 1196 | /* The dongle doesn't seem to have any problems with operation at 7N1 */ |
| 1197 | soutp(UART_LCR, UART_LCR_WLEN7); |
| 1198 | |
| 1199 | /* enable interrupts */ |
| 1200 | soutp(UART_IER, UART_IER_RDI); |
| 1201 | } |
| 1202 | #endif |
| 1203 | |
| 1204 | static int init_lirc_sir(void) |
| 1205 | { |
| 1206 | int retval; |
| 1207 | |
| 1208 | init_waitqueue_head(&lirc_read_queue); |
| 1209 | retval = init_port(); |
| 1210 | if (retval < 0) |
| 1211 | return retval; |
| 1212 | init_hardware(); |
| 1213 | printk(KERN_INFO LIRC_DRIVER_NAME |
| 1214 | ": Installed.\n"); |
| 1215 | return 0; |
| 1216 | } |
| 1217 | |
| 1218 | |
| 1219 | static int __init lirc_sir_init(void) |
| 1220 | { |
| 1221 | int retval; |
| 1222 | |
| 1223 | retval = init_chrdev(); |
| 1224 | if (retval < 0) |
| 1225 | return retval; |
| 1226 | retval = init_lirc_sir(); |
| 1227 | if (retval) { |
| 1228 | drop_chrdev(); |
| 1229 | return retval; |
| 1230 | } |
| 1231 | return 0; |
| 1232 | } |
| 1233 | |
| 1234 | static void __exit lirc_sir_exit(void) |
| 1235 | { |
| 1236 | drop_hardware(); |
| 1237 | drop_chrdev(); |
| 1238 | drop_port(); |
| 1239 | printk(KERN_INFO LIRC_DRIVER_NAME ": Uninstalled.\n"); |
| 1240 | } |
| 1241 | |
| 1242 | module_init(lirc_sir_init); |
| 1243 | module_exit(lirc_sir_exit); |
| 1244 | |
| 1245 | #ifdef LIRC_SIR_TEKRAM |
| 1246 | MODULE_DESCRIPTION("Infrared receiver driver for Tekram Irmate 210"); |
| 1247 | MODULE_AUTHOR("Christoph Bartelmus"); |
| 1248 | #elif defined(LIRC_ON_SA1100) |
| 1249 | MODULE_DESCRIPTION("LIRC driver for StrongARM SA1100 embedded microprocessor"); |
| 1250 | MODULE_AUTHOR("Christoph Bartelmus"); |
| 1251 | #elif defined(LIRC_SIR_ACTISYS_ACT200L) |
| 1252 | MODULE_DESCRIPTION("LIRC driver for Actisys Act200L"); |
| 1253 | MODULE_AUTHOR("Karl Bongers"); |
| 1254 | #elif defined(LIRC_SIR_ACTISYS_ACT220L) |
| 1255 | MODULE_DESCRIPTION("LIRC driver for Actisys Act220L(+)"); |
| 1256 | MODULE_AUTHOR("Jan Roemisch"); |
| 1257 | #else |
| 1258 | MODULE_DESCRIPTION("Infrared receiver driver for SIR type serial ports"); |
| 1259 | MODULE_AUTHOR("Milan Pikula"); |
| 1260 | #endif |
| 1261 | MODULE_LICENSE("GPL"); |
| 1262 | |
| 1263 | #ifdef LIRC_ON_SA1100 |
| 1264 | module_param(irq, int, S_IRUGO); |
| 1265 | MODULE_PARM_DESC(irq, "Interrupt (16)"); |
| 1266 | #else |
| 1267 | module_param(io, int, S_IRUGO); |
| 1268 | MODULE_PARM_DESC(io, "I/O address base (0x3f8 or 0x2f8)"); |
| 1269 | |
| 1270 | module_param(irq, int, S_IRUGO); |
| 1271 | MODULE_PARM_DESC(irq, "Interrupt (4 or 3)"); |
| 1272 | |
| 1273 | module_param(threshold, int, S_IRUGO); |
| 1274 | MODULE_PARM_DESC(threshold, "space detection threshold (3)"); |
| 1275 | #endif |
| 1276 | |
| 1277 | module_param(debug, bool, S_IRUGO | S_IWUSR); |
| 1278 | MODULE_PARM_DESC(debug, "Enable debugging messages"); |