| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-integrator/include/mach/irqs.h |
| 3 | * |
| 4 | * Copyright (C) 1999 ARM Limited |
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| Linus Walleij | da72a66 | 2012-10-27 01:24:29 +0200 | [diff] [blame] | 22 | /* |
| 23 | * Interrupt numbers, all of the above are just static reservations |
| 24 | * used so they can be encoded into device resources. They will finally |
| 25 | * be done away with when switching to device tree. |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 26 | */ |
| Linus Walleij | da72a66 | 2012-10-27 01:24:29 +0200 | [diff] [blame] | 27 | #define IRQ_PIC_START 64 |
| 28 | #define IRQ_SOFTINT (IRQ_PIC_START+0) |
| 29 | #define IRQ_UARTINT0 (IRQ_PIC_START+1) |
| 30 | #define IRQ_UARTINT1 (IRQ_PIC_START+2) |
| 31 | #define IRQ_KMIINT0 (IRQ_PIC_START+3) |
| 32 | #define IRQ_KMIINT1 (IRQ_PIC_START+4) |
| 33 | #define IRQ_TIMERINT0 (IRQ_PIC_START+5) |
| 34 | #define IRQ_TIMERINT1 (IRQ_PIC_START+6) |
| 35 | #define IRQ_TIMERINT2 (IRQ_PIC_START+7) |
| 36 | #define IRQ_RTCINT (IRQ_PIC_START+8) |
| 37 | #define IRQ_AP_EXPINT0 (IRQ_PIC_START+9) |
| 38 | #define IRQ_AP_EXPINT1 (IRQ_PIC_START+10) |
| 39 | #define IRQ_AP_EXPINT2 (IRQ_PIC_START+11) |
| 40 | #define IRQ_AP_EXPINT3 (IRQ_PIC_START+12) |
| 41 | #define IRQ_AP_PCIINT0 (IRQ_PIC_START+13) |
| 42 | #define IRQ_AP_PCIINT1 (IRQ_PIC_START+14) |
| 43 | #define IRQ_AP_PCIINT2 (IRQ_PIC_START+15) |
| 44 | #define IRQ_AP_PCIINT3 (IRQ_PIC_START+16) |
| 45 | #define IRQ_AP_V3INT (IRQ_PIC_START+17) |
| 46 | #define IRQ_AP_CPINT0 (IRQ_PIC_START+18) |
| 47 | #define IRQ_AP_CPINT1 (IRQ_PIC_START+19) |
| 48 | #define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20) |
| 49 | #define IRQ_AP_APCINT (IRQ_PIC_START+21) |
| 50 | #define IRQ_CP_CLCDCINT (IRQ_PIC_START+22) |
| 51 | #define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23) |
| 52 | #define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24) |
| 53 | #define IRQ_CP_AACIINT (IRQ_PIC_START+25) |
| 54 | #define IRQ_CP_CPPLDINT (IRQ_PIC_START+26) |
| 55 | #define IRQ_CP_ETHINT (IRQ_PIC_START+27) |
| 56 | #define IRQ_CP_TSPENINT (IRQ_PIC_START+28) |
| 57 | #define IRQ_PIC_END (IRQ_PIC_START+28) |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 58 | |
| Linus Walleij | da72a66 | 2012-10-27 01:24:29 +0200 | [diff] [blame] | 59 | #define IRQ_CIC_START (IRQ_PIC_END+1) |
| 60 | #define IRQ_CM_SOFTINT (IRQ_CIC_START+0) |
| 61 | #define IRQ_CM_COMMRX (IRQ_CIC_START+1) |
| 62 | #define IRQ_CM_COMMTX (IRQ_CIC_START+2) |
| 63 | #define IRQ_CIC_END (IRQ_CIC_START+2) |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 64 | |
| 65 | /* |
| 66 | * IntegratorCP only |
| 67 | */ |
| Linus Walleij | da72a66 | 2012-10-27 01:24:29 +0200 | [diff] [blame] | 68 | #define IRQ_SIC_START (IRQ_CIC_END+1) |
| 69 | #define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0) |
| 70 | #define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1) |
| 71 | #define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2) |
| 72 | #define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3) |
| 73 | #define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4) |
| 74 | #define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5) |
| 75 | #define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6) |
| 76 | #define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7) |
| 77 | #define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8) |
| 78 | #define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9) |
| 79 | #define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10) |
| 80 | #define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11) |
| 81 | #define IRQ_SIC_END (IRQ_SIC_START+11) |