Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 1 | /* |
| 2 | Driver for M88RS2000 demodulator and tuner |
| 3 | |
| 4 | Copyright (C) 2012 Malcolm Priestley (tvboxspy@gmail.com) |
| 5 | Beta Driver |
| 6 | |
| 7 | Include various calculation code from DS3000 driver. |
| 8 | Copyright (C) 2009 Konstantin Dimitrov. |
| 9 | |
| 10 | This program is free software; you can redistribute it and/or modify |
| 11 | it under the terms of the GNU General Public License as published by |
| 12 | the Free Software Foundation; either version 2 of the License, or |
| 13 | (at your option) any later version. |
| 14 | |
| 15 | This program is distributed in the hope that it will be useful, |
| 16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | GNU General Public License for more details. |
| 19 | |
| 20 | You should have received a copy of the GNU General Public License |
| 21 | along with this program; if not, write to the Free Software |
| 22 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 23 | |
| 24 | */ |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/device.h> |
| 28 | #include <linux/jiffies.h> |
| 29 | #include <linux/string.h> |
| 30 | #include <linux/slab.h> |
| 31 | #include <linux/types.h> |
| 32 | |
| 33 | |
| 34 | #include "dvb_frontend.h" |
| 35 | #include "m88rs2000.h" |
| 36 | |
| 37 | struct m88rs2000_state { |
| 38 | struct i2c_adapter *i2c; |
| 39 | const struct m88rs2000_config *config; |
| 40 | struct dvb_frontend frontend; |
| 41 | u8 no_lock_count; |
| 42 | u32 tuner_frequency; |
| 43 | u32 symbol_rate; |
| 44 | fe_code_rate_t fec_inner; |
| 45 | u8 tuner_level; |
| 46 | int errmode; |
| 47 | }; |
| 48 | |
| 49 | static int m88rs2000_debug; |
| 50 | |
| 51 | module_param_named(debug, m88rs2000_debug, int, 0644); |
| 52 | MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able))."); |
| 53 | |
| 54 | #define dprintk(level, args...) do { \ |
| 55 | if (level & m88rs2000_debug) \ |
| 56 | printk(KERN_DEBUG "m88rs2000-fe: " args); \ |
| 57 | } while (0) |
| 58 | |
| 59 | #define deb_info(args...) dprintk(0x01, args) |
| 60 | #define info(format, arg...) \ |
| 61 | printk(KERN_INFO "m88rs2000-fe: " format "\n" , ## arg) |
| 62 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 63 | static int m88rs2000_writereg(struct m88rs2000_state *state, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 64 | u8 reg, u8 data) |
| 65 | { |
| 66 | int ret; |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 67 | u8 buf[] = { reg, data }; |
| 68 | struct i2c_msg msg = { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 69 | .addr = state->config->demod_addr, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 70 | .flags = 0, |
| 71 | .buf = buf, |
| 72 | .len = 2 |
| 73 | }; |
| 74 | |
| 75 | ret = i2c_transfer(state->i2c, &msg, 1); |
| 76 | |
| 77 | if (ret != 1) |
| 78 | deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, " |
| 79 | "ret == %i)\n", __func__, reg, data, ret); |
| 80 | |
| 81 | return (ret != 1) ? -EREMOTEIO : 0; |
| 82 | } |
| 83 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 84 | static u8 m88rs2000_readreg(struct m88rs2000_state *state, u8 reg) |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 85 | { |
| 86 | int ret; |
| 87 | u8 b0[] = { reg }; |
| 88 | u8 b1[] = { 0 }; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 89 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 90 | struct i2c_msg msg[] = { |
| 91 | { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 92 | .addr = state->config->demod_addr, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 93 | .flags = 0, |
| 94 | .buf = b0, |
| 95 | .len = 1 |
| 96 | }, { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 97 | .addr = state->config->demod_addr, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 98 | .flags = I2C_M_RD, |
| 99 | .buf = b1, |
| 100 | .len = 1 |
| 101 | } |
| 102 | }; |
| 103 | |
| 104 | ret = i2c_transfer(state->i2c, msg, 2); |
| 105 | |
| 106 | if (ret != 2) |
| 107 | deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n", |
| 108 | __func__, reg, ret); |
| 109 | |
| 110 | return b1[0]; |
| 111 | } |
| 112 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 113 | static int m88rs2000_set_symbolrate(struct dvb_frontend *fe, u32 srate) |
| 114 | { |
| 115 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 116 | int ret; |
| 117 | u32 temp; |
| 118 | u8 b[3]; |
| 119 | |
| 120 | if ((srate < 1000000) || (srate > 45000000)) |
| 121 | return -EINVAL; |
| 122 | |
| 123 | temp = srate / 1000; |
| 124 | temp *= 11831; |
| 125 | temp /= 68; |
| 126 | temp -= 3; |
| 127 | |
| 128 | b[0] = (u8) (temp >> 16) & 0xff; |
| 129 | b[1] = (u8) (temp >> 8) & 0xff; |
| 130 | b[2] = (u8) temp & 0xff; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 131 | ret = m88rs2000_writereg(state, 0x93, b[2]); |
| 132 | ret |= m88rs2000_writereg(state, 0x94, b[1]); |
| 133 | ret |= m88rs2000_writereg(state, 0x95, b[0]); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 134 | |
| 135 | deb_info("m88rs2000: m88rs2000_set_symbolrate\n"); |
| 136 | return ret; |
| 137 | } |
| 138 | |
| 139 | static int m88rs2000_send_diseqc_msg(struct dvb_frontend *fe, |
| 140 | struct dvb_diseqc_master_cmd *m) |
| 141 | { |
| 142 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 143 | |
| 144 | int i; |
| 145 | u8 reg; |
| 146 | deb_info("%s\n", __func__); |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 147 | m88rs2000_writereg(state, 0x9a, 0x30); |
| 148 | reg = m88rs2000_readreg(state, 0xb2); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 149 | reg &= 0x3f; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 150 | m88rs2000_writereg(state, 0xb2, reg); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 151 | for (i = 0; i < m->msg_len; i++) |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 152 | m88rs2000_writereg(state, 0xb3 + i, m->msg[i]); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 153 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 154 | reg = m88rs2000_readreg(state, 0xb1); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 155 | reg &= 0x87; |
| 156 | reg |= ((m->msg_len - 1) << 3) | 0x07; |
| 157 | reg &= 0x7f; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 158 | m88rs2000_writereg(state, 0xb1, reg); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 159 | |
| 160 | for (i = 0; i < 15; i++) { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 161 | if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0) |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 162 | break; |
| 163 | msleep(20); |
| 164 | } |
| 165 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 166 | reg = m88rs2000_readreg(state, 0xb1); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 167 | if ((reg & 0x40) > 0x0) { |
| 168 | reg &= 0x7f; |
| 169 | reg |= 0x40; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 170 | m88rs2000_writereg(state, 0xb1, reg); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 171 | } |
| 172 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 173 | reg = m88rs2000_readreg(state, 0xb2); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 174 | reg &= 0x3f; |
| 175 | reg |= 0x80; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 176 | m88rs2000_writereg(state, 0xb2, reg); |
| 177 | m88rs2000_writereg(state, 0x9a, 0xb0); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 178 | |
| 179 | |
| 180 | return 0; |
| 181 | } |
| 182 | |
| 183 | static int m88rs2000_send_diseqc_burst(struct dvb_frontend *fe, |
| 184 | fe_sec_mini_cmd_t burst) |
| 185 | { |
| 186 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 187 | u8 reg0, reg1; |
| 188 | deb_info("%s\n", __func__); |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 189 | m88rs2000_writereg(state, 0x9a, 0x30); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 190 | msleep(50); |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 191 | reg0 = m88rs2000_readreg(state, 0xb1); |
| 192 | reg1 = m88rs2000_readreg(state, 0xb2); |
Malcolm Priestley | 593a2ce0 | 2012-03-14 16:31:26 -0300 | [diff] [blame] | 193 | /* TODO complete this section */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 194 | m88rs2000_writereg(state, 0xb2, reg1); |
| 195 | m88rs2000_writereg(state, 0xb1, reg0); |
| 196 | m88rs2000_writereg(state, 0x9a, 0xb0); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | static int m88rs2000_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone) |
| 202 | { |
| 203 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 204 | u8 reg0, reg1; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 205 | m88rs2000_writereg(state, 0x9a, 0x30); |
| 206 | reg0 = m88rs2000_readreg(state, 0xb1); |
| 207 | reg1 = m88rs2000_readreg(state, 0xb2); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 208 | |
| 209 | reg1 &= 0x3f; |
| 210 | |
| 211 | switch (tone) { |
| 212 | case SEC_TONE_ON: |
| 213 | reg0 |= 0x4; |
| 214 | reg0 &= 0xbc; |
Malcolm Priestley | 593a2ce0 | 2012-03-14 16:31:26 -0300 | [diff] [blame] | 215 | break; |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 216 | case SEC_TONE_OFF: |
| 217 | reg1 |= 0x80; |
Malcolm Priestley | 593a2ce0 | 2012-03-14 16:31:26 -0300 | [diff] [blame] | 218 | break; |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 219 | default: |
Malcolm Priestley | 593a2ce0 | 2012-03-14 16:31:26 -0300 | [diff] [blame] | 220 | break; |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 221 | } |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 222 | m88rs2000_writereg(state, 0xb2, reg1); |
| 223 | m88rs2000_writereg(state, 0xb1, reg0); |
| 224 | m88rs2000_writereg(state, 0x9a, 0xb0); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 225 | return 0; |
| 226 | } |
| 227 | |
| 228 | struct inittab { |
| 229 | u8 cmd; |
| 230 | u8 reg; |
| 231 | u8 val; |
| 232 | }; |
| 233 | |
| 234 | struct inittab m88rs2000_setup[] = { |
| 235 | {DEMOD_WRITE, 0x9a, 0x30}, |
| 236 | {DEMOD_WRITE, 0x00, 0x01}, |
| 237 | {WRITE_DELAY, 0x19, 0x00}, |
| 238 | {DEMOD_WRITE, 0x00, 0x00}, |
| 239 | {DEMOD_WRITE, 0x9a, 0xb0}, |
| 240 | {DEMOD_WRITE, 0x81, 0xc1}, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 241 | {DEMOD_WRITE, 0x81, 0x81}, |
| 242 | {DEMOD_WRITE, 0x86, 0xc6}, |
| 243 | {DEMOD_WRITE, 0x9a, 0x30}, |
| 244 | {DEMOD_WRITE, 0xf0, 0x22}, |
| 245 | {DEMOD_WRITE, 0xf1, 0xbf}, |
| 246 | {DEMOD_WRITE, 0xb0, 0x45}, |
Malcolm Priestley | 593a2ce0 | 2012-03-14 16:31:26 -0300 | [diff] [blame] | 247 | {DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/ |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 248 | {DEMOD_WRITE, 0x9a, 0xb0}, |
| 249 | {0xff, 0xaa, 0xff} |
| 250 | }; |
| 251 | |
| 252 | struct inittab m88rs2000_shutdown[] = { |
| 253 | {DEMOD_WRITE, 0x9a, 0x30}, |
| 254 | {DEMOD_WRITE, 0xb0, 0x00}, |
| 255 | {DEMOD_WRITE, 0xf1, 0x89}, |
| 256 | {DEMOD_WRITE, 0x00, 0x01}, |
| 257 | {DEMOD_WRITE, 0x9a, 0xb0}, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 258 | {DEMOD_WRITE, 0x81, 0x81}, |
| 259 | {0xff, 0xaa, 0xff} |
| 260 | }; |
| 261 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 262 | struct inittab fe_reset[] = { |
| 263 | {DEMOD_WRITE, 0x00, 0x01}, |
| 264 | {DEMOD_WRITE, 0xf1, 0xbf}, |
| 265 | {DEMOD_WRITE, 0x00, 0x01}, |
| 266 | {DEMOD_WRITE, 0x20, 0x81}, |
| 267 | {DEMOD_WRITE, 0x21, 0x80}, |
| 268 | {DEMOD_WRITE, 0x10, 0x33}, |
| 269 | {DEMOD_WRITE, 0x11, 0x44}, |
| 270 | {DEMOD_WRITE, 0x12, 0x07}, |
| 271 | {DEMOD_WRITE, 0x18, 0x20}, |
| 272 | {DEMOD_WRITE, 0x28, 0x04}, |
| 273 | {DEMOD_WRITE, 0x29, 0x8e}, |
| 274 | {DEMOD_WRITE, 0x3b, 0xff}, |
| 275 | {DEMOD_WRITE, 0x32, 0x10}, |
| 276 | {DEMOD_WRITE, 0x33, 0x02}, |
| 277 | {DEMOD_WRITE, 0x34, 0x30}, |
| 278 | {DEMOD_WRITE, 0x35, 0xff}, |
| 279 | {DEMOD_WRITE, 0x38, 0x50}, |
| 280 | {DEMOD_WRITE, 0x39, 0x68}, |
| 281 | {DEMOD_WRITE, 0x3c, 0x7f}, |
| 282 | {DEMOD_WRITE, 0x3d, 0x0f}, |
| 283 | {DEMOD_WRITE, 0x45, 0x20}, |
| 284 | {DEMOD_WRITE, 0x46, 0x24}, |
| 285 | {DEMOD_WRITE, 0x47, 0x7c}, |
| 286 | {DEMOD_WRITE, 0x48, 0x16}, |
| 287 | {DEMOD_WRITE, 0x49, 0x04}, |
| 288 | {DEMOD_WRITE, 0x4a, 0x01}, |
| 289 | {DEMOD_WRITE, 0x4b, 0x78}, |
| 290 | {DEMOD_WRITE, 0X4d, 0xd2}, |
| 291 | {DEMOD_WRITE, 0x4e, 0x6d}, |
| 292 | {DEMOD_WRITE, 0x50, 0x30}, |
| 293 | {DEMOD_WRITE, 0x51, 0x30}, |
| 294 | {DEMOD_WRITE, 0x54, 0x7b}, |
| 295 | {DEMOD_WRITE, 0x56, 0x09}, |
| 296 | {DEMOD_WRITE, 0x58, 0x59}, |
| 297 | {DEMOD_WRITE, 0x59, 0x37}, |
| 298 | {DEMOD_WRITE, 0x63, 0xfa}, |
| 299 | {0xff, 0xaa, 0xff} |
| 300 | }; |
| 301 | |
| 302 | struct inittab fe_trigger[] = { |
| 303 | {DEMOD_WRITE, 0x97, 0x04}, |
| 304 | {DEMOD_WRITE, 0x99, 0x77}, |
| 305 | {DEMOD_WRITE, 0x9b, 0x64}, |
| 306 | {DEMOD_WRITE, 0x9e, 0x00}, |
| 307 | {DEMOD_WRITE, 0x9f, 0xf8}, |
| 308 | {DEMOD_WRITE, 0xa0, 0x20}, |
| 309 | {DEMOD_WRITE, 0xa1, 0xe0}, |
| 310 | {DEMOD_WRITE, 0xa3, 0x38}, |
| 311 | {DEMOD_WRITE, 0x98, 0xff}, |
| 312 | {DEMOD_WRITE, 0xc0, 0x0f}, |
| 313 | {DEMOD_WRITE, 0x89, 0x01}, |
| 314 | {DEMOD_WRITE, 0x00, 0x00}, |
| 315 | {WRITE_DELAY, 0x0a, 0x00}, |
| 316 | {DEMOD_WRITE, 0x00, 0x01}, |
| 317 | {DEMOD_WRITE, 0x00, 0x00}, |
| 318 | {DEMOD_WRITE, 0x9a, 0xb0}, |
| 319 | {0xff, 0xaa, 0xff} |
| 320 | }; |
| 321 | |
| 322 | static int m88rs2000_tab_set(struct m88rs2000_state *state, |
| 323 | struct inittab *tab) |
| 324 | { |
| 325 | int ret = 0; |
| 326 | u8 i; |
| 327 | if (tab == NULL) |
| 328 | return -EINVAL; |
| 329 | |
| 330 | for (i = 0; i < 255; i++) { |
| 331 | switch (tab[i].cmd) { |
| 332 | case 0x01: |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 333 | ret = m88rs2000_writereg(state, tab[i].reg, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 334 | tab[i].val); |
| 335 | break; |
| 336 | case 0x10: |
| 337 | if (tab[i].reg > 0) |
| 338 | mdelay(tab[i].reg); |
| 339 | break; |
| 340 | case 0xff: |
| 341 | if (tab[i].reg == 0xaa && tab[i].val == 0xff) |
| 342 | return 0; |
| 343 | case 0x00: |
| 344 | break; |
| 345 | default: |
| 346 | return -EINVAL; |
| 347 | } |
| 348 | if (ret < 0) |
| 349 | return -ENODEV; |
| 350 | } |
| 351 | return 0; |
| 352 | } |
| 353 | |
| 354 | static int m88rs2000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t volt) |
| 355 | { |
Igor M. Liplianin | 38431a9 | 2012-05-08 04:25:24 -0300 | [diff] [blame] | 356 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 357 | u8 data; |
| 358 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 359 | data = m88rs2000_readreg(state, 0xb2); |
Igor M. Liplianin | 38431a9 | 2012-05-08 04:25:24 -0300 | [diff] [blame] | 360 | data |= 0x03; /* bit0 V/H, bit1 off/on */ |
| 361 | |
| 362 | switch (volt) { |
| 363 | case SEC_VOLTAGE_18: |
| 364 | data &= ~0x03; |
| 365 | break; |
| 366 | case SEC_VOLTAGE_13: |
| 367 | data &= ~0x03; |
| 368 | data |= 0x01; |
| 369 | break; |
| 370 | case SEC_VOLTAGE_OFF: |
| 371 | break; |
| 372 | } |
| 373 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 374 | m88rs2000_writereg(state, 0xb2, data); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 375 | |
| 376 | return 0; |
| 377 | } |
| 378 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 379 | static int m88rs2000_init(struct dvb_frontend *fe) |
| 380 | { |
| 381 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 382 | int ret; |
| 383 | |
| 384 | deb_info("m88rs2000: init chip\n"); |
| 385 | /* Setup frontend from shutdown/cold */ |
Igor M. Liplianin | 081416e | 2012-05-08 04:08:04 -0300 | [diff] [blame] | 386 | if (state->config->inittab) |
| 387 | ret = m88rs2000_tab_set(state, |
| 388 | (struct inittab *)state->config->inittab); |
| 389 | else |
| 390 | ret = m88rs2000_tab_set(state, m88rs2000_setup); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 391 | |
| 392 | return ret; |
| 393 | } |
| 394 | |
| 395 | static int m88rs2000_sleep(struct dvb_frontend *fe) |
| 396 | { |
| 397 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 398 | int ret; |
| 399 | /* Shutdown the frondend */ |
| 400 | ret = m88rs2000_tab_set(state, m88rs2000_shutdown); |
| 401 | return ret; |
| 402 | } |
| 403 | |
| 404 | static int m88rs2000_read_status(struct dvb_frontend *fe, fe_status_t *status) |
| 405 | { |
| 406 | struct m88rs2000_state *state = fe->demodulator_priv; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 407 | u8 reg = m88rs2000_readreg(state, 0x8c); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 408 | |
| 409 | *status = 0; |
| 410 | |
| 411 | if ((reg & 0x7) == 0x7) { |
| 412 | *status = FE_HAS_CARRIER | FE_HAS_SIGNAL | FE_HAS_VITERBI |
Antti Palosaari | ff54298 | 2012-08-06 18:35:26 -0300 | [diff] [blame] | 413 | | FE_HAS_SYNC | FE_HAS_LOCK; |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 414 | if (state->config->set_ts_params) |
| 415 | state->config->set_ts_params(fe, CALL_IS_READ); |
| 416 | } |
| 417 | return 0; |
| 418 | } |
| 419 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 420 | static int m88rs2000_read_ber(struct dvb_frontend *fe, u32 *ber) |
| 421 | { |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 422 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 423 | u8 tmp0, tmp1; |
| 424 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 425 | m88rs2000_writereg(state, 0x9a, 0x30); |
| 426 | tmp0 = m88rs2000_readreg(state, 0xd8); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 427 | if ((tmp0 & 0x10) != 0) { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 428 | m88rs2000_writereg(state, 0x9a, 0xb0); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 429 | *ber = 0xffffffff; |
| 430 | return 0; |
| 431 | } |
| 432 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 433 | *ber = (m88rs2000_readreg(state, 0xd7) << 8) | |
| 434 | m88rs2000_readreg(state, 0xd6); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 435 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 436 | tmp1 = m88rs2000_readreg(state, 0xd9); |
| 437 | m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 438 | /* needs twice */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 439 | m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30); |
| 440 | m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30); |
| 441 | m88rs2000_writereg(state, 0x9a, 0xb0); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 442 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 443 | return 0; |
| 444 | } |
| 445 | |
| 446 | static int m88rs2000_read_signal_strength(struct dvb_frontend *fe, |
| 447 | u16 *strength) |
| 448 | { |
Malcolm Priestley | a0a030b | 2013-01-06 08:40:42 -0300 | [diff] [blame] | 449 | if (fe->ops.tuner_ops.get_rf_strength) |
| 450 | fe->ops.tuner_ops.get_rf_strength(fe, strength); |
| 451 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | static int m88rs2000_read_snr(struct dvb_frontend *fe, u16 *snr) |
| 456 | { |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 457 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 458 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 459 | *snr = 512 * m88rs2000_readreg(state, 0x65); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 460 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 461 | return 0; |
| 462 | } |
| 463 | |
| 464 | static int m88rs2000_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) |
| 465 | { |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 466 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 467 | u8 tmp; |
| 468 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 469 | *ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) | |
| 470 | m88rs2000_readreg(state, 0xd4); |
| 471 | tmp = m88rs2000_readreg(state, 0xd8); |
| 472 | m88rs2000_writereg(state, 0xd8, tmp & ~0x20); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 473 | /* needs two times */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 474 | m88rs2000_writereg(state, 0xd8, tmp | 0x20); |
| 475 | m88rs2000_writereg(state, 0xd8, tmp | 0x20); |
Igor M. Liplianin | 38f7889 | 2012-12-28 19:40:16 -0300 | [diff] [blame] | 476 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 477 | return 0; |
| 478 | } |
| 479 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 480 | static int m88rs2000_set_fec(struct m88rs2000_state *state, |
| 481 | fe_code_rate_t fec) |
| 482 | { |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 483 | u16 fec_set; |
| 484 | switch (fec) { |
| 485 | /* This is not confirmed kept for reference */ |
| 486 | /* case FEC_1_2: |
| 487 | fec_set = 0x88; |
| 488 | break; |
| 489 | case FEC_2_3: |
| 490 | fec_set = 0x68; |
| 491 | break; |
| 492 | case FEC_3_4: |
| 493 | fec_set = 0x48; |
| 494 | break; |
| 495 | case FEC_5_6: |
| 496 | fec_set = 0x28; |
| 497 | break; |
| 498 | case FEC_7_8: |
| 499 | fec_set = 0x18; |
| 500 | break; */ |
| 501 | case FEC_AUTO: |
| 502 | default: |
| 503 | fec_set = 0x08; |
| 504 | } |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 505 | m88rs2000_writereg(state, 0x76, fec_set); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | |
| 511 | static fe_code_rate_t m88rs2000_get_fec(struct m88rs2000_state *state) |
| 512 | { |
| 513 | u8 reg; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 514 | m88rs2000_writereg(state, 0x9a, 0x30); |
| 515 | reg = m88rs2000_readreg(state, 0x76); |
| 516 | m88rs2000_writereg(state, 0x9a, 0xb0); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 517 | |
| 518 | switch (reg) { |
| 519 | case 0x88: |
| 520 | return FEC_1_2; |
| 521 | case 0x68: |
| 522 | return FEC_2_3; |
| 523 | case 0x48: |
| 524 | return FEC_3_4; |
| 525 | case 0x28: |
| 526 | return FEC_5_6; |
| 527 | case 0x18: |
| 528 | return FEC_7_8; |
| 529 | case 0x08: |
| 530 | default: |
| 531 | break; |
| 532 | } |
| 533 | |
| 534 | return FEC_AUTO; |
| 535 | } |
| 536 | |
| 537 | static int m88rs2000_set_frontend(struct dvb_frontend *fe) |
| 538 | { |
| 539 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 540 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
| 541 | fe_status_t status; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 542 | int i, ret = 0; |
| 543 | s32 tmp; |
| 544 | u32 tuner_freq; |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 545 | u16 offset = 0; |
| 546 | u8 reg; |
| 547 | |
| 548 | state->no_lock_count = 0; |
| 549 | |
| 550 | if (c->delivery_system != SYS_DVBS) { |
| 551 | deb_info("%s: unsupported delivery " |
| 552 | "system selected (%d)\n", |
| 553 | __func__, c->delivery_system); |
| 554 | return -EOPNOTSUPP; |
| 555 | } |
| 556 | |
| 557 | /* Set Tuner */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 558 | if (fe->ops.tuner_ops.set_params) |
| 559 | ret = fe->ops.tuner_ops.set_params(fe); |
| 560 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 561 | if (ret < 0) |
| 562 | return -ENODEV; |
| 563 | |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 564 | if (fe->ops.tuner_ops.get_frequency) |
| 565 | ret = fe->ops.tuner_ops.get_frequency(fe, &tuner_freq); |
| 566 | |
| 567 | if (ret < 0) |
| 568 | return -ENODEV; |
| 569 | |
| 570 | offset = tuner_freq - c->frequency; |
| 571 | |
| 572 | /* calculate offset assuming 96000kHz*/ |
| 573 | tmp = offset; |
| 574 | tmp *= 65536; |
| 575 | |
| 576 | tmp = (2 * tmp + 96000) / (2 * 96000); |
| 577 | if (tmp < 0) |
| 578 | tmp += 65536; |
| 579 | |
| 580 | offset = tmp & 0xffff; |
| 581 | |
| 582 | ret = m88rs2000_writereg(state, 0x9a, 0x30); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 583 | /* Unknown usually 0xc6 sometimes 0xc1 */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 584 | reg = m88rs2000_readreg(state, 0x86); |
| 585 | ret |= m88rs2000_writereg(state, 0x86, reg); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 586 | /* Offset lower nibble always 0 */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 587 | ret |= m88rs2000_writereg(state, 0x9c, (offset >> 8)); |
| 588 | ret |= m88rs2000_writereg(state, 0x9d, offset & 0xf0); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 589 | |
| 590 | |
| 591 | /* Reset Demod */ |
| 592 | ret = m88rs2000_tab_set(state, fe_reset); |
| 593 | if (ret < 0) |
| 594 | return -ENODEV; |
| 595 | |
| 596 | /* Unknown */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 597 | reg = m88rs2000_readreg(state, 0x70); |
| 598 | ret = m88rs2000_writereg(state, 0x70, reg); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 599 | |
| 600 | /* Set FEC */ |
| 601 | ret |= m88rs2000_set_fec(state, c->fec_inner); |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 602 | ret |= m88rs2000_writereg(state, 0x85, 0x1); |
| 603 | ret |= m88rs2000_writereg(state, 0x8a, 0xbf); |
| 604 | ret |= m88rs2000_writereg(state, 0x8d, 0x1e); |
| 605 | ret |= m88rs2000_writereg(state, 0x90, 0xf1); |
| 606 | ret |= m88rs2000_writereg(state, 0x91, 0x08); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 607 | |
| 608 | if (ret < 0) |
| 609 | return -ENODEV; |
| 610 | |
| 611 | /* Set Symbol Rate */ |
| 612 | ret = m88rs2000_set_symbolrate(fe, c->symbol_rate); |
| 613 | if (ret < 0) |
| 614 | return -ENODEV; |
| 615 | |
| 616 | /* Set up Demod */ |
| 617 | ret = m88rs2000_tab_set(state, fe_trigger); |
| 618 | if (ret < 0) |
| 619 | return -ENODEV; |
| 620 | |
| 621 | for (i = 0; i < 25; i++) { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 622 | reg = m88rs2000_readreg(state, 0x8c); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 623 | if ((reg & 0x7) == 0x7) { |
| 624 | status = FE_HAS_LOCK; |
| 625 | break; |
| 626 | } |
| 627 | state->no_lock_count++; |
Malcolm Priestley | e58c11f | 2012-05-14 16:43:50 -0300 | [diff] [blame] | 628 | if (state->no_lock_count == 15) { |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 629 | reg = m88rs2000_readreg(state, 0x70); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 630 | reg ^= 0x4; |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 631 | m88rs2000_writereg(state, 0x70, reg); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 632 | state->no_lock_count = 0; |
| 633 | } |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 634 | msleep(20); |
| 635 | } |
| 636 | |
| 637 | if (status & FE_HAS_LOCK) { |
| 638 | state->fec_inner = m88rs2000_get_fec(state); |
| 639 | /* Uknown suspect SNR level */ |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 640 | reg = m88rs2000_readreg(state, 0x65); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 641 | } |
| 642 | |
| 643 | state->tuner_frequency = c->frequency; |
| 644 | state->symbol_rate = c->symbol_rate; |
| 645 | return 0; |
| 646 | } |
| 647 | |
| 648 | static int m88rs2000_get_frontend(struct dvb_frontend *fe) |
| 649 | { |
| 650 | struct dtv_frontend_properties *c = &fe->dtv_property_cache; |
| 651 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 652 | c->fec_inner = state->fec_inner; |
| 653 | c->frequency = state->tuner_frequency; |
| 654 | c->symbol_rate = state->symbol_rate; |
| 655 | return 0; |
| 656 | } |
| 657 | |
| 658 | static int m88rs2000_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) |
| 659 | { |
| 660 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 661 | |
| 662 | if (enable) |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 663 | m88rs2000_writereg(state, 0x81, 0x84); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 664 | else |
Igor M. Liplianin | b858c33 | 2012-12-28 19:40:33 -0300 | [diff] [blame] | 665 | m88rs2000_writereg(state, 0x81, 0x81); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 666 | udelay(10); |
| 667 | return 0; |
| 668 | } |
| 669 | |
| 670 | static void m88rs2000_release(struct dvb_frontend *fe) |
| 671 | { |
| 672 | struct m88rs2000_state *state = fe->demodulator_priv; |
| 673 | kfree(state); |
| 674 | } |
| 675 | |
| 676 | static struct dvb_frontend_ops m88rs2000_ops = { |
| 677 | .delsys = { SYS_DVBS }, |
| 678 | .info = { |
| 679 | .name = "M88RS2000 DVB-S", |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 680 | .frequency_min = 950000, |
| 681 | .frequency_max = 2150000, |
| 682 | .frequency_stepsize = 1000, /* kHz for QPSK frontends */ |
| 683 | .frequency_tolerance = 5000, |
| 684 | .symbol_rate_min = 1000000, |
| 685 | .symbol_rate_max = 45000000, |
| 686 | .symbol_rate_tolerance = 500, /* ppm */ |
| 687 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
| 688 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | |
| 689 | FE_CAN_QPSK | |
| 690 | FE_CAN_FEC_AUTO |
| 691 | }, |
| 692 | |
| 693 | .release = m88rs2000_release, |
| 694 | .init = m88rs2000_init, |
| 695 | .sleep = m88rs2000_sleep, |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 696 | .i2c_gate_ctrl = m88rs2000_i2c_gate_ctrl, |
| 697 | .read_status = m88rs2000_read_status, |
| 698 | .read_ber = m88rs2000_read_ber, |
| 699 | .read_signal_strength = m88rs2000_read_signal_strength, |
| 700 | .read_snr = m88rs2000_read_snr, |
| 701 | .read_ucblocks = m88rs2000_read_ucblocks, |
| 702 | .diseqc_send_master_cmd = m88rs2000_send_diseqc_msg, |
| 703 | .diseqc_send_burst = m88rs2000_send_diseqc_burst, |
| 704 | .set_tone = m88rs2000_set_tone, |
| 705 | .set_voltage = m88rs2000_set_voltage, |
| 706 | |
| 707 | .set_frontend = m88rs2000_set_frontend, |
| 708 | .get_frontend = m88rs2000_get_frontend, |
| 709 | }; |
| 710 | |
| 711 | struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config, |
| 712 | struct i2c_adapter *i2c) |
| 713 | { |
| 714 | struct m88rs2000_state *state = NULL; |
| 715 | |
| 716 | /* allocate memory for the internal state */ |
| 717 | state = kzalloc(sizeof(struct m88rs2000_state), GFP_KERNEL); |
| 718 | if (state == NULL) |
| 719 | goto error; |
| 720 | |
| 721 | /* setup the state */ |
| 722 | state->config = config; |
| 723 | state->i2c = i2c; |
| 724 | state->tuner_frequency = 0; |
| 725 | state->symbol_rate = 0; |
| 726 | state->fec_inner = 0; |
| 727 | |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 728 | /* create dvb_frontend */ |
| 729 | memcpy(&state->frontend.ops, &m88rs2000_ops, |
| 730 | sizeof(struct dvb_frontend_ops)); |
| 731 | state->frontend.demodulator_priv = state; |
| 732 | return &state->frontend; |
| 733 | |
| 734 | error: |
| 735 | kfree(state); |
| 736 | |
| 737 | return NULL; |
| 738 | } |
| 739 | EXPORT_SYMBOL(m88rs2000_attach); |
| 740 | |
| 741 | MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver"); |
| 742 | MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); |
| 743 | MODULE_LICENSE("GPL"); |
Malcolm Priestley | 593a2ce0 | 2012-03-14 16:31:26 -0300 | [diff] [blame] | 744 | MODULE_VERSION("1.13"); |
Malcolm Priestley | ae8dc8ee | 2012-03-07 18:11:03 -0300 | [diff] [blame] | 745 | |