blob: 184bc9570b1c4b2b74c65240fea0516f46618b6b [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_i2c.h"
28#include "nouveau_encoder.h"
29
30static int
31auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
32{
33 struct drm_device *dev = encoder->dev;
34 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
35 struct nouveau_i2c_chan *auxch;
36 int ret;
37
38 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
39 if (!auxch)
40 return -ENODEV;
41
42 ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
43 if (ret)
44 return ret;
45
46 return 0;
47}
48
49static int
50auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
51{
52 struct drm_device *dev = encoder->dev;
53 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
54 struct nouveau_i2c_chan *auxch;
55 int ret;
56
57 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
58 if (!auxch)
59 return -ENODEV;
60
61 ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
62 return ret;
63}
64
65static int
66nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
67{
68 struct drm_device *dev = encoder->dev;
69 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
70 uint32_t tmp;
71 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
72
73 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
74 tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
75 NV50_SOR_DP_CTRL_LANE_MASK);
76 tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
77 if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
78 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
79 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
80
81 return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
82}
83
84static int
85nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
86{
87 struct drm_device *dev = encoder->dev;
88 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
89 uint32_t tmp;
90 int reg = 0x614300 + (nv_encoder->or * 0x800);
91
92 tmp = nv_rd32(dev, reg);
93 tmp &= 0xfff3ffff;
94 if (cmd == DP_LINK_BW_2_7)
95 tmp |= 0x00040000;
96 nv_wr32(dev, reg, tmp);
97
98 return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
99}
100
101static int
102nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
103{
104 struct drm_device *dev = encoder->dev;
105 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
106 uint32_t tmp;
107 uint8_t cmd;
108 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
109 int ret;
110
111 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
112 tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
113 tmp |= (pattern << 24);
114 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
115
116 ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
117 if (ret)
118 return ret;
119 cmd &= ~DP_TRAINING_PATTERN_MASK;
120 cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
121 return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
122}
123
124static int
125nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
126{
127 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
128 struct drm_device *dev = encoder->dev;
129 struct bit_displayport_encoder_table_entry *dpse;
130 struct bit_displayport_encoder_table *dpe;
131 int i, dpe_headerlen, max_vs = 0;
132
133 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
134 if (!dpe)
135 return false;
136 dpse = (void *)((char *)dpe + dpe_headerlen);
137
138 for (i = 0; i < dpe_headerlen; i++, dpse++) {
139 if (dpse->vs_level > max_vs)
140 max_vs = dpse->vs_level;
141 }
142
143 return max_vs;
144}
145
146static int
147nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
148{
149 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
150 struct drm_device *dev = encoder->dev;
151 struct bit_displayport_encoder_table_entry *dpse;
152 struct bit_displayport_encoder_table *dpe;
153 int i, dpe_headerlen, max_pre = 0;
154
155 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
156 if (!dpe)
157 return false;
158 dpse = (void *)((char *)dpe + dpe_headerlen);
159
160 for (i = 0; i < dpe_headerlen; i++, dpse++) {
161 if (dpse->vs_level != vs)
162 continue;
163
164 if (dpse->pre_level > max_pre)
165 max_pre = dpse->pre_level;
166 }
167
168 return max_pre;
169}
170
171static bool
172nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
173{
174 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
175 struct drm_device *dev = encoder->dev;
176 struct bit_displayport_encoder_table_entry *dpse;
177 struct bit_displayport_encoder_table *dpe;
178 int ret, i, dpe_headerlen, vs = 0, pre = 0;
179 uint8_t request[2];
180
181 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
182 if (!dpe)
183 return false;
184 dpse = (void *)((char *)dpe + dpe_headerlen);
185
186 ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
187 if (ret)
188 return false;
189
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100190 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000191
192 /* Keep all lanes at the same level.. */
193 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
194 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
195 int lane_vs = lane_req & 3;
196 int lane_pre = (lane_req >> 2) & 3;
197
198 if (lane_vs > vs)
199 vs = lane_vs;
200 if (lane_pre > pre)
201 pre = lane_pre;
202 }
203
204 if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
205 vs = nouveau_dp_max_voltage_swing(encoder);
206 vs |= 4;
207 }
208
209 if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
210 pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
211 pre |= 4;
212 }
213
214 /* Update the configuration for all lanes.. */
215 for (i = 0; i < nv_encoder->dp.link_nr; i++)
216 config[i] = (pre << 3) | vs;
217
218 return true;
219}
220
221static bool
222nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
223{
224 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
225 struct drm_device *dev = encoder->dev;
226 struct bit_displayport_encoder_table_entry *dpse;
227 struct bit_displayport_encoder_table *dpe;
228 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
229 int dpe_headerlen, ret, i;
230
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100231 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
Ben Skeggs6ee73862009-12-11 19:24:15 +1000232 config[0], config[1], config[2], config[3]);
233
234 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
235 if (!dpe)
236 return false;
237 dpse = (void *)((char *)dpe + dpe_headerlen);
238
239 for (i = 0; i < dpe->record_nr; i++, dpse++) {
240 if (dpse->vs_level == (config[0] & 3) &&
241 dpse->pre_level == ((config[0] >> 3) & 3))
242 break;
243 }
244 BUG_ON(i == dpe->record_nr);
245
246 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
247 const int shift[4] = { 16, 8, 0, 24 };
248 uint32_t mask = 0xff << shift[i];
249 uint32_t reg0, reg1, reg2;
250
251 reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
252 reg0 |= (dpse->reg0 << shift[i]);
253 reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
254 reg1 |= (dpse->reg1 << shift[i]);
255 reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
256 reg2 |= (dpse->reg2 << 8);
257 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
258 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
259 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
260 }
261
262 ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
263 if (ret)
264 return false;
265
266 return true;
267}
268
269bool
270nouveau_dp_link_train(struct drm_encoder *encoder)
271{
272 struct drm_device *dev = encoder->dev;
273 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
Ben Skeggsea4718d2010-07-06 11:00:42 +1000274 struct bit_displayport_encoder_table *dpe;
275 int dpe_headerlen;
276 uint8_t config[4], status[3];
Ben Skeggs6ee73862009-12-11 19:24:15 +1000277 bool cr_done, cr_max_vs, eq_done;
278 int ret = 0, i, tries, voltage;
279
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100280 NV_DEBUG_KMS(dev, "link training!!\n");
Ben Skeggsea4718d2010-07-06 11:00:42 +1000281
282 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
283 if (!dpe) {
284 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
285 return false;
286 }
287
288 if (dpe->script0) {
289 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
290 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
291 nv_encoder->dcb);
292 }
293
Ben Skeggs6ee73862009-12-11 19:24:15 +1000294train:
295 cr_done = eq_done = false;
296
297 /* set link configuration */
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100298 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
Ben Skeggs6ee73862009-12-11 19:24:15 +1000299 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
300
301 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
302 if (ret)
303 return false;
304
305 config[0] = nv_encoder->dp.link_nr;
306 if (nv_encoder->dp.dpcd_version >= 0x11)
307 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
308
309 ret = nouveau_dp_lane_count_set(encoder, config[0]);
310 if (ret)
311 return false;
312
313 /* clock recovery */
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100314 NV_DEBUG_KMS(dev, "\tbegin cr\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000315 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
316 if (ret)
317 goto stop;
318
319 tries = 0;
320 voltage = -1;
321 memset(config, 0x00, sizeof(config));
322 for (;;) {
323 if (!nouveau_dp_link_train_commit(encoder, config))
324 break;
325
326 udelay(100);
327
328 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
329 if (ret)
330 break;
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100331 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
Ben Skeggs6ee73862009-12-11 19:24:15 +1000332 status[0], status[1]);
333
334 cr_done = true;
335 cr_max_vs = false;
336 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
337 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
338
339 if (!(lane & DP_LANE_CR_DONE)) {
340 cr_done = false;
341 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
342 cr_max_vs = true;
343 break;
344 }
345 }
346
347 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
348 voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
349 tries = 0;
350 }
351
352 if (cr_done || cr_max_vs || (++tries == 5))
353 break;
354
355 if (!nouveau_dp_link_train_adjust(encoder, config))
356 break;
357 }
358
359 if (!cr_done)
360 goto stop;
361
362 /* channel equalisation */
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100363 NV_DEBUG_KMS(dev, "\tbegin eq\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000364 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
365 if (ret)
366 goto stop;
367
368 for (tries = 0; tries <= 5; tries++) {
369 udelay(400);
370
371 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
372 if (ret)
373 break;
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100374 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
Ben Skeggs6ee73862009-12-11 19:24:15 +1000375 status[0], status[1]);
376
377 eq_done = true;
378 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
379 eq_done = false;
380
381 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
382 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
383
384 if (!(lane & DP_LANE_CR_DONE)) {
385 cr_done = false;
386 break;
387 }
388
389 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
390 !(lane & DP_LANE_SYMBOL_LOCKED)) {
391 eq_done = false;
392 break;
393 }
394 }
395
396 if (eq_done || !cr_done)
397 break;
398
399 if (!nouveau_dp_link_train_adjust(encoder, config) ||
400 !nouveau_dp_link_train_commit(encoder, config))
401 break;
402 }
403
404stop:
405 /* end link training */
406 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
407 if (ret)
408 return false;
409
410 /* retry at a lower setting, if possible */
411 if (!ret && !(eq_done && cr_done)) {
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100412 NV_DEBUG_KMS(dev, "\twe failed\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000413 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100414 NV_DEBUG_KMS(dev, "retry link training at low rate\n");
Ben Skeggs6ee73862009-12-11 19:24:15 +1000415 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
416 goto train;
417 }
418 }
419
Ben Skeggsea4718d2010-07-06 11:00:42 +1000420 if (dpe->script1) {
421 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
422 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
423 nv_encoder->dcb);
424 }
425
Ben Skeggs6ee73862009-12-11 19:24:15 +1000426 return eq_done;
427}
428
429bool
430nouveau_dp_detect(struct drm_encoder *encoder)
431{
432 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
433 struct drm_device *dev = encoder->dev;
434 uint8_t dpcd[4];
435 int ret;
436
437 ret = auxch_rd(encoder, 0x0000, dpcd, 4);
438 if (ret)
439 return false;
440
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100441 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
Ben Skeggs6ee73862009-12-11 19:24:15 +1000442 "display: link_bw %d, link_nr %d version 0x%02x\n",
443 nv_encoder->dcb->dpconf.link_bw,
444 nv_encoder->dcb->dpconf.link_nr,
445 dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
446
447 nv_encoder->dp.dpcd_version = dpcd[0];
448
449 nv_encoder->dp.link_bw = dpcd[1];
450 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
451 !nv_encoder->dcb->dpconf.link_bw)
452 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
453
454 nv_encoder->dp.link_nr = dpcd[2] & 0xf;
455 if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
456 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
457
458 return true;
459}
460
461int
462nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
463 uint8_t *data, int data_nr)
464{
465 struct drm_device *dev = auxch->dev;
466 uint32_t tmp, ctrl, stat = 0, data32[4] = {};
467 int ret = 0, i, index = auxch->rd;
468
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100469 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000470
471 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
472 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
473 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
474 if (!(tmp & 0x01000000)) {
475 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
476 ret = -EIO;
477 goto out;
478 }
479
480 for (i = 0; i < 3; i++) {
481 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
482 if (tmp & NV50_AUXCH_STAT_STATE_READY)
483 break;
484 udelay(100);
485 }
486
487 if (i == 3) {
488 ret = -EBUSY;
489 goto out;
490 }
491
492 if (!(cmd & 1)) {
493 memcpy(data32, data, data_nr);
494 for (i = 0; i < 4; i++) {
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100495 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000496 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
497 }
498 }
499
500 nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
501 ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index));
502 ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
503 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
504 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
505
Ben Skeggs8e024f12010-03-16 08:45:07 +1000506 for (i = 0; i < 16; i++) {
Ben Skeggs6ee73862009-12-11 19:24:15 +1000507 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
508 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
509 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
510 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
511 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
512 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
Ben Skeggs0107bae2010-01-22 09:10:05 +1000513 ret = -EBUSY;
514 goto out;
Ben Skeggs6ee73862009-12-11 19:24:15 +1000515 }
516
517 udelay(400);
518
519 stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
520 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
521 NV50_AUXCH_STAT_REPLY_AUX_DEFER)
522 break;
523 }
524
Ben Skeggs8e024f12010-03-16 08:45:07 +1000525 if (i == 16) {
526 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
527 ret = -EREMOTEIO;
528 goto out;
529 }
530
Ben Skeggs6ee73862009-12-11 19:24:15 +1000531 if (cmd & 1) {
Ben Skeggs1ee76982010-02-09 10:08:34 +1000532 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
533 ret = -EREMOTEIO;
534 goto out;
535 }
536
Ben Skeggs6ee73862009-12-11 19:24:15 +1000537 for (i = 0; i < 4; i++) {
538 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
Maarten Maathuisef2bb502009-12-13 16:53:12 +0100539 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
Ben Skeggs6ee73862009-12-11 19:24:15 +1000540 }
541 memcpy(data, data32, data_nr);
542 }
543
544out:
545 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
546 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
547 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
548 if (tmp & 0x01000000) {
549 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
550 ret = -EIO;
551 }
552
553 udelay(400);
554
555 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
556}
557
558int
559nouveau_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
560 uint8_t write_byte, uint8_t *read_byte)
561{
562 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
563 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adapter;
564 struct drm_device *dev = auxch->dev;
565 int ret = 0, cmd, addr = algo_data->address;
566 uint8_t *buf;
567
568 if (mode == MODE_I2C_READ) {
569 cmd = AUX_I2C_READ;
570 buf = read_byte;
571 } else {
572 cmd = (mode & MODE_I2C_READ) ? AUX_I2C_READ : AUX_I2C_WRITE;
573 buf = &write_byte;
574 }
575
576 if (!(mode & MODE_I2C_STOP))
577 cmd |= AUX_I2C_MOT;
578
579 if (mode & MODE_I2C_START)
580 return 1;
581
582 for (;;) {
583 ret = nouveau_dp_auxch(auxch, cmd, addr, buf, 1);
584 if (ret < 0)
585 return ret;
586
587 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
588 case NV50_AUXCH_STAT_REPLY_I2C_ACK:
589 return 1;
590 case NV50_AUXCH_STAT_REPLY_I2C_NACK:
591 return -EREMOTEIO;
592 case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
593 udelay(100);
594 break;
595 default:
596 NV_ERROR(dev, "invalid auxch status: 0x%08x\n", ret);
597 return -EREMOTEIO;
598 }
599 }
600}
601