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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/acorn/net/ether1.h
3 *
4 * Copyright (C) 1996 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Network driver for Acorn Ether1 cards.
11 */
12
13#ifndef _LINUX_ether1_H
14#define _LINUX_ether1_H
15
16#ifdef __ETHER1_C
17/* use 0 for production, 1 for verification, >2 for debug */
18#ifndef NET_DEBUG
19#define NET_DEBUG 0
20#endif
21
22#define priv(dev) ((struct ether1_priv *)netdev_priv(dev))
23
24/* Page register */
25#define REG_PAGE (priv(dev)->base + 0x0000)
26
27/* Control register */
28#define REG_CONTROL (priv(dev)->base + 0x0004)
29#define CTRL_RST 0x01
30#define CTRL_LOOPBACK 0x02
31#define CTRL_CA 0x04
32#define CTRL_ACK 0x08
33
34#define ETHER1_RAM (priv(dev)->base + 0x2000)
35
36/* HW address */
37#define IDPROM_ADDRESS (priv(dev)->base + 0x0024)
38
39struct ether1_priv {
40 void __iomem *base;
41 struct net_device_stats stats;
42 unsigned int tx_link;
43 unsigned int tx_head;
44 volatile unsigned int tx_tail;
45 volatile unsigned int rx_head;
46 volatile unsigned int rx_tail;
47 unsigned char bus_type;
48 unsigned char resetting;
49 unsigned char initialising : 1;
50 unsigned char restart : 1;
51};
52
53#define I82586_NULL (-1)
54
55typedef struct { /* tdr */
56 unsigned short tdr_status;
57 unsigned short tdr_command;
58 unsigned short tdr_link;
59 unsigned short tdr_result;
60#define TDR_TIME (0x7ff)
61#define TDR_SHORT (1 << 12)
62#define TDR_OPEN (1 << 13)
63#define TDR_XCVRPROB (1 << 14)
64#define TDR_LNKOK (1 << 15)
65} tdr_t;
66
67typedef struct { /* transmit */
68 unsigned short tx_status;
69 unsigned short tx_command;
70 unsigned short tx_link;
71 unsigned short tx_tbdoffset;
72} tx_t;
73
74typedef struct { /* tbd */
75 unsigned short tbd_opts;
76#define TBD_CNT (0x3fff)
77#define TBD_EOL (1 << 15)
78 unsigned short tbd_link;
79 unsigned short tbd_bufl;
80 unsigned short tbd_bufh;
81} tbd_t;
82
83typedef struct { /* rfd */
84 unsigned short rfd_status;
85#define RFD_NOEOF (1 << 6)
86#define RFD_FRAMESHORT (1 << 7)
87#define RFD_DMAOVRN (1 << 8)
88#define RFD_NORESOURCES (1 << 9)
89#define RFD_ALIGNERROR (1 << 10)
90#define RFD_CRCERROR (1 << 11)
91#define RFD_OK (1 << 13)
92#define RFD_FDCONSUMED (1 << 14)
93#define RFD_COMPLETE (1 << 15)
94 unsigned short rfd_command;
95#define RFD_CMDSUSPEND (1 << 14)
96#define RFD_CMDEL (1 << 15)
97 unsigned short rfd_link;
98 unsigned short rfd_rbdoffset;
99 unsigned char rfd_dest[6];
100 unsigned char rfd_src[6];
101 unsigned short rfd_len;
102} rfd_t;
103
104typedef struct { /* rbd */
105 unsigned short rbd_status;
106#define RBD_ACNT (0x3fff)
107#define RBD_ACNTVALID (1 << 14)
108#define RBD_EOF (1 << 15)
109 unsigned short rbd_link;
110 unsigned short rbd_bufl;
111 unsigned short rbd_bufh;
112 unsigned short rbd_len;
113} rbd_t;
114
115typedef struct { /* nop */
116 unsigned short nop_status;
117 unsigned short nop_command;
118 unsigned short nop_link;
119} nop_t;
120
121typedef struct { /* set multicast */
122 unsigned short mc_status;
123 unsigned short mc_command;
124 unsigned short mc_link;
125 unsigned short mc_cnt;
126 unsigned char mc_addrs[1][6];
127} mc_t;
128
129typedef struct { /* set address */
130 unsigned short sa_status;
131 unsigned short sa_command;
132 unsigned short sa_link;
133 unsigned char sa_addr[6];
134} sa_t;
135
136typedef struct { /* config command */
137 unsigned short cfg_status;
138 unsigned short cfg_command;
139 unsigned short cfg_link;
140 unsigned char cfg_bytecnt; /* size foll data: 4 - 12 */
141 unsigned char cfg_fifolim; /* FIFO threshold */
142 unsigned char cfg_byte8;
143#define CFG8_SRDY (1 << 6)
144#define CFG8_SAVEBADF (1 << 7)
145 unsigned char cfg_byte9;
146#define CFG9_ADDRLEN(x) (x)
147#define CFG9_ADDRLENBUF (1 << 3)
148#define CFG9_PREAMB2 (0 << 4)
149#define CFG9_PREAMB4 (1 << 4)
150#define CFG9_PREAMB8 (2 << 4)
151#define CFG9_PREAMB16 (3 << 4)
152#define CFG9_ILOOPBACK (1 << 6)
153#define CFG9_ELOOPBACK (1 << 7)
154 unsigned char cfg_byte10;
155#define CFG10_LINPRI(x) (x)
156#define CFG10_ACR(x) (x << 4)
157#define CFG10_BOFMET (1 << 7)
158 unsigned char cfg_ifs;
159 unsigned char cfg_slotl;
160 unsigned char cfg_byte13;
161#define CFG13_SLOTH(x) (x)
162#define CFG13_RETRY(x) (x << 4)
163 unsigned char cfg_byte14;
164#define CFG14_PROMISC (1 << 0)
165#define CFG14_DISBRD (1 << 1)
166#define CFG14_MANCH (1 << 2)
167#define CFG14_TNCRS (1 << 3)
168#define CFG14_NOCRC (1 << 4)
169#define CFG14_CRC16 (1 << 5)
170#define CFG14_BTSTF (1 << 6)
171#define CFG14_FLGPAD (1 << 7)
172 unsigned char cfg_byte15;
173#define CFG15_CSTF(x) (x)
174#define CFG15_ICSS (1 << 3)
175#define CFG15_CDTF(x) (x << 4)
176#define CFG15_ICDS (1 << 7)
177 unsigned short cfg_minfrmlen;
178} cfg_t;
179
180typedef struct { /* scb */
181 unsigned short scb_status; /* status of 82586 */
182#define SCB_STRXMASK (7 << 4) /* Receive unit status */
183#define SCB_STRXIDLE (0 << 4) /* Idle */
184#define SCB_STRXSUSP (1 << 4) /* Suspended */
185#define SCB_STRXNRES (2 << 4) /* No resources */
186#define SCB_STRXRDY (4 << 4) /* Ready */
187#define SCB_STCUMASK (7 << 8) /* Command unit status */
188#define SCB_STCUIDLE (0 << 8) /* Idle */
189#define SCB_STCUSUSP (1 << 8) /* Suspended */
190#define SCB_STCUACTV (2 << 8) /* Active */
191#define SCB_STRNR (1 << 12) /* Receive unit not ready */
192#define SCB_STCNA (1 << 13) /* Command unit not ready */
193#define SCB_STFR (1 << 14) /* Frame received */
194#define SCB_STCX (1 << 15) /* Command completed */
195 unsigned short scb_command; /* Next command */
196#define SCB_CMDRXSTART (1 << 4) /* Start (at rfa_offset) */
197#define SCB_CMDRXRESUME (2 << 4) /* Resume reception */
198#define SCB_CMDRXSUSPEND (3 << 4) /* Suspend reception */
199#define SCB_CMDRXABORT (4 << 4) /* Abort reception */
200#define SCB_CMDCUCSTART (1 << 8) /* Start (at cbl_offset) */
201#define SCB_CMDCUCRESUME (2 << 8) /* Resume execution */
202#define SCB_CMDCUCSUSPEND (3 << 8) /* Suspend execution */
203#define SCB_CMDCUCABORT (4 << 8) /* Abort execution */
204#define SCB_CMDACKRNR (1 << 12) /* Ack RU not ready */
205#define SCB_CMDACKCNA (1 << 13) /* Ack CU not ready */
206#define SCB_CMDACKFR (1 << 14) /* Ack Frame received */
207#define SCB_CMDACKCX (1 << 15) /* Ack Command complete */
208 unsigned short scb_cbl_offset; /* Offset of first command unit */
209 unsigned short scb_rfa_offset; /* Offset of first receive frame area */
210 unsigned short scb_crc_errors; /* Properly aligned frame with CRC error*/
211 unsigned short scb_aln_errors; /* Misaligned frames */
212 unsigned short scb_rsc_errors; /* Frames lost due to no space */
213 unsigned short scb_ovn_errors; /* Frames lost due to slow bus */
214} scb_t;
215
216typedef struct { /* iscp */
217 unsigned short iscp_busy; /* set by CPU before CA */
218 unsigned short iscp_offset; /* offset of SCB */
219 unsigned short iscp_basel; /* base of SCB */
220 unsigned short iscp_baseh;
221} iscp_t;
222
223 /* this address must be 0xfff6 */
224typedef struct { /* scp */
225 unsigned short scp_sysbus; /* bus size */
226#define SCP_SY_16BBUS 0x00
227#define SCP_SY_8BBUS 0x01
228 unsigned short scp_junk[2]; /* junk */
229 unsigned short scp_iscpl; /* lower 16 bits of iscp */
230 unsigned short scp_iscph; /* upper 16 bits of iscp */
231} scp_t;
232
233/* commands */
234#define CMD_NOP 0
235#define CMD_SETADDRESS 1
236#define CMD_CONFIG 2
237#define CMD_SETMULTICAST 3
238#define CMD_TX 4
239#define CMD_TDR 5
240#define CMD_DUMP 6
241#define CMD_DIAGNOSE 7
242
243#define CMD_MASK 7
244
245#define CMD_INTR (1 << 13)
246#define CMD_SUSP (1 << 14)
247#define CMD_EOL (1 << 15)
248
249#define STAT_COLLISIONS (15)
250#define STAT_COLLEXCESSIVE (1 << 5)
251#define STAT_COLLAFTERTX (1 << 6)
252#define STAT_TXDEFERRED (1 << 7)
253#define STAT_TXSLOWDMA (1 << 8)
254#define STAT_TXLOSTCTS (1 << 9)
255#define STAT_NOCARRIER (1 << 10)
256#define STAT_FAIL (1 << 11)
257#define STAT_ABORTED (1 << 12)
258#define STAT_OK (1 << 13)
259#define STAT_BUSY (1 << 14)
260#define STAT_COMPLETE (1 << 15)
261#endif
262#endif
263
264/*
265 * Ether1 card definitions:
266 *
267 * FAST accesses:
268 * +0 Page register
269 * 16 pages
270 * +4 Control
271 * '1' = reset
272 * '2' = loopback
273 * '4' = CA
274 * '8' = int ack
275 *
276 * RAM at address + 0x2000
277 * Pod. Prod id = 3
278 * Words after ID block [base + 8 words]
279 * +0 pcb issue (0x0c and 0xf3 invalid)
280 * +1 - +6 eth hw address
281 */