blob: 48adb2a0903e52a9567682430e5035b50487f6ae [file] [log] [blame]
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001/*
2 * Cryptographic API.
3 *
4 * Support for OMAP SHA1/MD5 HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
Mark A. Greer0d373d62012-12-21 10:04:08 -07008 * Copyright (c) 2011 Texas Instruments Incorporated
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08009 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 * Some ideas are from old omap-sha1-md5.c driver.
15 */
16
17#define pr_fmt(fmt) "%s: " fmt, __func__
18
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080019#include <linux/err.h>
20#include <linux/device.h>
21#include <linux/module.h>
22#include <linux/init.h>
23#include <linux/errno.h>
24#include <linux/interrupt.h>
25#include <linux/kernel.h>
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080026#include <linux/irq.h>
27#include <linux/io.h>
28#include <linux/platform_device.h>
29#include <linux/scatterlist.h>
30#include <linux/dma-mapping.h>
Mark A. Greerdfd061d2012-12-21 10:04:04 -070031#include <linux/dmaengine.h>
32#include <linux/omap-dma.h>
Mark A. Greerb359f032012-12-21 10:04:02 -070033#include <linux/pm_runtime.h>
Mark A. Greer03feec92012-12-21 10:04:06 -070034#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/of_address.h>
37#include <linux/of_irq.h>
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080038#include <linux/delay.h>
39#include <linux/crypto.h>
40#include <linux/cryptohash.h>
41#include <crypto/scatterwalk.h>
42#include <crypto/algapi.h>
43#include <crypto/sha.h>
44#include <crypto/hash.h>
45#include <crypto/internal/hash.h>
46
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080047#define MD5_DIGEST_SIZE 16
48
Mark A. Greer0d373d62012-12-21 10:04:08 -070049#define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
50#define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
51#define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
52
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +053053#define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080054
55#define SHA_REG_CTRL 0x18
56#define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
57#define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
58#define SHA_REG_CTRL_ALGO_CONST (1 << 3)
59#define SHA_REG_CTRL_ALGO (1 << 2)
60#define SHA_REG_CTRL_INPUT_READY (1 << 1)
61#define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
62
Mark A. Greer0d373d62012-12-21 10:04:08 -070063#define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080064
Mark A. Greer0d373d62012-12-21 10:04:08 -070065#define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080066#define SHA_REG_MASK_DMA_EN (1 << 3)
67#define SHA_REG_MASK_IT_EN (1 << 2)
68#define SHA_REG_MASK_SOFTRESET (1 << 1)
69#define SHA_REG_AUTOIDLE (1 << 0)
70
Mark A. Greer0d373d62012-12-21 10:04:08 -070071#define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +080072#define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
73
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +053074#define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
Mark A. Greer0d373d62012-12-21 10:04:08 -070075#define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
76#define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
77#define SHA_REG_MODE_CLOSE_HASH (1 << 4)
78#define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
Mark A. Greer0d373d62012-12-21 10:04:08 -070079
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +053080#define SHA_REG_MODE_ALGO_MASK (7 << 0)
81#define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
82#define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
83#define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
84#define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
85#define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
86#define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
87
88#define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
Mark A. Greer0d373d62012-12-21 10:04:08 -070089
90#define SHA_REG_IRQSTATUS 0x118
91#define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
92#define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
93#define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
94#define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
95
96#define SHA_REG_IRQENA 0x11C
97#define SHA_REG_IRQENA_CTX_RDY (1 << 3)
98#define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
99#define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
100#define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
101
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800102#define DEFAULT_TIMEOUT_INTERVAL HZ
103
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300104/* mostly device flags */
105#define FLAGS_BUSY 0
106#define FLAGS_FINAL 1
107#define FLAGS_DMA_ACTIVE 2
108#define FLAGS_OUTPUT_READY 3
109#define FLAGS_INIT 4
110#define FLAGS_CPU 5
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +0300111#define FLAGS_DMA_READY 6
Mark A. Greer0d373d62012-12-21 10:04:08 -0700112#define FLAGS_AUTO_XOR 7
113#define FLAGS_BE32_SHA1 8
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300114/* context flags */
115#define FLAGS_FINUP 16
116#define FLAGS_SG 17
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800117
Mark A. Greer0d373d62012-12-21 10:04:08 -0700118#define FLAGS_MODE_SHIFT 18
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530119#define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
120#define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
121#define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
122#define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
123#define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
124#define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
125#define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
126
127#define FLAGS_HMAC 21
128#define FLAGS_ERROR 22
Mark A. Greer0d373d62012-12-21 10:04:08 -0700129
130#define OP_UPDATE 1
131#define OP_FINAL 2
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800132
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200133#define OMAP_ALIGN_MASK (sizeof(u32)-1)
134#define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
135
Mark A. Greer0d373d62012-12-21 10:04:08 -0700136#define BUFLEN PAGE_SIZE
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200137
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800138struct omap_sham_dev;
139
140struct omap_sham_reqctx {
141 struct omap_sham_dev *dd;
142 unsigned long flags;
143 unsigned long op;
144
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530145 u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800146 size_t digcnt;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800147 size_t bufcnt;
148 size_t buflen;
149 dma_addr_t dma_addr;
150
151 /* walk state */
152 struct scatterlist *sg;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700153 struct scatterlist sgl;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800154 unsigned int offset; /* offset in current sg */
155 unsigned int total; /* total request */
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200156
157 u8 buffer[0] OMAP_ALIGNED;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800158};
159
160struct omap_sham_hmac_ctx {
161 struct crypto_shash *shash;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530162 u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
163 u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800164};
165
166struct omap_sham_ctx {
167 struct omap_sham_dev *dd;
168
169 unsigned long flags;
170
171 /* fallback stuff */
172 struct crypto_shash *fallback;
173
174 struct omap_sham_hmac_ctx base[0];
175};
176
177#define OMAP_SHAM_QUEUE_LENGTH 1
178
Mark A. Greerd20fb182012-12-21 10:04:09 -0700179struct omap_sham_algs_info {
180 struct ahash_alg *algs_list;
181 unsigned int size;
182 unsigned int registered;
183};
184
Mark A. Greer0d373d62012-12-21 10:04:08 -0700185struct omap_sham_pdata {
Mark A. Greerd20fb182012-12-21 10:04:09 -0700186 struct omap_sham_algs_info *algs_info;
187 unsigned int algs_info_size;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700188 unsigned long flags;
189 int digest_size;
190
191 void (*copy_hash)(struct ahash_request *req, int out);
192 void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
193 int final, int dma);
194 void (*trigger)(struct omap_sham_dev *dd, size_t length);
195 int (*poll_irq)(struct omap_sham_dev *dd);
196 irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
197
198 u32 odigest_ofs;
199 u32 idigest_ofs;
200 u32 din_ofs;
201 u32 digcnt_ofs;
202 u32 rev_ofs;
203 u32 mask_ofs;
204 u32 sysstatus_ofs;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530205 u32 mode_ofs;
206 u32 length_ofs;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700207
208 u32 major_mask;
209 u32 major_shift;
210 u32 minor_mask;
211 u32 minor_shift;
212};
213
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800214struct omap_sham_dev {
215 struct list_head list;
216 unsigned long phys_base;
217 struct device *dev;
218 void __iomem *io_base;
219 int irq;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800220 spinlock_t lock;
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +0200221 int err;
Mark A. Greer03feec92012-12-21 10:04:06 -0700222 unsigned int dma;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700223 struct dma_chan *dma_lch;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800224 struct tasklet_struct done_task;
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530225 u8 polling_mode;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800226
227 unsigned long flags;
228 struct crypto_queue queue;
229 struct ahash_request *req;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700230
231 const struct omap_sham_pdata *pdata;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800232};
233
234struct omap_sham_drv {
235 struct list_head dev_list;
236 spinlock_t lock;
237 unsigned long flags;
238};
239
240static struct omap_sham_drv sham = {
241 .dev_list = LIST_HEAD_INIT(sham.dev_list),
242 .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
243};
244
245static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
246{
247 return __raw_readl(dd->io_base + offset);
248}
249
250static inline void omap_sham_write(struct omap_sham_dev *dd,
251 u32 offset, u32 value)
252{
253 __raw_writel(value, dd->io_base + offset);
254}
255
256static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
257 u32 value, u32 mask)
258{
259 u32 val;
260
261 val = omap_sham_read(dd, address);
262 val &= ~mask;
263 val |= value;
264 omap_sham_write(dd, address, val);
265}
266
267static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
268{
269 unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
270
271 while (!(omap_sham_read(dd, offset) & bit)) {
272 if (time_is_before_jiffies(timeout))
273 return -ETIMEDOUT;
274 }
275
276 return 0;
277}
278
Mark A. Greer0d373d62012-12-21 10:04:08 -0700279static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800280{
281 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700282 struct omap_sham_dev *dd = ctx->dd;
Dmitry Kasatkin0c3cf4c2010-11-19 16:04:22 +0200283 u32 *hash = (u32 *)ctx->digest;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800284 int i;
285
Mark A. Greer0d373d62012-12-21 10:04:08 -0700286 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200287 if (out)
Mark A. Greer0d373d62012-12-21 10:04:08 -0700288 hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200289 else
Mark A. Greer0d373d62012-12-21 10:04:08 -0700290 omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200291 }
292}
293
Mark A. Greer0d373d62012-12-21 10:04:08 -0700294static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
295{
296 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
297 struct omap_sham_dev *dd = ctx->dd;
298 int i;
299
300 if (ctx->flags & BIT(FLAGS_HMAC)) {
301 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
302 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
303 struct omap_sham_hmac_ctx *bctx = tctx->base;
304 u32 *opad = (u32 *)bctx->opad;
305
306 for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
307 if (out)
308 opad[i] = omap_sham_read(dd,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530309 SHA_REG_ODIGEST(dd, i));
Mark A. Greer0d373d62012-12-21 10:04:08 -0700310 else
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530311 omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
Mark A. Greer0d373d62012-12-21 10:04:08 -0700312 opad[i]);
313 }
314 }
315
316 omap_sham_copy_hash_omap2(req, out);
317}
318
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200319static void omap_sham_copy_ready_hash(struct ahash_request *req)
320{
321 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
322 u32 *in = (u32 *)ctx->digest;
323 u32 *hash = (u32 *)req->result;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700324 int i, d, big_endian = 0;
Dmitry Kasatkin3c8d7582010-11-19 16:04:27 +0200325
326 if (!hash)
327 return;
328
Mark A. Greer0d373d62012-12-21 10:04:08 -0700329 switch (ctx->flags & FLAGS_MODE_MASK) {
330 case FLAGS_MODE_MD5:
331 d = MD5_DIGEST_SIZE / sizeof(u32);
332 break;
333 case FLAGS_MODE_SHA1:
334 /* OMAP2 SHA1 is big endian */
335 if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
336 big_endian = 1;
337 d = SHA1_DIGEST_SIZE / sizeof(u32);
338 break;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700339 case FLAGS_MODE_SHA224:
340 d = SHA224_DIGEST_SIZE / sizeof(u32);
341 break;
342 case FLAGS_MODE_SHA256:
343 d = SHA256_DIGEST_SIZE / sizeof(u32);
344 break;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530345 case FLAGS_MODE_SHA384:
346 d = SHA384_DIGEST_SIZE / sizeof(u32);
347 break;
348 case FLAGS_MODE_SHA512:
349 d = SHA512_DIGEST_SIZE / sizeof(u32);
350 break;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700351 default:
352 d = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800353 }
Mark A. Greer0d373d62012-12-21 10:04:08 -0700354
355 if (big_endian)
356 for (i = 0; i < d; i++)
357 hash[i] = be32_to_cpu(in[i]);
358 else
359 for (i = 0; i < d; i++)
360 hash[i] = le32_to_cpu(in[i]);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800361}
362
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200363static int omap_sham_hw_init(struct omap_sham_dev *dd)
364{
Pali Rohár604c3102015-03-08 11:01:01 +0100365 int err;
366
367 err = pm_runtime_get_sync(dd->dev);
368 if (err < 0) {
369 dev_err(dd->dev, "failed to get sync: %d\n", err);
370 return err;
371 }
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200372
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +0300373 if (!test_bit(FLAGS_INIT, &dd->flags)) {
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +0300374 set_bit(FLAGS_INIT, &dd->flags);
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200375 dd->err = 0;
376 }
377
378 return 0;
379}
380
Mark A. Greer0d373d62012-12-21 10:04:08 -0700381static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800382 int final, int dma)
383{
384 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
385 u32 val = length << 5, mask;
386
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200387 if (likely(ctx->digcnt))
Mark A. Greer0d373d62012-12-21 10:04:08 -0700388 omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800389
Mark A. Greer0d373d62012-12-21 10:04:08 -0700390 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800391 SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
392 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
393 /*
394 * Setting ALGO_CONST only for the first iteration
395 * and CLOSE_HASH only for the last one.
396 */
Mark A. Greer0d373d62012-12-21 10:04:08 -0700397 if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800398 val |= SHA_REG_CTRL_ALGO;
399 if (!ctx->digcnt)
400 val |= SHA_REG_CTRL_ALGO_CONST;
401 if (final)
402 val |= SHA_REG_CTRL_CLOSE_HASH;
403
404 mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
405 SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
406
407 omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800408}
409
Mark A. Greer0d373d62012-12-21 10:04:08 -0700410static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
411{
412}
413
414static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
415{
416 return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
417}
418
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530419static int get_block_size(struct omap_sham_reqctx *ctx)
420{
421 int d;
422
423 switch (ctx->flags & FLAGS_MODE_MASK) {
424 case FLAGS_MODE_MD5:
425 case FLAGS_MODE_SHA1:
426 d = SHA1_BLOCK_SIZE;
427 break;
428 case FLAGS_MODE_SHA224:
429 case FLAGS_MODE_SHA256:
430 d = SHA256_BLOCK_SIZE;
431 break;
432 case FLAGS_MODE_SHA384:
433 case FLAGS_MODE_SHA512:
434 d = SHA512_BLOCK_SIZE;
435 break;
436 default:
437 d = 0;
438 }
439
440 return d;
441}
442
Mark A. Greer0d373d62012-12-21 10:04:08 -0700443static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
444 u32 *value, int count)
445{
446 for (; count--; value++, offset += 4)
447 omap_sham_write(dd, offset, *value);
448}
449
450static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
451 int final, int dma)
452{
453 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
454 u32 val, mask;
455
456 /*
457 * Setting ALGO_CONST only for the first iteration and
458 * CLOSE_HASH only for the last one. Note that flags mode bits
459 * correspond to algorithm encoding in mode register.
460 */
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530461 val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700462 if (!ctx->digcnt) {
463 struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
464 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
465 struct omap_sham_hmac_ctx *bctx = tctx->base;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530466 int bs, nr_dr;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700467
468 val |= SHA_REG_MODE_ALGO_CONSTANT;
469
470 if (ctx->flags & BIT(FLAGS_HMAC)) {
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530471 bs = get_block_size(ctx);
472 nr_dr = bs / (2 * sizeof(u32));
Mark A. Greer0d373d62012-12-21 10:04:08 -0700473 val |= SHA_REG_MODE_HMAC_KEY_PROC;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530474 omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
475 (u32 *)bctx->ipad, nr_dr);
476 omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
477 (u32 *)bctx->ipad + nr_dr, nr_dr);
478 ctx->digcnt += bs;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700479 }
480 }
481
482 if (final) {
483 val |= SHA_REG_MODE_CLOSE_HASH;
484
485 if (ctx->flags & BIT(FLAGS_HMAC))
486 val |= SHA_REG_MODE_HMAC_OUTER_HASH;
487 }
488
489 mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
490 SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
491 SHA_REG_MODE_HMAC_KEY_PROC;
492
493 dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530494 omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700495 omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
496 omap_sham_write_mask(dd, SHA_REG_MASK(dd),
497 SHA_REG_MASK_IT_EN |
498 (dma ? SHA_REG_MASK_DMA_EN : 0),
499 SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
500}
501
502static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
503{
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530504 omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700505}
506
507static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
508{
509 return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
510 SHA_REG_IRQSTATUS_INPUT_RDY);
511}
512
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800513static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, const u8 *buf,
514 size_t length, int final)
515{
516 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530517 int count, len32, bs32, offset = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800518 const u32 *buffer = (const u32 *)buf;
519
520 dev_dbg(dd->dev, "xmit_cpu: digcnt: %d, length: %d, final: %d\n",
521 ctx->digcnt, length, final);
522
Mark A. Greer0d373d62012-12-21 10:04:08 -0700523 dd->pdata->write_ctrl(dd, length, final, 0);
524 dd->pdata->trigger(dd, length);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800525
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +0200526 /* should be non-zero before next lines to disable clocks later */
527 ctx->digcnt += length;
528
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800529 if (final)
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +0300530 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800531
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +0300532 set_bit(FLAGS_CPU, &dd->flags);
533
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800534 len32 = DIV_ROUND_UP(length, sizeof(u32));
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530535 bs32 = get_block_size(ctx) / sizeof(u32);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800536
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530537 while (len32) {
538 if (dd->pdata->poll_irq(dd))
539 return -ETIMEDOUT;
540
541 for (count = 0; count < min(len32, bs32); count++, offset++)
542 omap_sham_write(dd, SHA_REG_DIN(dd, count),
543 buffer[offset]);
544 len32 -= min(len32, bs32);
545 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800546
547 return -EINPROGRESS;
548}
549
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700550static void omap_sham_dma_callback(void *param)
551{
552 struct omap_sham_dev *dd = param;
553
554 set_bit(FLAGS_DMA_READY, &dd->flags);
555 tasklet_schedule(&dd->done_task);
556}
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700557
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800558static int omap_sham_xmit_dma(struct omap_sham_dev *dd, dma_addr_t dma_addr,
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700559 size_t length, int final, int is_sg)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800560{
561 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700562 struct dma_async_tx_descriptor *tx;
563 struct dma_slave_config cfg;
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530564 int len32, ret, dma_min = get_block_size(ctx);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800565
566 dev_dbg(dd->dev, "xmit_dma: digcnt: %d, length: %d, final: %d\n",
567 ctx->digcnt, length, final);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800568
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700569 memset(&cfg, 0, sizeof(cfg));
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800570
Mark A. Greer0d373d62012-12-21 10:04:08 -0700571 cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700572 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530573 cfg.dst_maxburst = dma_min / DMA_SLAVE_BUSWIDTH_4_BYTES;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800574
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700575 ret = dmaengine_slave_config(dd->dma_lch, &cfg);
576 if (ret) {
577 pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
578 return ret;
579 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800580
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530581 len32 = DIV_ROUND_UP(length, dma_min) * dma_min;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700582
583 if (is_sg) {
584 /*
585 * The SG entry passed in may not have the 'length' member
586 * set correctly so use a local SG entry (sgl) with the
587 * proper value for 'length' instead. If this is not done,
588 * the dmaengine may try to DMA the incorrect amount of data.
589 */
590 sg_init_table(&ctx->sgl, 1);
Christoph Hellwig89e2a842015-08-07 18:15:15 +0200591 sg_assign_page(&ctx->sgl, sg_page(ctx->sg));
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700592 ctx->sgl.offset = ctx->sg->offset;
593 sg_dma_len(&ctx->sgl) = len32;
594 sg_dma_address(&ctx->sgl) = sg_dma_address(ctx->sg);
595
596 tx = dmaengine_prep_slave_sg(dd->dma_lch, &ctx->sgl, 1,
597 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
598 } else {
599 tx = dmaengine_prep_slave_single(dd->dma_lch, dma_addr, len32,
600 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
601 }
602
603 if (!tx) {
604 dev_err(dd->dev, "prep_slave_sg/single() failed\n");
605 return -EINVAL;
606 }
607
608 tx->callback = omap_sham_dma_callback;
609 tx->callback_param = dd;
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700610
Mark A. Greer0d373d62012-12-21 10:04:08 -0700611 dd->pdata->write_ctrl(dd, length, final, 1);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800612
613 ctx->digcnt += length;
614
615 if (final)
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +0300616 set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800617
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +0300618 set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800619
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700620 dmaengine_submit(tx);
621 dma_async_issue_pending(dd->dma_lch);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800622
Mark A. Greer0d373d62012-12-21 10:04:08 -0700623 dd->pdata->trigger(dd, length);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800624
625 return -EINPROGRESS;
626}
627
628static size_t omap_sham_append_buffer(struct omap_sham_reqctx *ctx,
629 const u8 *data, size_t length)
630{
631 size_t count = min(length, ctx->buflen - ctx->bufcnt);
632
633 count = min(count, ctx->total);
634 if (count <= 0)
635 return 0;
636 memcpy(ctx->buffer + ctx->bufcnt, data, count);
637 ctx->bufcnt += count;
638
639 return count;
640}
641
642static size_t omap_sham_append_sg(struct omap_sham_reqctx *ctx)
643{
644 size_t count;
Joel Fernandes26a05482014-03-07 10:28:46 -0600645 const u8 *vaddr;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800646
647 while (ctx->sg) {
Joel Fernandes26a05482014-03-07 10:28:46 -0600648 vaddr = kmap_atomic(sg_page(ctx->sg));
Vutla, Lokesh13cf3942015-04-02 15:32:45 +0530649 vaddr += ctx->sg->offset;
Joel Fernandes26a05482014-03-07 10:28:46 -0600650
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800651 count = omap_sham_append_buffer(ctx,
Joel Fernandes26a05482014-03-07 10:28:46 -0600652 vaddr + ctx->offset,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800653 ctx->sg->length - ctx->offset);
Joel Fernandes26a05482014-03-07 10:28:46 -0600654
655 kunmap_atomic((void *)vaddr);
656
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800657 if (!count)
658 break;
659 ctx->offset += count;
660 ctx->total -= count;
661 if (ctx->offset == ctx->sg->length) {
662 ctx->sg = sg_next(ctx->sg);
663 if (ctx->sg)
664 ctx->offset = 0;
665 else
666 ctx->total = 0;
667 }
668 }
669
670 return 0;
671}
672
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200673static int omap_sham_xmit_dma_map(struct omap_sham_dev *dd,
674 struct omap_sham_reqctx *ctx,
675 size_t length, int final)
676{
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700677 int ret;
678
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200679 ctx->dma_addr = dma_map_single(dd->dev, ctx->buffer, ctx->buflen,
680 DMA_TO_DEVICE);
681 if (dma_mapping_error(dd->dev, ctx->dma_addr)) {
682 dev_err(dd->dev, "dma %u bytes error\n", ctx->buflen);
683 return -EINVAL;
684 }
685
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300686 ctx->flags &= ~BIT(FLAGS_SG);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200687
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700688 ret = omap_sham_xmit_dma(dd, ctx->dma_addr, length, final, 0);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700689 if (ret != -EINPROGRESS)
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700690 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
691 DMA_TO_DEVICE);
692
693 return ret;
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200694}
695
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800696static int omap_sham_update_dma_slow(struct omap_sham_dev *dd)
697{
698 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
699 unsigned int final;
700 size_t count;
701
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800702 omap_sham_append_sg(ctx);
703
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300704 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800705
706 dev_dbg(dd->dev, "slow: bufcnt: %u, digcnt: %d, final: %d\n",
707 ctx->bufcnt, ctx->digcnt, final);
708
709 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
710 count = ctx->bufcnt;
711 ctx->bufcnt = 0;
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200712 return omap_sham_xmit_dma_map(dd, ctx, count, final);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800713 }
714
715 return 0;
716}
717
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200718/* Start address alignment */
719#define SG_AA(sg) (IS_ALIGNED(sg->offset, sizeof(u32)))
720/* SHA1 block size alignment */
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530721#define SG_SA(sg, bs) (IS_ALIGNED(sg->length, bs))
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200722
723static int omap_sham_update_dma_start(struct omap_sham_dev *dd)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800724{
725 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200726 unsigned int length, final, tail;
727 struct scatterlist *sg;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530728 int ret, bs;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800729
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200730 if (!ctx->total)
731 return 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800732
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200733 if (ctx->bufcnt || ctx->offset)
734 return omap_sham_update_dma_slow(dd);
735
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700736 /*
737 * Don't use the sg interface when the transfer size is less
738 * than the number of elements in a DMA frame. Otherwise,
739 * the dmaengine infrastructure will calculate that it needs
740 * to transfer 0 frames which ultimately fails.
741 */
Lokesh Vutlaf5e46262013-08-20 20:32:35 +0530742 if (ctx->total < get_block_size(ctx))
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700743 return omap_sham_update_dma_slow(dd);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700744
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200745 dev_dbg(dd->dev, "fast: digcnt: %d, bufcnt: %u, total: %u\n",
746 ctx->digcnt, ctx->bufcnt, ctx->total);
747
748 sg = ctx->sg;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530749 bs = get_block_size(ctx);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200750
751 if (!SG_AA(sg))
752 return omap_sham_update_dma_slow(dd);
753
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530754 if (!sg_is_last(sg) && !SG_SA(sg, bs))
755 /* size is not BLOCK_SIZE aligned */
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200756 return omap_sham_update_dma_slow(dd);
757
758 length = min(ctx->total, sg->length);
759
760 if (sg_is_last(sg)) {
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300761 if (!(ctx->flags & BIT(FLAGS_FINUP))) {
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530762 /* not last sg must be BLOCK_SIZE aligned */
763 tail = length & (bs - 1);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200764 /* without finup() we need one block to close hash */
765 if (!tail)
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530766 tail = bs;
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200767 length -= tail;
768 }
769 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800770
771 if (!dma_map_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE)) {
772 dev_err(dd->dev, "dma_map_sg error\n");
773 return -EINVAL;
774 }
775
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300776 ctx->flags |= BIT(FLAGS_SG);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200777
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800778 ctx->total -= length;
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200779 ctx->offset = length; /* offset where to start slow */
780
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300781 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800782
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700783 ret = omap_sham_xmit_dma(dd, sg_dma_address(ctx->sg), length, final, 1);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700784 if (ret != -EINPROGRESS)
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700785 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
786
787 return ret;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800788}
789
790static int omap_sham_update_cpu(struct omap_sham_dev *dd)
791{
792 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530793 int bufcnt, final;
794
795 if (!ctx->total)
796 return 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800797
798 omap_sham_append_sg(ctx);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530799
800 final = (ctx->flags & BIT(FLAGS_FINUP)) && !ctx->total;
801
802 dev_dbg(dd->dev, "cpu: bufcnt: %u, digcnt: %d, final: %d\n",
803 ctx->bufcnt, ctx->digcnt, final);
804
Lokesh Vutlaacef7b02013-12-18 19:03:33 +0530805 if (final || (ctx->bufcnt == ctx->buflen && ctx->total)) {
806 bufcnt = ctx->bufcnt;
807 ctx->bufcnt = 0;
808 return omap_sham_xmit_cpu(dd, ctx->buffer, bufcnt, final);
809 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800810
Lokesh Vutlaacef7b02013-12-18 19:03:33 +0530811 return 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800812}
813
814static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
815{
816 struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
817
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700818 dmaengine_terminate_all(dd->dma_lch);
Mark A. Greerdfd061d2012-12-21 10:04:04 -0700819
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300820 if (ctx->flags & BIT(FLAGS_SG)) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800821 dma_unmap_sg(dd->dev, ctx->sg, 1, DMA_TO_DEVICE);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200822 if (ctx->sg->length == ctx->offset) {
823 ctx->sg = sg_next(ctx->sg);
824 if (ctx->sg)
825 ctx->offset = 0;
826 }
827 } else {
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200828 dma_unmap_single(dd->dev, ctx->dma_addr, ctx->buflen,
829 DMA_TO_DEVICE);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200830 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800831
832 return 0;
833}
834
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800835static int omap_sham_init(struct ahash_request *req)
836{
837 struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
838 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
839 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
840 struct omap_sham_dev *dd = NULL, *tmp;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530841 int bs = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800842
843 spin_lock_bh(&sham.lock);
844 if (!tctx->dd) {
845 list_for_each_entry(tmp, &sham.dev_list, list) {
846 dd = tmp;
847 break;
848 }
849 tctx->dd = dd;
850 } else {
851 dd = tctx->dd;
852 }
853 spin_unlock_bh(&sham.lock);
854
855 ctx->dd = dd;
856
857 ctx->flags = 0;
858
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800859 dev_dbg(dd->dev, "init: digest size: %d\n",
860 crypto_ahash_digestsize(tfm));
861
Mark A. Greer0d373d62012-12-21 10:04:08 -0700862 switch (crypto_ahash_digestsize(tfm)) {
863 case MD5_DIGEST_SIZE:
864 ctx->flags |= FLAGS_MODE_MD5;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530865 bs = SHA1_BLOCK_SIZE;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700866 break;
867 case SHA1_DIGEST_SIZE:
868 ctx->flags |= FLAGS_MODE_SHA1;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530869 bs = SHA1_BLOCK_SIZE;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700870 break;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700871 case SHA224_DIGEST_SIZE:
872 ctx->flags |= FLAGS_MODE_SHA224;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530873 bs = SHA224_BLOCK_SIZE;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700874 break;
875 case SHA256_DIGEST_SIZE:
876 ctx->flags |= FLAGS_MODE_SHA256;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530877 bs = SHA256_BLOCK_SIZE;
878 break;
879 case SHA384_DIGEST_SIZE:
880 ctx->flags |= FLAGS_MODE_SHA384;
881 bs = SHA384_BLOCK_SIZE;
882 break;
883 case SHA512_DIGEST_SIZE:
884 ctx->flags |= FLAGS_MODE_SHA512;
885 bs = SHA512_BLOCK_SIZE;
Mark A. Greerd20fb182012-12-21 10:04:09 -0700886 break;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700887 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800888
889 ctx->bufcnt = 0;
890 ctx->digcnt = 0;
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200891 ctx->buflen = BUFLEN;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800892
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300893 if (tctx->flags & BIT(FLAGS_HMAC)) {
Mark A. Greer0d373d62012-12-21 10:04:08 -0700894 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
895 struct omap_sham_hmac_ctx *bctx = tctx->base;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800896
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +0530897 memcpy(ctx->buffer, bctx->ipad, bs);
898 ctx->bufcnt = bs;
Mark A. Greer0d373d62012-12-21 10:04:08 -0700899 }
900
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300901 ctx->flags |= BIT(FLAGS_HMAC);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800902 }
903
904 return 0;
905
906}
907
908static int omap_sham_update_req(struct omap_sham_dev *dd)
909{
910 struct ahash_request *req = dd->req;
911 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
912 int err;
913
914 dev_dbg(dd->dev, "update_req: total: %u, digcnt: %d, finup: %d\n",
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300915 ctx->total, ctx->digcnt, (ctx->flags & BIT(FLAGS_FINUP)) != 0);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800916
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300917 if (ctx->flags & BIT(FLAGS_CPU))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800918 err = omap_sham_update_cpu(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800919 else
Dmitry Kasatkin887c8832010-11-19 16:04:29 +0200920 err = omap_sham_update_dma_start(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800921
922 /* wait for dma completion before can take more data */
923 dev_dbg(dd->dev, "update: err: %d, digcnt: %d\n", err, ctx->digcnt);
924
925 return err;
926}
927
928static int omap_sham_final_req(struct omap_sham_dev *dd)
929{
930 struct ahash_request *req = dd->req;
931 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
932 int err = 0, use_dma = 1;
933
Lokesh Vutlab8411cc2013-08-20 20:32:34 +0530934 if ((ctx->bufcnt <= get_block_size(ctx)) || dd->polling_mode)
935 /*
936 * faster to handle last block with cpu or
937 * use cpu when dma is not present.
938 */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800939 use_dma = 0;
940
941 if (use_dma)
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200942 err = omap_sham_xmit_dma_map(dd, ctx, ctx->bufcnt, 1);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800943 else
944 err = omap_sham_xmit_cpu(dd, ctx->buffer, ctx->bufcnt, 1);
945
946 ctx->bufcnt = 0;
947
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800948 dev_dbg(dd->dev, "final_req: err: %d\n", err);
949
950 return err;
951}
952
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300953static int omap_sham_finish_hmac(struct ahash_request *req)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800954{
955 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
956 struct omap_sham_hmac_ctx *bctx = tctx->base;
957 int bs = crypto_shash_blocksize(bctx->shash);
958 int ds = crypto_shash_digestsize(bctx->shash);
Behan Webster7bc53c32014-04-04 18:18:00 -0300959 SHASH_DESC_ON_STACK(shash, bctx->shash);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800960
Behan Webster7bc53c32014-04-04 18:18:00 -0300961 shash->tfm = bctx->shash;
962 shash->flags = 0; /* not CRYPTO_TFM_REQ_MAY_SLEEP */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800963
Behan Webster7bc53c32014-04-04 18:18:00 -0300964 return crypto_shash_init(shash) ?:
965 crypto_shash_update(shash, bctx->opad, bs) ?:
966 crypto_shash_finup(shash, req->result, ds, req->result);
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300967}
968
969static int omap_sham_finish(struct ahash_request *req)
970{
971 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
972 struct omap_sham_dev *dd = ctx->dd;
973 int err = 0;
974
975 if (ctx->digcnt) {
976 omap_sham_copy_ready_hash(req);
Mark A. Greer0d373d62012-12-21 10:04:08 -0700977 if ((ctx->flags & BIT(FLAGS_HMAC)) &&
978 !test_bit(FLAGS_AUTO_XOR, &dd->flags))
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300979 err = omap_sham_finish_hmac(req);
980 }
981
982 dev_dbg(dd->dev, "digcnt: %d, bufcnt: %d\n", ctx->digcnt, ctx->bufcnt);
983
984 return err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800985}
986
987static void omap_sham_finish_req(struct ahash_request *req, int err)
988{
989 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Dmitry Kasatkin798eed52010-11-19 16:04:26 +0200990 struct omap_sham_dev *dd = ctx->dd;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800991
992 if (!err) {
Mark A. Greer0d373d62012-12-21 10:04:08 -0700993 dd->pdata->copy_hash(req, 1);
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +0300994 if (test_bit(FLAGS_FINAL, &dd->flags))
Dmitry Kasatkinbf362752011-04-20 13:34:58 +0300995 err = omap_sham_finish(req);
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +0200996 } else {
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +0300997 ctx->flags |= BIT(FLAGS_ERROR);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +0800998 }
999
Dmitry Kasatkin0efd4d82011-06-02 21:10:12 +03001000 /* atomic operation is not needed here */
1001 dd->flags &= ~(BIT(FLAGS_BUSY) | BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
1002 BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
Mark A. Greerb359f032012-12-21 10:04:02 -07001003
Joel A Fernandese68af482013-02-26 10:04:31 -06001004 pm_runtime_put(dd->dev);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001005
1006 if (req->base.complete)
1007 req->base.complete(&req->base, err);
Dmitry Kasatkin6cb3ffe2011-06-02 21:10:09 +03001008
1009 /* handle new request */
1010 tasklet_schedule(&dd->done_task);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001011}
1012
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001013static int omap_sham_handle_queue(struct omap_sham_dev *dd,
1014 struct ahash_request *req)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001015{
Dmitry Kasatkin6c39d112010-12-29 21:52:04 +11001016 struct crypto_async_request *async_req, *backlog;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001017 struct omap_sham_reqctx *ctx;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001018 unsigned long flags;
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001019 int err = 0, ret = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001020
1021 spin_lock_irqsave(&dd->lock, flags);
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001022 if (req)
1023 ret = ahash_enqueue_request(&dd->queue, req);
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +03001024 if (test_bit(FLAGS_BUSY, &dd->flags)) {
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001025 spin_unlock_irqrestore(&dd->lock, flags);
1026 return ret;
1027 }
Dmitry Kasatkin6c39d112010-12-29 21:52:04 +11001028 backlog = crypto_get_backlog(&dd->queue);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001029 async_req = crypto_dequeue_request(&dd->queue);
Dmitry Kasatkin6c39d112010-12-29 21:52:04 +11001030 if (async_req)
Dmitry Kasatkina929cbe2011-06-02 21:10:06 +03001031 set_bit(FLAGS_BUSY, &dd->flags);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001032 spin_unlock_irqrestore(&dd->lock, flags);
1033
1034 if (!async_req)
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001035 return ret;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001036
1037 if (backlog)
1038 backlog->complete(backlog, -EINPROGRESS);
1039
1040 req = ahash_request_cast(async_req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001041 dd->req = req;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001042 ctx = ahash_request_ctx(req);
1043
1044 dev_dbg(dd->dev, "handling new req, op: %lu, nbytes: %d\n",
1045 ctx->op, req->nbytes);
1046
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001047 err = omap_sham_hw_init(dd);
1048 if (err)
1049 goto err1;
1050
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001051 if (ctx->digcnt)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001052 /* request has changed - restore hash */
Mark A. Greer0d373d62012-12-21 10:04:08 -07001053 dd->pdata->copy_hash(req, 0);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001054
1055 if (ctx->op == OP_UPDATE) {
1056 err = omap_sham_update_req(dd);
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001057 if (err != -EINPROGRESS && (ctx->flags & BIT(FLAGS_FINUP)))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001058 /* no final() after finup() */
1059 err = omap_sham_final_req(dd);
1060 } else if (ctx->op == OP_FINAL) {
1061 err = omap_sham_final_req(dd);
1062 }
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001063err1:
Dmitry Kasatkin6cb3ffe2011-06-02 21:10:09 +03001064 if (err != -EINPROGRESS)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001065 /* done_task will not finish it, so do it here */
1066 omap_sham_finish_req(req, err);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001067
1068 dev_dbg(dd->dev, "exit, err: %d\n", err);
1069
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001070 return ret;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001071}
1072
1073static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
1074{
1075 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1076 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1077 struct omap_sham_dev *dd = tctx->dd;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001078
1079 ctx->op = op;
1080
Dmitry Kasatkina5d87232010-11-19 16:04:25 +02001081 return omap_sham_handle_queue(dd, req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001082}
1083
1084static int omap_sham_update(struct ahash_request *req)
1085{
1086 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301087 struct omap_sham_dev *dd = ctx->dd;
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301088 int bs = get_block_size(ctx);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001089
1090 if (!req->nbytes)
1091 return 0;
1092
1093 ctx->total = req->nbytes;
1094 ctx->sg = req->src;
1095 ctx->offset = 0;
1096
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001097 if (ctx->flags & BIT(FLAGS_FINUP)) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001098 if ((ctx->digcnt + ctx->bufcnt + ctx->total) < 9) {
1099 /*
1100 * OMAP HW accel works only with buffers >= 9
1101 * will switch to bypass in final()
1102 * final has the same request and data
1103 */
1104 omap_sham_append_sg(ctx);
1105 return 0;
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301106 } else if ((ctx->bufcnt + ctx->total <= bs) ||
1107 dd->polling_mode) {
Dmitry Kasatkin887c8832010-11-19 16:04:29 +02001108 /*
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301109 * faster to use CPU for short transfers or
1110 * use cpu when dma is not present.
1111 */
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001112 ctx->flags |= BIT(FLAGS_CPU);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001113 }
Dmitry Kasatkin887c8832010-11-19 16:04:29 +02001114 } else if (ctx->bufcnt + ctx->total < ctx->buflen) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001115 omap_sham_append_sg(ctx);
1116 return 0;
1117 }
1118
Lokesh Vutlaacef7b02013-12-18 19:03:33 +05301119 if (dd->polling_mode)
1120 ctx->flags |= BIT(FLAGS_CPU);
1121
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001122 return omap_sham_enqueue(req, OP_UPDATE);
1123}
1124
Behan Webster7bc53c32014-04-04 18:18:00 -03001125static int omap_sham_shash_digest(struct crypto_shash *tfm, u32 flags,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001126 const u8 *data, unsigned int len, u8 *out)
1127{
Behan Webster7bc53c32014-04-04 18:18:00 -03001128 SHASH_DESC_ON_STACK(shash, tfm);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001129
Behan Webster7bc53c32014-04-04 18:18:00 -03001130 shash->tfm = tfm;
1131 shash->flags = flags & CRYPTO_TFM_REQ_MAY_SLEEP;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001132
Behan Webster7bc53c32014-04-04 18:18:00 -03001133 return crypto_shash_digest(shash, data, len, out);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001134}
1135
1136static int omap_sham_final_shash(struct ahash_request *req)
1137{
1138 struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1139 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1140
1141 return omap_sham_shash_digest(tctx->fallback, req->base.flags,
1142 ctx->buffer, ctx->bufcnt, req->result);
1143}
1144
1145static int omap_sham_final(struct ahash_request *req)
1146{
1147 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001148
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001149 ctx->flags |= BIT(FLAGS_FINUP);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001150
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001151 if (ctx->flags & BIT(FLAGS_ERROR))
Dmitry Kasatkinbf362752011-04-20 13:34:58 +03001152 return 0; /* uncompleted hash is not needed */
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001153
Dmitry Kasatkinbf362752011-04-20 13:34:58 +03001154 /* OMAP HW accel works only with buffers >= 9 */
1155 /* HMAC is always >= 9 because ipad == block size */
1156 if ((ctx->digcnt + ctx->bufcnt) < 9)
1157 return omap_sham_final_shash(req);
1158 else if (ctx->bufcnt)
1159 return omap_sham_enqueue(req, OP_FINAL);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001160
Dmitry Kasatkinbf362752011-04-20 13:34:58 +03001161 /* copy ready hash (+ finalize hmac) */
1162 return omap_sham_finish(req);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001163}
1164
1165static int omap_sham_finup(struct ahash_request *req)
1166{
1167 struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
1168 int err1, err2;
1169
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001170 ctx->flags |= BIT(FLAGS_FINUP);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001171
1172 err1 = omap_sham_update(req);
Markku Kylanpaa455e3382011-04-20 13:34:55 +03001173 if (err1 == -EINPROGRESS || err1 == -EBUSY)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001174 return err1;
1175 /*
1176 * final() has to be always called to cleanup resources
1177 * even if udpate() failed, except EINPROGRESS
1178 */
1179 err2 = omap_sham_final(req);
1180
1181 return err1 ?: err2;
1182}
1183
1184static int omap_sham_digest(struct ahash_request *req)
1185{
1186 return omap_sham_init(req) ?: omap_sham_finup(req);
1187}
1188
1189static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
1190 unsigned int keylen)
1191{
1192 struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
1193 struct omap_sham_hmac_ctx *bctx = tctx->base;
1194 int bs = crypto_shash_blocksize(bctx->shash);
1195 int ds = crypto_shash_digestsize(bctx->shash);
Mark A. Greer0d373d62012-12-21 10:04:08 -07001196 struct omap_sham_dev *dd = NULL, *tmp;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001197 int err, i;
Mark A. Greer0d373d62012-12-21 10:04:08 -07001198
1199 spin_lock_bh(&sham.lock);
1200 if (!tctx->dd) {
1201 list_for_each_entry(tmp, &sham.dev_list, list) {
1202 dd = tmp;
1203 break;
1204 }
1205 tctx->dd = dd;
1206 } else {
1207 dd = tctx->dd;
1208 }
1209 spin_unlock_bh(&sham.lock);
1210
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001211 err = crypto_shash_setkey(tctx->fallback, key, keylen);
1212 if (err)
1213 return err;
1214
1215 if (keylen > bs) {
1216 err = omap_sham_shash_digest(bctx->shash,
1217 crypto_shash_get_flags(bctx->shash),
1218 key, keylen, bctx->ipad);
1219 if (err)
1220 return err;
1221 keylen = ds;
1222 } else {
1223 memcpy(bctx->ipad, key, keylen);
1224 }
1225
1226 memset(bctx->ipad + keylen, 0, bs - keylen);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001227
Mark A. Greer0d373d62012-12-21 10:04:08 -07001228 if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
1229 memcpy(bctx->opad, bctx->ipad, bs);
1230
1231 for (i = 0; i < bs; i++) {
1232 bctx->ipad[i] ^= 0x36;
1233 bctx->opad[i] ^= 0x5c;
1234 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001235 }
1236
1237 return err;
1238}
1239
1240static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
1241{
1242 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1243 const char *alg_name = crypto_tfm_alg_name(tfm);
1244
1245 /* Allocate a fallback and abort if it failed. */
1246 tctx->fallback = crypto_alloc_shash(alg_name, 0,
1247 CRYPTO_ALG_NEED_FALLBACK);
1248 if (IS_ERR(tctx->fallback)) {
1249 pr_err("omap-sham: fallback driver '%s' "
1250 "could not be loaded.\n", alg_name);
1251 return PTR_ERR(tctx->fallback);
1252 }
1253
1254 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001255 sizeof(struct omap_sham_reqctx) + BUFLEN);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001256
1257 if (alg_base) {
1258 struct omap_sham_hmac_ctx *bctx = tctx->base;
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001259 tctx->flags |= BIT(FLAGS_HMAC);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001260 bctx->shash = crypto_alloc_shash(alg_base, 0,
1261 CRYPTO_ALG_NEED_FALLBACK);
1262 if (IS_ERR(bctx->shash)) {
1263 pr_err("omap-sham: base driver '%s' "
1264 "could not be loaded.\n", alg_base);
1265 crypto_free_shash(tctx->fallback);
1266 return PTR_ERR(bctx->shash);
1267 }
1268
1269 }
1270
1271 return 0;
1272}
1273
1274static int omap_sham_cra_init(struct crypto_tfm *tfm)
1275{
1276 return omap_sham_cra_init_alg(tfm, NULL);
1277}
1278
1279static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
1280{
1281 return omap_sham_cra_init_alg(tfm, "sha1");
1282}
1283
Mark A. Greerd20fb182012-12-21 10:04:09 -07001284static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
1285{
1286 return omap_sham_cra_init_alg(tfm, "sha224");
1287}
1288
1289static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
1290{
1291 return omap_sham_cra_init_alg(tfm, "sha256");
1292}
1293
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001294static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
1295{
1296 return omap_sham_cra_init_alg(tfm, "md5");
1297}
1298
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301299static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
1300{
1301 return omap_sham_cra_init_alg(tfm, "sha384");
1302}
1303
1304static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
1305{
1306 return omap_sham_cra_init_alg(tfm, "sha512");
1307}
1308
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001309static void omap_sham_cra_exit(struct crypto_tfm *tfm)
1310{
1311 struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
1312
1313 crypto_free_shash(tctx->fallback);
1314 tctx->fallback = NULL;
1315
Dmitry Kasatkinea1fd222011-06-02 21:10:05 +03001316 if (tctx->flags & BIT(FLAGS_HMAC)) {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001317 struct omap_sham_hmac_ctx *bctx = tctx->base;
1318 crypto_free_shash(bctx->shash);
1319 }
1320}
1321
Mark A. Greerd20fb182012-12-21 10:04:09 -07001322static struct ahash_alg algs_sha1_md5[] = {
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001323{
1324 .init = omap_sham_init,
1325 .update = omap_sham_update,
1326 .final = omap_sham_final,
1327 .finup = omap_sham_finup,
1328 .digest = omap_sham_digest,
1329 .halg.digestsize = SHA1_DIGEST_SIZE,
1330 .halg.base = {
1331 .cra_name = "sha1",
1332 .cra_driver_name = "omap-sha1",
1333 .cra_priority = 100,
1334 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001335 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001336 CRYPTO_ALG_ASYNC |
1337 CRYPTO_ALG_NEED_FALLBACK,
1338 .cra_blocksize = SHA1_BLOCK_SIZE,
1339 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1340 .cra_alignmask = 0,
1341 .cra_module = THIS_MODULE,
1342 .cra_init = omap_sham_cra_init,
1343 .cra_exit = omap_sham_cra_exit,
1344 }
1345},
1346{
1347 .init = omap_sham_init,
1348 .update = omap_sham_update,
1349 .final = omap_sham_final,
1350 .finup = omap_sham_finup,
1351 .digest = omap_sham_digest,
1352 .halg.digestsize = MD5_DIGEST_SIZE,
1353 .halg.base = {
1354 .cra_name = "md5",
1355 .cra_driver_name = "omap-md5",
1356 .cra_priority = 100,
1357 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001358 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001359 CRYPTO_ALG_ASYNC |
1360 CRYPTO_ALG_NEED_FALLBACK,
1361 .cra_blocksize = SHA1_BLOCK_SIZE,
1362 .cra_ctxsize = sizeof(struct omap_sham_ctx),
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001363 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001364 .cra_module = THIS_MODULE,
1365 .cra_init = omap_sham_cra_init,
1366 .cra_exit = omap_sham_cra_exit,
1367 }
1368},
1369{
1370 .init = omap_sham_init,
1371 .update = omap_sham_update,
1372 .final = omap_sham_final,
1373 .finup = omap_sham_finup,
1374 .digest = omap_sham_digest,
1375 .setkey = omap_sham_setkey,
1376 .halg.digestsize = SHA1_DIGEST_SIZE,
1377 .halg.base = {
1378 .cra_name = "hmac(sha1)",
1379 .cra_driver_name = "omap-hmac-sha1",
1380 .cra_priority = 100,
1381 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001382 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001383 CRYPTO_ALG_ASYNC |
1384 CRYPTO_ALG_NEED_FALLBACK,
1385 .cra_blocksize = SHA1_BLOCK_SIZE,
1386 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1387 sizeof(struct omap_sham_hmac_ctx),
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001388 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001389 .cra_module = THIS_MODULE,
1390 .cra_init = omap_sham_cra_sha1_init,
1391 .cra_exit = omap_sham_cra_exit,
1392 }
1393},
1394{
1395 .init = omap_sham_init,
1396 .update = omap_sham_update,
1397 .final = omap_sham_final,
1398 .finup = omap_sham_finup,
1399 .digest = omap_sham_digest,
1400 .setkey = omap_sham_setkey,
1401 .halg.digestsize = MD5_DIGEST_SIZE,
1402 .halg.base = {
1403 .cra_name = "hmac(md5)",
1404 .cra_driver_name = "omap-hmac-md5",
1405 .cra_priority = 100,
1406 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
Nikos Mavrogiannopoulosd912bb72011-11-01 13:39:56 +01001407 CRYPTO_ALG_KERN_DRIVER_ONLY |
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001408 CRYPTO_ALG_ASYNC |
1409 CRYPTO_ALG_NEED_FALLBACK,
1410 .cra_blocksize = SHA1_BLOCK_SIZE,
1411 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1412 sizeof(struct omap_sham_hmac_ctx),
Dmitry Kasatkin798eed52010-11-19 16:04:26 +02001413 .cra_alignmask = OMAP_ALIGN_MASK,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001414 .cra_module = THIS_MODULE,
1415 .cra_init = omap_sham_cra_md5_init,
1416 .cra_exit = omap_sham_cra_exit,
1417 }
1418}
1419};
1420
Mark A. Greerd20fb182012-12-21 10:04:09 -07001421/* OMAP4 has some algs in addition to what OMAP2 has */
1422static struct ahash_alg algs_sha224_sha256[] = {
1423{
1424 .init = omap_sham_init,
1425 .update = omap_sham_update,
1426 .final = omap_sham_final,
1427 .finup = omap_sham_finup,
1428 .digest = omap_sham_digest,
1429 .halg.digestsize = SHA224_DIGEST_SIZE,
1430 .halg.base = {
1431 .cra_name = "sha224",
1432 .cra_driver_name = "omap-sha224",
1433 .cra_priority = 100,
1434 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1435 CRYPTO_ALG_ASYNC |
1436 CRYPTO_ALG_NEED_FALLBACK,
1437 .cra_blocksize = SHA224_BLOCK_SIZE,
1438 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1439 .cra_alignmask = 0,
1440 .cra_module = THIS_MODULE,
1441 .cra_init = omap_sham_cra_init,
1442 .cra_exit = omap_sham_cra_exit,
1443 }
1444},
1445{
1446 .init = omap_sham_init,
1447 .update = omap_sham_update,
1448 .final = omap_sham_final,
1449 .finup = omap_sham_finup,
1450 .digest = omap_sham_digest,
1451 .halg.digestsize = SHA256_DIGEST_SIZE,
1452 .halg.base = {
1453 .cra_name = "sha256",
1454 .cra_driver_name = "omap-sha256",
1455 .cra_priority = 100,
1456 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1457 CRYPTO_ALG_ASYNC |
1458 CRYPTO_ALG_NEED_FALLBACK,
1459 .cra_blocksize = SHA256_BLOCK_SIZE,
1460 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1461 .cra_alignmask = 0,
1462 .cra_module = THIS_MODULE,
1463 .cra_init = omap_sham_cra_init,
1464 .cra_exit = omap_sham_cra_exit,
1465 }
1466},
1467{
1468 .init = omap_sham_init,
1469 .update = omap_sham_update,
1470 .final = omap_sham_final,
1471 .finup = omap_sham_finup,
1472 .digest = omap_sham_digest,
1473 .setkey = omap_sham_setkey,
1474 .halg.digestsize = SHA224_DIGEST_SIZE,
1475 .halg.base = {
1476 .cra_name = "hmac(sha224)",
1477 .cra_driver_name = "omap-hmac-sha224",
1478 .cra_priority = 100,
1479 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1480 CRYPTO_ALG_ASYNC |
1481 CRYPTO_ALG_NEED_FALLBACK,
1482 .cra_blocksize = SHA224_BLOCK_SIZE,
1483 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1484 sizeof(struct omap_sham_hmac_ctx),
1485 .cra_alignmask = OMAP_ALIGN_MASK,
1486 .cra_module = THIS_MODULE,
1487 .cra_init = omap_sham_cra_sha224_init,
1488 .cra_exit = omap_sham_cra_exit,
1489 }
1490},
1491{
1492 .init = omap_sham_init,
1493 .update = omap_sham_update,
1494 .final = omap_sham_final,
1495 .finup = omap_sham_finup,
1496 .digest = omap_sham_digest,
1497 .setkey = omap_sham_setkey,
1498 .halg.digestsize = SHA256_DIGEST_SIZE,
1499 .halg.base = {
1500 .cra_name = "hmac(sha256)",
1501 .cra_driver_name = "omap-hmac-sha256",
1502 .cra_priority = 100,
1503 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1504 CRYPTO_ALG_ASYNC |
1505 CRYPTO_ALG_NEED_FALLBACK,
1506 .cra_blocksize = SHA256_BLOCK_SIZE,
1507 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1508 sizeof(struct omap_sham_hmac_ctx),
1509 .cra_alignmask = OMAP_ALIGN_MASK,
1510 .cra_module = THIS_MODULE,
1511 .cra_init = omap_sham_cra_sha256_init,
1512 .cra_exit = omap_sham_cra_exit,
1513 }
1514},
1515};
1516
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301517static struct ahash_alg algs_sha384_sha512[] = {
1518{
1519 .init = omap_sham_init,
1520 .update = omap_sham_update,
1521 .final = omap_sham_final,
1522 .finup = omap_sham_finup,
1523 .digest = omap_sham_digest,
1524 .halg.digestsize = SHA384_DIGEST_SIZE,
1525 .halg.base = {
1526 .cra_name = "sha384",
1527 .cra_driver_name = "omap-sha384",
1528 .cra_priority = 100,
1529 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1530 CRYPTO_ALG_ASYNC |
1531 CRYPTO_ALG_NEED_FALLBACK,
1532 .cra_blocksize = SHA384_BLOCK_SIZE,
1533 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1534 .cra_alignmask = 0,
1535 .cra_module = THIS_MODULE,
1536 .cra_init = omap_sham_cra_init,
1537 .cra_exit = omap_sham_cra_exit,
1538 }
1539},
1540{
1541 .init = omap_sham_init,
1542 .update = omap_sham_update,
1543 .final = omap_sham_final,
1544 .finup = omap_sham_finup,
1545 .digest = omap_sham_digest,
1546 .halg.digestsize = SHA512_DIGEST_SIZE,
1547 .halg.base = {
1548 .cra_name = "sha512",
1549 .cra_driver_name = "omap-sha512",
1550 .cra_priority = 100,
1551 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1552 CRYPTO_ALG_ASYNC |
1553 CRYPTO_ALG_NEED_FALLBACK,
1554 .cra_blocksize = SHA512_BLOCK_SIZE,
1555 .cra_ctxsize = sizeof(struct omap_sham_ctx),
1556 .cra_alignmask = 0,
1557 .cra_module = THIS_MODULE,
1558 .cra_init = omap_sham_cra_init,
1559 .cra_exit = omap_sham_cra_exit,
1560 }
1561},
1562{
1563 .init = omap_sham_init,
1564 .update = omap_sham_update,
1565 .final = omap_sham_final,
1566 .finup = omap_sham_finup,
1567 .digest = omap_sham_digest,
1568 .setkey = omap_sham_setkey,
1569 .halg.digestsize = SHA384_DIGEST_SIZE,
1570 .halg.base = {
1571 .cra_name = "hmac(sha384)",
1572 .cra_driver_name = "omap-hmac-sha384",
1573 .cra_priority = 100,
1574 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1575 CRYPTO_ALG_ASYNC |
1576 CRYPTO_ALG_NEED_FALLBACK,
1577 .cra_blocksize = SHA384_BLOCK_SIZE,
1578 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1579 sizeof(struct omap_sham_hmac_ctx),
1580 .cra_alignmask = OMAP_ALIGN_MASK,
1581 .cra_module = THIS_MODULE,
1582 .cra_init = omap_sham_cra_sha384_init,
1583 .cra_exit = omap_sham_cra_exit,
1584 }
1585},
1586{
1587 .init = omap_sham_init,
1588 .update = omap_sham_update,
1589 .final = omap_sham_final,
1590 .finup = omap_sham_finup,
1591 .digest = omap_sham_digest,
1592 .setkey = omap_sham_setkey,
1593 .halg.digestsize = SHA512_DIGEST_SIZE,
1594 .halg.base = {
1595 .cra_name = "hmac(sha512)",
1596 .cra_driver_name = "omap-hmac-sha512",
1597 .cra_priority = 100,
1598 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
1599 CRYPTO_ALG_ASYNC |
1600 CRYPTO_ALG_NEED_FALLBACK,
1601 .cra_blocksize = SHA512_BLOCK_SIZE,
1602 .cra_ctxsize = sizeof(struct omap_sham_ctx) +
1603 sizeof(struct omap_sham_hmac_ctx),
1604 .cra_alignmask = OMAP_ALIGN_MASK,
1605 .cra_module = THIS_MODULE,
1606 .cra_init = omap_sham_cra_sha512_init,
1607 .cra_exit = omap_sham_cra_exit,
1608 }
1609},
1610};
1611
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001612static void omap_sham_done_task(unsigned long data)
1613{
1614 struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001615 int err = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001616
Dmitry Kasatkin6cb3ffe2011-06-02 21:10:09 +03001617 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1618 omap_sham_handle_queue(dd, NULL);
1619 return;
1620 }
1621
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001622 if (test_bit(FLAGS_CPU, &dd->flags)) {
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301623 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1624 /* hash or semi-hash ready */
1625 err = omap_sham_update_cpu(dd);
1626 if (err != -EINPROGRESS)
1627 goto finish;
1628 }
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001629 } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
1630 if (test_and_clear_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
1631 omap_sham_update_dma_stop(dd);
1632 if (dd->err) {
1633 err = dd->err;
1634 goto finish;
1635 }
1636 }
1637 if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
1638 /* hash or semi-hash ready */
1639 clear_bit(FLAGS_DMA_READY, &dd->flags);
Dmitry Kasatkin887c8832010-11-19 16:04:29 +02001640 err = omap_sham_update_dma_start(dd);
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001641 if (err != -EINPROGRESS)
1642 goto finish;
1643 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001644 }
1645
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001646 return;
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +02001647
Dmitry Kasatkin6c63db82011-06-02 21:10:10 +03001648finish:
1649 dev_dbg(dd->dev, "update done: err: %d\n", err);
1650 /* finish curent request */
1651 omap_sham_finish_req(dd->req, err);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001652}
1653
Mark A. Greer0d373d62012-12-21 10:04:08 -07001654static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
1655{
1656 if (!test_bit(FLAGS_BUSY, &dd->flags)) {
1657 dev_warn(dd->dev, "Interrupt when no active requests.\n");
1658 } else {
1659 set_bit(FLAGS_OUTPUT_READY, &dd->flags);
1660 tasklet_schedule(&dd->done_task);
1661 }
1662
1663 return IRQ_HANDLED;
1664}
1665
1666static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001667{
1668 struct omap_sham_dev *dd = dev_id;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001669
Dmitry Kasatkined3ea9a82011-06-02 21:10:07 +03001670 if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001671 /* final -> allow device to go to power-saving mode */
1672 omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
1673
1674 omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
1675 SHA_REG_CTRL_OUTPUT_READY);
1676 omap_sham_read(dd, SHA_REG_CTRL);
1677
Mark A. Greer0d373d62012-12-21 10:04:08 -07001678 return omap_sham_irq_common(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001679}
1680
Mark A. Greer0d373d62012-12-21 10:04:08 -07001681static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001682{
Mark A. Greer0d373d62012-12-21 10:04:08 -07001683 struct omap_sham_dev *dd = dev_id;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001684
Mark A. Greer0d373d62012-12-21 10:04:08 -07001685 omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
Dmitry Kasatkin3e133c82010-11-19 16:04:24 +02001686
Mark A. Greer0d373d62012-12-21 10:04:08 -07001687 return omap_sham_irq_common(dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001688}
1689
Mark A. Greerd20fb182012-12-21 10:04:09 -07001690static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
1691 {
1692 .algs_list = algs_sha1_md5,
1693 .size = ARRAY_SIZE(algs_sha1_md5),
1694 },
1695};
1696
Mark A. Greer0d373d62012-12-21 10:04:08 -07001697static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
Mark A. Greerd20fb182012-12-21 10:04:09 -07001698 .algs_info = omap_sham_algs_info_omap2,
1699 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
Mark A. Greer0d373d62012-12-21 10:04:08 -07001700 .flags = BIT(FLAGS_BE32_SHA1),
1701 .digest_size = SHA1_DIGEST_SIZE,
1702 .copy_hash = omap_sham_copy_hash_omap2,
1703 .write_ctrl = omap_sham_write_ctrl_omap2,
1704 .trigger = omap_sham_trigger_omap2,
1705 .poll_irq = omap_sham_poll_irq_omap2,
1706 .intr_hdlr = omap_sham_irq_omap2,
1707 .idigest_ofs = 0x00,
1708 .din_ofs = 0x1c,
1709 .digcnt_ofs = 0x14,
1710 .rev_ofs = 0x5c,
1711 .mask_ofs = 0x60,
1712 .sysstatus_ofs = 0x64,
1713 .major_mask = 0xf0,
1714 .major_shift = 4,
1715 .minor_mask = 0x0f,
1716 .minor_shift = 0,
1717};
1718
Mark A. Greer03feec92012-12-21 10:04:06 -07001719#ifdef CONFIG_OF
Mark A. Greerd20fb182012-12-21 10:04:09 -07001720static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
1721 {
1722 .algs_list = algs_sha1_md5,
1723 .size = ARRAY_SIZE(algs_sha1_md5),
1724 },
1725 {
1726 .algs_list = algs_sha224_sha256,
1727 .size = ARRAY_SIZE(algs_sha224_sha256),
1728 },
1729};
1730
Mark A. Greer0d373d62012-12-21 10:04:08 -07001731static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
Mark A. Greerd20fb182012-12-21 10:04:09 -07001732 .algs_info = omap_sham_algs_info_omap4,
1733 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
Mark A. Greer0d373d62012-12-21 10:04:08 -07001734 .flags = BIT(FLAGS_AUTO_XOR),
1735 .digest_size = SHA256_DIGEST_SIZE,
1736 .copy_hash = omap_sham_copy_hash_omap4,
1737 .write_ctrl = omap_sham_write_ctrl_omap4,
1738 .trigger = omap_sham_trigger_omap4,
1739 .poll_irq = omap_sham_poll_irq_omap4,
1740 .intr_hdlr = omap_sham_irq_omap4,
1741 .idigest_ofs = 0x020,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301742 .odigest_ofs = 0x0,
Mark A. Greer0d373d62012-12-21 10:04:08 -07001743 .din_ofs = 0x080,
1744 .digcnt_ofs = 0x040,
1745 .rev_ofs = 0x100,
1746 .mask_ofs = 0x110,
1747 .sysstatus_ofs = 0x114,
Lokesh Vutlaeaef7e32013-07-26 12:29:14 +05301748 .mode_ofs = 0x44,
1749 .length_ofs = 0x48,
Mark A. Greer0d373d62012-12-21 10:04:08 -07001750 .major_mask = 0x0700,
1751 .major_shift = 8,
1752 .minor_mask = 0x003f,
1753 .minor_shift = 0,
1754};
1755
Lokesh Vutla7d7c7042013-07-26 12:29:15 +05301756static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
1757 {
1758 .algs_list = algs_sha1_md5,
1759 .size = ARRAY_SIZE(algs_sha1_md5),
1760 },
1761 {
1762 .algs_list = algs_sha224_sha256,
1763 .size = ARRAY_SIZE(algs_sha224_sha256),
1764 },
1765 {
1766 .algs_list = algs_sha384_sha512,
1767 .size = ARRAY_SIZE(algs_sha384_sha512),
1768 },
1769};
1770
1771static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
1772 .algs_info = omap_sham_algs_info_omap5,
1773 .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
1774 .flags = BIT(FLAGS_AUTO_XOR),
1775 .digest_size = SHA512_DIGEST_SIZE,
1776 .copy_hash = omap_sham_copy_hash_omap4,
1777 .write_ctrl = omap_sham_write_ctrl_omap4,
1778 .trigger = omap_sham_trigger_omap4,
1779 .poll_irq = omap_sham_poll_irq_omap4,
1780 .intr_hdlr = omap_sham_irq_omap4,
1781 .idigest_ofs = 0x240,
1782 .odigest_ofs = 0x200,
1783 .din_ofs = 0x080,
1784 .digcnt_ofs = 0x280,
1785 .rev_ofs = 0x100,
1786 .mask_ofs = 0x110,
1787 .sysstatus_ofs = 0x114,
1788 .mode_ofs = 0x284,
1789 .length_ofs = 0x288,
1790 .major_mask = 0x0700,
1791 .major_shift = 8,
1792 .minor_mask = 0x003f,
1793 .minor_shift = 0,
1794};
1795
Mark A. Greer03feec92012-12-21 10:04:06 -07001796static const struct of_device_id omap_sham_of_match[] = {
1797 {
1798 .compatible = "ti,omap2-sham",
Mark A. Greer0d373d62012-12-21 10:04:08 -07001799 .data = &omap_sham_pdata_omap2,
1800 },
1801 {
Pali Roháreddca852015-02-26 14:49:53 +01001802 .compatible = "ti,omap3-sham",
1803 .data = &omap_sham_pdata_omap2,
1804 },
1805 {
Mark A. Greer0d373d62012-12-21 10:04:08 -07001806 .compatible = "ti,omap4-sham",
1807 .data = &omap_sham_pdata_omap4,
Mark A. Greer03feec92012-12-21 10:04:06 -07001808 },
Lokesh Vutla7d7c7042013-07-26 12:29:15 +05301809 {
1810 .compatible = "ti,omap5-sham",
1811 .data = &omap_sham_pdata_omap5,
1812 },
Mark A. Greer03feec92012-12-21 10:04:06 -07001813 {},
1814};
1815MODULE_DEVICE_TABLE(of, omap_sham_of_match);
1816
1817static int omap_sham_get_res_of(struct omap_sham_dev *dd,
1818 struct device *dev, struct resource *res)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001819{
Mark A. Greer03feec92012-12-21 10:04:06 -07001820 struct device_node *node = dev->of_node;
1821 const struct of_device_id *match;
1822 int err = 0;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001823
Mark A. Greer03feec92012-12-21 10:04:06 -07001824 match = of_match_device(of_match_ptr(omap_sham_of_match), dev);
1825 if (!match) {
1826 dev_err(dev, "no compatible OF match\n");
1827 err = -EINVAL;
1828 goto err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001829 }
Samu Onkalo584db6a2010-09-03 19:20:19 +08001830
Mark A. Greer03feec92012-12-21 10:04:06 -07001831 err = of_address_to_resource(node, 0, res);
1832 if (err < 0) {
1833 dev_err(dev, "can't translate OF node address\n");
1834 err = -EINVAL;
1835 goto err;
1836 }
1837
Thierry Redingf7578492013-09-18 15:24:44 +02001838 dd->irq = irq_of_parse_and_map(node, 0);
Mark A. Greer03feec92012-12-21 10:04:06 -07001839 if (!dd->irq) {
1840 dev_err(dev, "can't translate OF irq value\n");
1841 err = -EINVAL;
1842 goto err;
1843 }
1844
1845 dd->dma = -1; /* Dummy value that's unused */
Mark A. Greer0d373d62012-12-21 10:04:08 -07001846 dd->pdata = match->data;
Mark A. Greer03feec92012-12-21 10:04:06 -07001847
1848err:
1849 return err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001850}
Mark A. Greer03feec92012-12-21 10:04:06 -07001851#else
Mark A. Greerc3c3b322013-01-15 13:53:02 -07001852static const struct of_device_id omap_sham_of_match[] = {
1853 {},
1854};
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001855
Mark A. Greerc3c3b322013-01-15 13:53:02 -07001856static int omap_sham_get_res_of(struct omap_sham_dev *dd,
Mark A. Greer03feec92012-12-21 10:04:06 -07001857 struct device *dev, struct resource *res)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001858{
Mark A. Greer03feec92012-12-21 10:04:06 -07001859 return -EINVAL;
1860}
1861#endif
1862
1863static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
1864 struct platform_device *pdev, struct resource *res)
1865{
1866 struct device *dev = &pdev->dev;
1867 struct resource *r;
1868 int err = 0;
1869
1870 /* Get the base address */
1871 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1872 if (!r) {
1873 dev_err(dev, "no MEM resource info\n");
1874 err = -ENODEV;
1875 goto err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001876 }
Mark A. Greer03feec92012-12-21 10:04:06 -07001877 memcpy(res, r, sizeof(*res));
1878
1879 /* Get the IRQ */
1880 dd->irq = platform_get_irq(pdev, 0);
1881 if (dd->irq < 0) {
1882 dev_err(dev, "no IRQ resource info\n");
1883 err = dd->irq;
1884 goto err;
1885 }
1886
1887 /* Get the DMA */
1888 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1889 if (!r) {
1890 dev_err(dev, "no DMA resource info\n");
1891 err = -ENODEV;
1892 goto err;
1893 }
1894 dd->dma = r->start;
1895
Mark A. Greer0d373d62012-12-21 10:04:08 -07001896 /* Only OMAP2/3 can be non-DT */
1897 dd->pdata = &omap_sham_pdata_omap2;
1898
Mark A. Greer03feec92012-12-21 10:04:06 -07001899err:
1900 return err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001901}
1902
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08001903static int omap_sham_probe(struct platform_device *pdev)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001904{
1905 struct omap_sham_dev *dd;
1906 struct device *dev = &pdev->dev;
Mark A. Greer03feec92012-12-21 10:04:06 -07001907 struct resource res;
Mark A. Greerdfd061d2012-12-21 10:04:04 -07001908 dma_cap_mask_t mask;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001909 int err, i, j;
Mark A. Greer0d373d62012-12-21 10:04:08 -07001910 u32 rev;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001911
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301912 dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001913 if (dd == NULL) {
1914 dev_err(dev, "unable to alloc data struct.\n");
1915 err = -ENOMEM;
1916 goto data_err;
1917 }
1918 dd->dev = dev;
1919 platform_set_drvdata(pdev, dd);
1920
1921 INIT_LIST_HEAD(&dd->list);
1922 spin_lock_init(&dd->lock);
1923 tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001924 crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
1925
Mark A. Greer03feec92012-12-21 10:04:06 -07001926 err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
1927 omap_sham_get_res_pdev(dd, pdev, &res);
1928 if (err)
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301929 goto data_err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001930
Laurent Navet30862282013-05-02 14:00:38 +02001931 dd->io_base = devm_ioremap_resource(dev, &res);
1932 if (IS_ERR(dd->io_base)) {
1933 err = PTR_ERR(dd->io_base);
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301934 goto data_err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001935 }
Mark A. Greer03feec92012-12-21 10:04:06 -07001936 dd->phys_base = res.start;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001937
Lokesh Vutla0de9c382013-07-26 12:29:16 +05301938 err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
1939 IRQF_TRIGGER_NONE, dev_name(dev), dd);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001940 if (err) {
Lokesh Vutla0de9c382013-07-26 12:29:16 +05301941 dev_err(dev, "unable to request irq %d, err = %d\n",
1942 dd->irq, err);
Lokesh Vutla7a7e4b72013-07-26 12:29:17 +05301943 goto data_err;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001944 }
1945
Mark A. Greerdfd061d2012-12-21 10:04:04 -07001946 dma_cap_zero(mask);
1947 dma_cap_set(DMA_SLAVE, mask);
1948
Mark A. Greer0e87e732012-12-21 10:04:07 -07001949 dd->dma_lch = dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
1950 &dd->dma, dev, "rx");
Mark A. Greerdfd061d2012-12-21 10:04:04 -07001951 if (!dd->dma_lch) {
Lokesh Vutlab8411cc2013-08-20 20:32:34 +05301952 dd->polling_mode = 1;
1953 dev_dbg(dev, "using polling mode instead of dma\n");
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001954 }
1955
Mark A. Greer0d373d62012-12-21 10:04:08 -07001956 dd->flags |= dd->pdata->flags;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001957
Mark A. Greerb359f032012-12-21 10:04:02 -07001958 pm_runtime_enable(dev);
Vutla, Lokeshb0a3d892015-03-31 09:52:24 +05301959 pm_runtime_irq_safe(dev);
Pali Rohár604c3102015-03-08 11:01:01 +01001960
1961 err = pm_runtime_get_sync(dev);
1962 if (err < 0) {
1963 dev_err(dev, "failed to get sync: %d\n", err);
1964 goto err_pm;
1965 }
1966
Mark A. Greer0d373d62012-12-21 10:04:08 -07001967 rev = omap_sham_read(dd, SHA_REG_REV(dd));
1968 pm_runtime_put_sync(&pdev->dev);
Mark A. Greerb359f032012-12-21 10:04:02 -07001969
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001970 dev_info(dev, "hw accel on OMAP rev %u.%u\n",
Mark A. Greer0d373d62012-12-21 10:04:08 -07001971 (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
1972 (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001973
1974 spin_lock(&sham.lock);
1975 list_add_tail(&dd->list, &sham.dev_list);
1976 spin_unlock(&sham.lock);
1977
Mark A. Greerd20fb182012-12-21 10:04:09 -07001978 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1979 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1980 err = crypto_register_ahash(
1981 &dd->pdata->algs_info[i].algs_list[j]);
1982 if (err)
1983 goto err_algs;
1984
1985 dd->pdata->algs_info[i].registered++;
1986 }
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08001987 }
1988
1989 return 0;
1990
1991err_algs:
Mark A. Greerd20fb182012-12-21 10:04:09 -07001992 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1993 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1994 crypto_unregister_ahash(
1995 &dd->pdata->algs_info[i].algs_list[j]);
Pali Rohár604c3102015-03-08 11:01:01 +01001996err_pm:
Mark A. Greerb359f032012-12-21 10:04:02 -07001997 pm_runtime_disable(dev);
Mark A. Greerf13ab862013-11-12 13:12:27 -07001998 if (dd->dma_lch)
1999 dma_release_channel(dd->dma_lch);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002000data_err:
2001 dev_err(dev, "initialization failed.\n");
2002
2003 return err;
2004}
2005
Greg Kroah-Hartman49cfe4d2012-12-21 13:14:09 -08002006static int omap_sham_remove(struct platform_device *pdev)
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002007{
2008 static struct omap_sham_dev *dd;
Mark A. Greerd20fb182012-12-21 10:04:09 -07002009 int i, j;
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002010
2011 dd = platform_get_drvdata(pdev);
2012 if (!dd)
2013 return -ENODEV;
2014 spin_lock(&sham.lock);
2015 list_del(&dd->list);
2016 spin_unlock(&sham.lock);
Mark A. Greerd20fb182012-12-21 10:04:09 -07002017 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
2018 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
2019 crypto_unregister_ahash(
2020 &dd->pdata->algs_info[i].algs_list[j]);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002021 tasklet_kill(&dd->done_task);
Mark A. Greerb359f032012-12-21 10:04:02 -07002022 pm_runtime_disable(&pdev->dev);
Mark A. Greerf13ab862013-11-12 13:12:27 -07002023
2024 if (dd->dma_lch)
2025 dma_release_channel(dd->dma_lch);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002026
2027 return 0;
2028}
2029
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002030#ifdef CONFIG_PM_SLEEP
2031static int omap_sham_suspend(struct device *dev)
2032{
2033 pm_runtime_put_sync(dev);
2034 return 0;
2035}
2036
2037static int omap_sham_resume(struct device *dev)
2038{
Pali Rohár604c3102015-03-08 11:01:01 +01002039 int err = pm_runtime_get_sync(dev);
2040 if (err < 0) {
2041 dev_err(dev, "failed to get sync: %d\n", err);
2042 return err;
2043 }
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002044 return 0;
2045}
2046#endif
2047
Jingoo Hanae12fe22014-02-27 20:33:32 +09002048static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002049
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002050static struct platform_driver omap_sham_driver = {
2051 .probe = omap_sham_probe,
2052 .remove = omap_sham_remove,
2053 .driver = {
2054 .name = "omap-sham",
Mark A. Greer3b3f4402012-12-21 10:04:03 -07002055 .pm = &omap_sham_pm_ops,
Mark A. Greer03feec92012-12-21 10:04:06 -07002056 .of_match_table = omap_sham_of_match,
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002057 },
2058};
2059
Sachin Kamat02613702013-03-04 15:09:43 +05302060module_platform_driver(omap_sham_driver);
Dmitry Kasatkin8628e7c2010-05-03 11:10:59 +08002061
2062MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
2063MODULE_LICENSE("GPL v2");
2064MODULE_AUTHOR("Dmitry Kasatkin");
Joni Lapilainen718249d2013-10-26 23:00:41 +02002065MODULE_ALIAS("platform:omap-sham");