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gerrit-public.fairphone.software / kernel / msm-4.9 / eaec1d675c194965081297014503938a9f58e2f7 / . / arch / arm / boot / dts / spear600.dtsi
blob: 9f60a7b6a42bf42e0b84584d94b48b7888ea58a0 [file] [log] [blame]
Stefan Roese9652e8b2012-03-16 14:03:23 +0100[diff] [blame]1/*
2 * Copyright 2012 Stefan Roese <sr@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 compatible = "st,spear600";
16
17 cpus {
Lorenzo Pieralisi78e65732013-04-18 18:41:22 +0100[diff] [blame]18 #address-cells = <0>;
19 #size-cells = <0>;
20
21 cpu {
22 compatible = "arm,arm926ej-s";
23 device_type = "cpu";
Stefan Roese9652e8b2012-03-16 14:03:23 +0100[diff] [blame]24 };
25 };
26
27 memory {
28 device_type = "memory";
29 reg = <0 0x40000000>;
30 };
31
32 ahb {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "simple-bus";
36 ranges = <0xd0000000 0xd0000000 0x30000000>;
37
38 vic0: interrupt-controller@f1100000 {
39 compatible = "arm,pl190-vic";
40 interrupt-controller;
41 reg = <0xf1100000 0x1000>;
42 #interrupt-cells = <1>;
43 };
44
45 vic1: interrupt-controller@f1000000 {
46 compatible = "arm,pl190-vic";
47 interrupt-controller;
48 reg = <0xf1000000 0x1000>;
49 #interrupt-cells = <1>;
50 };
51
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]52 clcd@fc200000 {
53 compatible = "arm,pl110", "arm,primecell";
54 reg = <0xfc200000 0x1000>;
55 interrupt-parent = <&vic1>;
56 interrupts = <12>;
57 status = "disabled";
58 };
59
Viresh Kumar0b7ee712012-03-26 10:29:23 +0530[diff] [blame]60 dma@fc400000 {
61 compatible = "arm,pl080", "arm,primecell";
62 reg = <0xfc400000 0x1000>;
63 interrupt-parent = <&vic1>;
64 interrupts = <10>;
65 status = "disabled";
66 };
67
Stefan Roese9652e8b2012-03-16 14:03:23 +0100[diff] [blame]68 gmac: ethernet@e0800000 {
69 compatible = "st,spear600-gmac";
70 reg = <0xe0800000 0x8000>;
71 interrupt-parent = <&vic1>;
72 interrupts = <24 23>;
73 interrupt-names = "macirq", "eth_wake_irq";
Deepak Sikri4c7a0782012-08-09 13:18:40 +0530[diff] [blame]74 phy-mode = "gmii";
Stefan Roese9652e8b2012-03-16 14:03:23 +0100[diff] [blame]75 status = "disabled";
76 };
77
78 fsmc: flash@d1800000 {
79 compatible = "st,spear600-fsmc-nand";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0xd1800000 0x1000 /* FSMC Register */
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200[diff] [blame]83 0xd2000000 0x0010 /* NAND Base DATA */
84 0xd2020000 0x0010 /* NAND Base ADDR */
85 0xd2010000 0x0010>; /* NAND Base CMD */
86 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
Stefan Roese9652e8b2012-03-16 14:03:23 +0100[diff] [blame]87 status = "disabled";
88 };
89
90 smi: flash@fc000000 {
91 compatible = "st,spear600-smi";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0xfc000000 0x1000>;
95 interrupt-parent = <&vic1>;
96 interrupts = <12>;
97 status = "disabled";
98 };
99
100 ehci@e1800000 {
101 compatible = "st,spear600-ehci", "usb-ehci";
102 reg = <0xe1800000 0x1000>;
103 interrupt-parent = <&vic1>;
104 interrupts = <27>;
105 status = "disabled";
106 };
107
108 ehci@e2000000 {
109 compatible = "st,spear600-ehci", "usb-ehci";
110 reg = <0xe2000000 0x1000>;
111 interrupt-parent = <&vic1>;
112 interrupts = <29>;
113 status = "disabled";
114 };
115
116 ohci@e1900000 {
117 compatible = "st,spear600-ohci", "usb-ohci";
118 reg = <0xe1900000 0x1000>;
119 interrupt-parent = <&vic1>;
120 interrupts = <26>;
121 status = "disabled";
122 };
123
124 ohci@e2100000 {
125 compatible = "st,spear600-ohci", "usb-ohci";
126 reg = <0xe2100000 0x1000>;
127 interrupt-parent = <&vic1>;
128 interrupts = <28>;
129 status = "disabled";
130 };
131
132 apb {
133 #address-cells = <1>;
134 #size-cells = <1>;
135 compatible = "simple-bus";
136 ranges = <0xd0000000 0xd0000000 0x30000000>;
137
138 serial@d0000000 {
139 compatible = "arm,pl011", "arm,primecell";
140 reg = <0xd0000000 0x1000>;
141 interrupt-parent = <&vic0>;
142 interrupts = <24>;
143 status = "disabled";
144 };
145
146 serial@d0080000 {
147 compatible = "arm,pl011", "arm,primecell";
148 reg = <0xd0080000 0x1000>;
149 interrupt-parent = <&vic0>;
150 interrupts = <25>;
151 status = "disabled";
152 };
153
154 /* local/cpu GPIO */
155 gpio0: gpio@f0100000 {
156 #gpio-cells = <2>;
157 compatible = "arm,pl061", "arm,primecell";
158 gpio-controller;
159 reg = <0xf0100000 0x1000>;
160 interrupt-parent = <&vic0>;
161 interrupts = <18>;
162 };
163
164 /* basic GPIO */
165 gpio1: gpio@fc980000 {
166 #gpio-cells = <2>;
167 compatible = "arm,pl061", "arm,primecell";
168 gpio-controller;
169 reg = <0xfc980000 0x1000>;
170 interrupt-parent = <&vic1>;
171 interrupts = <19>;
172 };
173
174 /* appl GPIO */
175 gpio2: gpio@d8100000 {
176 #gpio-cells = <2>;
177 compatible = "arm,pl061", "arm,primecell";
178 gpio-controller;
179 reg = <0xd8100000 0x1000>;
180 interrupt-parent = <&vic1>;
181 interrupts = <4>;
182 };
183
184 i2c@d0200000 {
185 #address-cells = <1>;
186 #size-cells = <0>;
187 compatible = "snps,designware-i2c";
188 reg = <0xd0200000 0x1000>;
189 interrupt-parent = <&vic0>;
190 interrupts = <28>;
191 status = "disabled";
192 };
Viresh Kumar30551c02012-04-21 13:15:37 +0530[diff] [blame]193
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]194 rtc@fc900000 {
195 compatible = "st,spear600-rtc";
196 reg = <0xfc900000 0x1000>;
197 interrupts = <10>;
198 status = "disabled";
199 };
200
Viresh Kumar30551c02012-04-21 13:15:37 +0530[diff] [blame]201 timer@f0000000 {
202 compatible = "st,spear-timer";
203 reg = <0xf0000000 0x400>;
Stefan Roese69c7e372012-05-11 10:41:01 +0200[diff] [blame]204 interrupt-parent = <&vic0>;
Viresh Kumar30551c02012-04-21 13:15:37 +0530[diff] [blame]205 interrupts = <16>;
206 };
Stefan Roese9652e8b2012-03-16 14:03:23 +0100[diff] [blame]207 };
208 };
209};