blob: e0e6af4e783b077ca01968ae54af1a2a622834fb [file] [log] [blame]
Chris Metcalf867e3592010-05-28 23:09:12 -04001/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * @file hypervisor.h
17 * The hypervisor's public API.
18 */
19
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040020#ifndef _HV_HV_H
21#define _HV_HV_H
Chris Metcalf867e3592010-05-28 23:09:12 -040022
Chris Metcalf867e3592010-05-28 23:09:12 -040023#include <arch/chip.h>
Chris Metcalffb702b92010-06-25 16:41:11 -040024
Chris Metcalf867e3592010-05-28 23:09:12 -040025/* Linux builds want unsigned long constants, but assembler wants numbers */
26#ifdef __ASSEMBLER__
27/** One, for assembler */
28#define __HV_SIZE_ONE 1
29#elif !defined(__tile__) && CHIP_VA_WIDTH() > 32
30/** One, for 64-bit on host */
31#define __HV_SIZE_ONE 1ULL
32#else
33/** One, for Linux */
34#define __HV_SIZE_ONE 1UL
35#endif
36
Chris Metcalf867e3592010-05-28 23:09:12 -040037/** The log2 of the span of a level-1 page table, in bytes.
38 */
39#define HV_LOG2_L1_SPAN 32
40
41/** The span of a level-1 page table, in bytes.
42 */
43#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
44
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040045/** The log2 of the initial size of small pages, in bytes.
46 * See HV_DEFAULT_PAGE_SIZE_SMALL.
Chris Metcalf5386e732011-05-02 16:21:12 -040047 */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040048#define HV_LOG2_DEFAULT_PAGE_SIZE_SMALL 16
Chris Metcalf5386e732011-05-02 16:21:12 -040049
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040050/** The initial size of small pages, in bytes. This value should be verified
Chris Metcalf867e3592010-05-28 23:09:12 -040051 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040052 * It may also be modified when installing a new context.
Chris Metcalf867e3592010-05-28 23:09:12 -040053 */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040054#define HV_DEFAULT_PAGE_SIZE_SMALL \
55 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_SMALL)
Chris Metcalf867e3592010-05-28 23:09:12 -040056
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040057/** The log2 of the initial size of large pages, in bytes.
58 * See HV_DEFAULT_PAGE_SIZE_LARGE.
Chris Metcalf5386e732011-05-02 16:21:12 -040059 */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040060#define HV_LOG2_DEFAULT_PAGE_SIZE_LARGE 24
Chris Metcalf5386e732011-05-02 16:21:12 -040061
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040062/** The initial size of large pages, in bytes. This value should be verified
Chris Metcalf867e3592010-05-28 23:09:12 -040063 * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040064 * It may also be modified when installing a new context.
Chris Metcalf867e3592010-05-28 23:09:12 -040065 */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -040066#define HV_DEFAULT_PAGE_SIZE_LARGE \
67 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_LARGE)
Chris Metcalf867e3592010-05-28 23:09:12 -040068
Chris Metcalf621b1952012-04-01 14:04:21 -040069#if CHIP_VA_WIDTH() > 32
70
71/** The log2 of the initial size of jumbo pages, in bytes.
72 * See HV_DEFAULT_PAGE_SIZE_JUMBO.
73 */
74#define HV_LOG2_DEFAULT_PAGE_SIZE_JUMBO 32
75
76/** The initial size of jumbo pages, in bytes. This value should
77 * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_JUMBO).
78 * It may also be modified when installing a new context.
79 */
80#define HV_DEFAULT_PAGE_SIZE_JUMBO \
81 (__HV_SIZE_ONE << HV_LOG2_DEFAULT_PAGE_SIZE_JUMBO)
82
83#endif
84
Chris Metcalf867e3592010-05-28 23:09:12 -040085/** The log2 of the granularity at which page tables must be aligned;
86 * in other words, the CPA for a page table must have this many zero
87 * bits at the bottom of the address.
88 */
89#define HV_LOG2_PAGE_TABLE_ALIGN 11
90
91/** The granularity at which page tables must be aligned.
92 */
93#define HV_PAGE_TABLE_ALIGN (__HV_SIZE_ONE << HV_LOG2_PAGE_TABLE_ALIGN)
94
95/** Normal start of hypervisor glue in client physical memory. */
96#define HV_GLUE_START_CPA 0x10000
97
98/** This much space is reserved at HV_GLUE_START_CPA
99 * for the hypervisor glue. The client program must start at
100 * some address higher than this, and in particular the address of
101 * its text section should be equal to zero modulo HV_PAGE_SIZE_LARGE
102 * so that relative offsets to the HV glue are correct.
103 */
104#define HV_GLUE_RESERVED_SIZE 0x10000
105
106/** Each entry in the hv dispatch array takes this many bytes. */
107#define HV_DISPATCH_ENTRY_SIZE 32
108
109/** Version of the hypervisor interface defined by this file */
Chris Metcalfc5399142013-05-02 15:29:04 -0400110#define _HV_VERSION 13
111
112/** Last version of the hypervisor interface with old hv_init() ABI.
113 *
114 * The change from version 12 to version 13 corresponds to launching
115 * the client by default at PL2 instead of PL1 (corresponding to the
116 * hv itself running at PL3 instead of PL2). To make this explicit,
117 * the hv_init() API was also extended so the client can report its
118 * desired PL, resulting in a more helpful failure diagnostic. If you
119 * call hv_init() with _HV_VERSION_OLD_HV_INIT and omit the client_pl
120 * argument, the hypervisor will assume client_pl = 1.
121 *
122 * Note that this is a deprecated solution and we do not expect to
123 * support clients of the Tilera hypervisor running at PL1 indefinitely.
124 */
125#define _HV_VERSION_OLD_HV_INIT 12
Chris Metcalf867e3592010-05-28 23:09:12 -0400126
127/* Index into hypervisor interface dispatch code blocks.
128 *
129 * Hypervisor calls are invoked from user space by calling code
130 * at an address HV_BASE_ADDRESS + (index) * HV_DISPATCH_ENTRY_SIZE,
131 * where index is one of these enum values.
132 *
133 * Normally a supervisor is expected to produce a set of symbols
134 * starting at HV_BASE_ADDRESS that obey this convention, but a user
135 * program could call directly through function pointers if desired.
136 *
137 * These numbers are part of the binary API and will not be changed
138 * without updating HV_VERSION, which should be a rare event.
139 */
140
141/** reserved. */
142#define _HV_DISPATCH_RESERVED 0
143
144/** hv_init */
145#define HV_DISPATCH_INIT 1
146
147/** hv_install_context */
148#define HV_DISPATCH_INSTALL_CONTEXT 2
149
150/** hv_sysconf */
151#define HV_DISPATCH_SYSCONF 3
152
153/** hv_get_rtc */
154#define HV_DISPATCH_GET_RTC 4
155
156/** hv_set_rtc */
157#define HV_DISPATCH_SET_RTC 5
158
159/** hv_flush_asid */
160#define HV_DISPATCH_FLUSH_ASID 6
161
162/** hv_flush_page */
163#define HV_DISPATCH_FLUSH_PAGE 7
164
165/** hv_flush_pages */
166#define HV_DISPATCH_FLUSH_PAGES 8
167
168/** hv_restart */
169#define HV_DISPATCH_RESTART 9
170
171/** hv_halt */
172#define HV_DISPATCH_HALT 10
173
174/** hv_power_off */
175#define HV_DISPATCH_POWER_OFF 11
176
177/** hv_inquire_physical */
178#define HV_DISPATCH_INQUIRE_PHYSICAL 12
179
180/** hv_inquire_memory_controller */
181#define HV_DISPATCH_INQUIRE_MEMORY_CONTROLLER 13
182
183/** hv_inquire_virtual */
184#define HV_DISPATCH_INQUIRE_VIRTUAL 14
185
186/** hv_inquire_asid */
187#define HV_DISPATCH_INQUIRE_ASID 15
188
189/** hv_nanosleep */
190#define HV_DISPATCH_NANOSLEEP 16
191
192/** hv_console_read_if_ready */
193#define HV_DISPATCH_CONSOLE_READ_IF_READY 17
194
195/** hv_console_write */
196#define HV_DISPATCH_CONSOLE_WRITE 18
197
198/** hv_downcall_dispatch */
199#define HV_DISPATCH_DOWNCALL_DISPATCH 19
200
201/** hv_inquire_topology */
202#define HV_DISPATCH_INQUIRE_TOPOLOGY 20
203
204/** hv_fs_findfile */
205#define HV_DISPATCH_FS_FINDFILE 21
206
207/** hv_fs_fstat */
208#define HV_DISPATCH_FS_FSTAT 22
209
210/** hv_fs_pread */
211#define HV_DISPATCH_FS_PREAD 23
212
213/** hv_physaddr_read64 */
214#define HV_DISPATCH_PHYSADDR_READ64 24
215
216/** hv_physaddr_write64 */
217#define HV_DISPATCH_PHYSADDR_WRITE64 25
218
219/** hv_get_command_line */
220#define HV_DISPATCH_GET_COMMAND_LINE 26
221
222/** hv_set_caching */
223#define HV_DISPATCH_SET_CACHING 27
224
225/** hv_bzero_page */
226#define HV_DISPATCH_BZERO_PAGE 28
227
228/** hv_register_message_state */
229#define HV_DISPATCH_REGISTER_MESSAGE_STATE 29
230
231/** hv_send_message */
232#define HV_DISPATCH_SEND_MESSAGE 30
233
234/** hv_receive_message */
235#define HV_DISPATCH_RECEIVE_MESSAGE 31
236
237/** hv_inquire_context */
238#define HV_DISPATCH_INQUIRE_CONTEXT 32
239
240/** hv_start_all_tiles */
241#define HV_DISPATCH_START_ALL_TILES 33
242
243/** hv_dev_open */
244#define HV_DISPATCH_DEV_OPEN 34
245
246/** hv_dev_close */
247#define HV_DISPATCH_DEV_CLOSE 35
248
249/** hv_dev_pread */
250#define HV_DISPATCH_DEV_PREAD 36
251
252/** hv_dev_pwrite */
253#define HV_DISPATCH_DEV_PWRITE 37
254
255/** hv_dev_poll */
256#define HV_DISPATCH_DEV_POLL 38
257
258/** hv_dev_poll_cancel */
259#define HV_DISPATCH_DEV_POLL_CANCEL 39
260
261/** hv_dev_preada */
262#define HV_DISPATCH_DEV_PREADA 40
263
264/** hv_dev_pwritea */
265#define HV_DISPATCH_DEV_PWRITEA 41
266
267/** hv_flush_remote */
268#define HV_DISPATCH_FLUSH_REMOTE 42
269
270/** hv_console_putc */
271#define HV_DISPATCH_CONSOLE_PUTC 43
272
273/** hv_inquire_tiles */
274#define HV_DISPATCH_INQUIRE_TILES 44
275
276/** hv_confstr */
277#define HV_DISPATCH_CONFSTR 45
278
279/** hv_reexec */
280#define HV_DISPATCH_REEXEC 46
281
282/** hv_set_command_line */
283#define HV_DISPATCH_SET_COMMAND_LINE 47
284
Chris Metcalffb702b92010-06-25 16:41:11 -0400285#if !CHIP_HAS_IPI()
286
287/** hv_clear_intr */
288#define HV_DISPATCH_CLEAR_INTR 48
Chris Metcalf867e3592010-05-28 23:09:12 -0400289
290/** hv_enable_intr */
291#define HV_DISPATCH_ENABLE_INTR 49
292
293/** hv_disable_intr */
294#define HV_DISPATCH_DISABLE_INTR 50
295
Chris Metcalffb702b92010-06-25 16:41:11 -0400296/** hv_raise_intr */
297#define HV_DISPATCH_RAISE_INTR 51
298
Chris Metcalf867e3592010-05-28 23:09:12 -0400299/** hv_trigger_ipi */
Chris Metcalffb702b92010-06-25 16:41:11 -0400300#define HV_DISPATCH_TRIGGER_IPI 52
301
302#endif /* !CHIP_HAS_IPI() */
Chris Metcalf867e3592010-05-28 23:09:12 -0400303
304/** hv_store_mapping */
Chris Metcalffb702b92010-06-25 16:41:11 -0400305#define HV_DISPATCH_STORE_MAPPING 53
Chris Metcalf867e3592010-05-28 23:09:12 -0400306
307/** hv_inquire_realpa */
Chris Metcalffb702b92010-06-25 16:41:11 -0400308#define HV_DISPATCH_INQUIRE_REALPA 54
Chris Metcalf867e3592010-05-28 23:09:12 -0400309
310/** hv_flush_all */
Chris Metcalffb702b92010-06-25 16:41:11 -0400311#define HV_DISPATCH_FLUSH_ALL 55
312
313#if CHIP_HAS_IPI()
314/** hv_get_ipi_pte */
315#define HV_DISPATCH_GET_IPI_PTE 56
316#endif
Chris Metcalf867e3592010-05-28 23:09:12 -0400317
Chris Metcalf621b1952012-04-01 14:04:21 -0400318/** hv_set_pte_super_shift */
319#define HV_DISPATCH_SET_PTE_SUPER_SHIFT 57
320
Chris Metcalfbda0f5b2013-08-06 14:11:21 -0400321/** hv_console_set_ipi */
322#define HV_DISPATCH_CONSOLE_SET_IPI 63
323
Chris Metcalf867e3592010-05-28 23:09:12 -0400324/** One more than the largest dispatch value */
Chris Metcalfbda0f5b2013-08-06 14:11:21 -0400325#define _HV_DISPATCH_END 64
Chris Metcalf867e3592010-05-28 23:09:12 -0400326
327
328#ifndef __ASSEMBLER__
329
330#ifdef __KERNEL__
331#include <asm/types.h>
332typedef u32 __hv32; /**< 32-bit value */
333typedef u64 __hv64; /**< 64-bit value */
334#else
335#include <stdint.h>
336typedef uint32_t __hv32; /**< 32-bit value */
337typedef uint64_t __hv64; /**< 64-bit value */
338#endif
339
340
341/** Hypervisor physical address. */
342typedef __hv64 HV_PhysAddr;
343
344#if CHIP_VA_WIDTH() > 32
345/** Hypervisor virtual address. */
346typedef __hv64 HV_VirtAddr;
347#else
348/** Hypervisor virtual address. */
349typedef __hv32 HV_VirtAddr;
350#endif /* CHIP_VA_WIDTH() > 32 */
351
352/** Hypervisor ASID. */
353typedef unsigned int HV_ASID;
354
355/** Hypervisor tile location for a memory access
356 * ("location overridden target").
357 */
358typedef unsigned int HV_LOTAR;
359
360/** Hypervisor size of a page. */
361typedef unsigned long HV_PageSize;
362
363/** A page table entry.
364 */
365typedef struct
366{
367 __hv64 val; /**< Value of PTE */
368} HV_PTE;
369
370/** Hypervisor error code. */
371typedef int HV_Errno;
372
373#endif /* !__ASSEMBLER__ */
374
375#define HV_OK 0 /**< No error */
376#define HV_EINVAL -801 /**< Invalid argument */
377#define HV_ENODEV -802 /**< No such device */
378#define HV_ENOENT -803 /**< No such file or directory */
379#define HV_EBADF -804 /**< Bad file number */
380#define HV_EFAULT -805 /**< Bad address */
381#define HV_ERECIP -806 /**< Bad recipients */
382#define HV_E2BIG -807 /**< Message too big */
383#define HV_ENOTSUP -808 /**< Service not supported */
384#define HV_EBUSY -809 /**< Device busy */
385#define HV_ENOSYS -810 /**< Invalid syscall */
386#define HV_EPERM -811 /**< No permission */
387#define HV_ENOTREADY -812 /**< Device not ready */
388#define HV_EIO -813 /**< I/O error */
389#define HV_ENOMEM -814 /**< Out of memory */
Chris Metcalf5c770752011-03-01 13:01:49 -0500390#define HV_EAGAIN -815 /**< Try again */
Chris Metcalf867e3592010-05-28 23:09:12 -0400391
392#define HV_ERR_MAX -801 /**< Largest HV error code */
Chris Metcalf5c770752011-03-01 13:01:49 -0500393#define HV_ERR_MIN -815 /**< Smallest HV error code */
Chris Metcalf867e3592010-05-28 23:09:12 -0400394
395#ifndef __ASSEMBLER__
396
397/** Pass HV_VERSION to hv_init to request this version of the interface. */
Chris Metcalfc5399142013-05-02 15:29:04 -0400398typedef enum {
399 HV_VERSION = _HV_VERSION,
400 HV_VERSION_OLD_HV_INIT = _HV_VERSION_OLD_HV_INIT,
401
402} HV_VersionNumber;
Chris Metcalf867e3592010-05-28 23:09:12 -0400403
404/** Initializes the hypervisor.
405 *
406 * @param interface_version_number The version of the hypervisor interface
407 * that this program expects, typically HV_VERSION.
408 * @param chip_num Architecture number of the chip the client was built for.
409 * @param chip_rev_num Revision number of the chip the client was built for.
Chris Metcalfc5399142013-05-02 15:29:04 -0400410 * @param client_pl Privilege level the client is built for
411 * (not required if interface_version_number == HV_VERSION_OLD_HV_INIT).
Chris Metcalf867e3592010-05-28 23:09:12 -0400412 */
413void hv_init(HV_VersionNumber interface_version_number,
Chris Metcalfc5399142013-05-02 15:29:04 -0400414 int chip_num, int chip_rev_num, int client_pl);
Chris Metcalf867e3592010-05-28 23:09:12 -0400415
416
417/** Queries we can make for hv_sysconf().
418 *
419 * These numbers are part of the binary API and guaranteed not to change.
420 */
421typedef enum {
422 /** An invalid value; do not use. */
423 _HV_SYSCONF_RESERVED = 0,
424
425 /** The length of the glue section containing the hv_ procs, in bytes. */
426 HV_SYSCONF_GLUE_SIZE = 1,
427
428 /** The size of small pages, in bytes. */
429 HV_SYSCONF_PAGE_SIZE_SMALL = 2,
430
431 /** The size of large pages, in bytes. */
432 HV_SYSCONF_PAGE_SIZE_LARGE = 3,
433
434 /** Processor clock speed, in hertz. */
435 HV_SYSCONF_CPU_SPEED = 4,
436
437 /** Processor temperature, in degrees Kelvin. The value
438 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
439 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
440 * that the temperature has hit an upper limit and is no longer being
441 * accurately tracked.
442 */
443 HV_SYSCONF_CPU_TEMP = 5,
444
445 /** Board temperature, in degrees Kelvin. The value
446 * HV_SYSCONF_TEMP_KTOC may be subtracted from this to get degrees
447 * Celsius. If that Celsius value is HV_SYSCONF_OVERTEMP, this indicates
448 * that the temperature has hit an upper limit and is no longer being
449 * accurately tracked.
450 */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -0400451 HV_SYSCONF_BOARD_TEMP = 6,
452
453 /** Legal page size bitmask for hv_install_context().
454 * For example, if 16KB and 64KB small pages are supported,
455 * it would return "HV_CTX_PG_SM_16K | HV_CTX_PG_SM_64K".
456 */
457 HV_SYSCONF_VALID_PAGE_SIZES = 7,
Chris Metcalf867e3592010-05-28 23:09:12 -0400458
Chris Metcalf621b1952012-04-01 14:04:21 -0400459 /** The size of jumbo pages, in bytes.
460 * If no jumbo pages are available, zero will be returned.
461 */
462 HV_SYSCONF_PAGE_SIZE_JUMBO = 8,
463
Chris Metcalf867e3592010-05-28 23:09:12 -0400464} HV_SysconfQuery;
465
466/** Offset to subtract from returned Kelvin temperature to get degrees
467 Celsius. */
468#define HV_SYSCONF_TEMP_KTOC 273
469
470/** Pseudo-temperature value indicating that the temperature has
471 * pegged at its upper limit and is no longer accurate; note that this is
472 * the value after subtracting HV_SYSCONF_TEMP_KTOC. */
473#define HV_SYSCONF_OVERTEMP 999
474
475/** Query a configuration value from the hypervisor.
476 * @param query Which value is requested (HV_SYSCONF_xxx).
477 * @return The requested value, or -1 the requested value is illegal or
478 * unavailable.
479 */
480long hv_sysconf(HV_SysconfQuery query);
481
482
483/** Queries we can make for hv_confstr().
484 *
485 * These numbers are part of the binary API and guaranteed not to change.
486 */
487typedef enum {
488 /** An invalid value; do not use. */
489 _HV_CONFSTR_RESERVED = 0,
490
491 /** Board part number. */
492 HV_CONFSTR_BOARD_PART_NUM = 1,
493
494 /** Board serial number. */
495 HV_CONFSTR_BOARD_SERIAL_NUM = 2,
496
497 /** Chip serial number. */
498 HV_CONFSTR_CHIP_SERIAL_NUM = 3,
499
500 /** Board revision level. */
501 HV_CONFSTR_BOARD_REV = 4,
502
503 /** Hypervisor software version. */
504 HV_CONFSTR_HV_SW_VER = 5,
505
506 /** The name for this chip model. */
507 HV_CONFSTR_CHIP_MODEL = 6,
508
509 /** Human-readable board description. */
510 HV_CONFSTR_BOARD_DESC = 7,
511
512 /** Human-readable description of the hypervisor configuration. */
513 HV_CONFSTR_HV_CONFIG = 8,
514
515 /** Human-readable version string for the boot image (for instance,
516 * who built it and when, what configuration file was used). */
517 HV_CONFSTR_HV_CONFIG_VER = 9,
518
519 /** Mezzanine part number. */
520 HV_CONFSTR_MEZZ_PART_NUM = 10,
521
522 /** Mezzanine serial number. */
523 HV_CONFSTR_MEZZ_SERIAL_NUM = 11,
524
525 /** Mezzanine revision level. */
526 HV_CONFSTR_MEZZ_REV = 12,
527
528 /** Human-readable mezzanine description. */
529 HV_CONFSTR_MEZZ_DESC = 13,
530
531 /** Control path for the onboard network switch. */
532 HV_CONFSTR_SWITCH_CONTROL = 14,
533
534 /** Chip revision level. */
Chris Metcalf8703d6e2012-03-30 16:21:17 -0400535 HV_CONFSTR_CHIP_REV = 15,
536
537 /** CPU module part number. */
538 HV_CONFSTR_CPUMOD_PART_NUM = 16,
539
540 /** CPU module serial number. */
541 HV_CONFSTR_CPUMOD_SERIAL_NUM = 17,
542
543 /** CPU module revision level. */
544 HV_CONFSTR_CPUMOD_REV = 18,
545
546 /** Human-readable CPU module description. */
Chris Metcalf80f18412013-08-12 14:39:22 -0400547 HV_CONFSTR_CPUMOD_DESC = 19,
548
549 /** Per-tile hypervisor statistics. When this identifier is specified,
550 * the hv_confstr call takes two extra arguments. The first is the
551 * HV_XY_TO_LOTAR of the target tile's coordinates. The second is
552 * a flag word. The only current flag is the lowest bit, which means
553 * "zero out the stats instead of retrieving them"; in this case the
554 * buffer and buffer length are ignored. */
555 HV_CONFSTR_HV_STATS = 20
Chris Metcalf867e3592010-05-28 23:09:12 -0400556
557} HV_ConfstrQuery;
558
559/** Query a configuration string from the hypervisor.
560 *
561 * @param query Identifier for the specific string to be retrieved
Chris Metcalf80f18412013-08-12 14:39:22 -0400562 * (HV_CONFSTR_xxx). Some strings may require or permit extra
563 * arguments to be appended which select specific objects to be
564 * described; see the string descriptions above.
Chris Metcalf867e3592010-05-28 23:09:12 -0400565 * @param buf Buffer in which to place the string.
566 * @param len Length of the buffer.
567 * @return If query is valid, then the length of the corresponding string,
568 * including the trailing null; if this is greater than len, the string
569 * was truncated. If query is invalid, HV_EINVAL. If the specified
570 * buffer is not writable by the client, HV_EFAULT.
571 */
Chris Metcalf80f18412013-08-12 14:39:22 -0400572int hv_confstr(HV_ConfstrQuery query, HV_VirtAddr buf, int len, ...);
Chris Metcalf867e3592010-05-28 23:09:12 -0400573
Chris Metcalf867e3592010-05-28 23:09:12 -0400574/** Tile coordinate */
575typedef struct
576{
577 /** X coordinate, relative to supervisor's top-left coordinate */
578 int x;
579
580 /** Y coordinate, relative to supervisor's top-left coordinate */
581 int y;
582} HV_Coord;
583
Chris Metcalffb702b92010-06-25 16:41:11 -0400584
585#if CHIP_HAS_IPI()
586
587/** Get the PTE for sending an IPI to a particular tile.
588 *
589 * @param tile Tile which will receive the IPI.
590 * @param pl Indicates which IPI registers: 0 = IPI_0, 1 = IPI_1.
591 * @param pte Filled with resulting PTE.
592 * @result Zero if no error, non-zero for invalid parameters.
593 */
594int hv_get_ipi_pte(HV_Coord tile, int pl, HV_PTE* pte);
595
Chris Metcalfbda0f5b2013-08-06 14:11:21 -0400596/** Configure the console interrupt.
597 *
598 * When the console client interrupt is enabled, the hypervisor will
599 * deliver the specified IPI to the client in the following situations:
600 *
601 * - The console has at least one character available for input.
602 *
603 * - The console can accept new characters for output, and the last call
604 * to hv_console_write() did not write all of the characters requested
605 * by the client.
606 *
607 * Note that in some system configurations, console interrupt will not
608 * be available; clients should be prepared for this routine to fail and
609 * to fall back to periodic console polling in that case.
610 *
611 * @param ipi Index of the IPI register which will receive the interrupt.
612 * @param event IPI event number for console interrupt. If less than 0,
613 * disable the console IPI interrupt.
614 * @param coord Tile to be targeted for console interrupt.
615 * @return 0 on success, otherwise, HV_EINVAL if illegal parameter,
616 * HV_ENOTSUP if console interrupt are not available.
617 */
618int hv_console_set_ipi(int ipi, int event, HV_Coord coord);
619
Chris Metcalffb702b92010-06-25 16:41:11 -0400620#else /* !CHIP_HAS_IPI() */
621
622/** A set of interrupts. */
623typedef __hv32 HV_IntrMask;
624
Chris Metcalf867e3592010-05-28 23:09:12 -0400625/** The low interrupt numbers are reserved for use by the client in
626 * delivering IPIs. Any interrupt numbers higher than this value are
627 * reserved for use by HV device drivers. */
628#define HV_MAX_IPI_INTERRUPT 7
629
Chris Metcalffb702b92010-06-25 16:41:11 -0400630/** Enable a set of device interrupts.
Chris Metcalf867e3592010-05-28 23:09:12 -0400631 *
Chris Metcalf867e3592010-05-28 23:09:12 -0400632 * @param enab_mask Bitmap of interrupts to enable.
633 */
Chris Metcalffb702b92010-06-25 16:41:11 -0400634void hv_enable_intr(HV_IntrMask enab_mask);
Chris Metcalf867e3592010-05-28 23:09:12 -0400635
Chris Metcalffb702b92010-06-25 16:41:11 -0400636/** Disable a set of device interrupts.
Chris Metcalf867e3592010-05-28 23:09:12 -0400637 *
Chris Metcalf867e3592010-05-28 23:09:12 -0400638 * @param disab_mask Bitmap of interrupts to disable.
639 */
Chris Metcalffb702b92010-06-25 16:41:11 -0400640void hv_disable_intr(HV_IntrMask disab_mask);
641
642/** Clear a set of device interrupts.
643 *
644 * @param clear_mask Bitmap of interrupts to clear.
645 */
646void hv_clear_intr(HV_IntrMask clear_mask);
647
Chris Metcalfc745a8a2010-08-13 08:52:19 -0400648/** Raise a set of device interrupts.
Chris Metcalffb702b92010-06-25 16:41:11 -0400649 *
Chris Metcalfc745a8a2010-08-13 08:52:19 -0400650 * @param raise_mask Bitmap of interrupts to raise.
Chris Metcalffb702b92010-06-25 16:41:11 -0400651 */
Chris Metcalfc745a8a2010-08-13 08:52:19 -0400652void hv_raise_intr(HV_IntrMask raise_mask);
Chris Metcalf867e3592010-05-28 23:09:12 -0400653
654/** Trigger a one-shot interrupt on some tile
655 *
656 * @param tile Which tile to interrupt.
657 * @param interrupt Interrupt number to trigger; must be between 0 and
658 * HV_MAX_IPI_INTERRUPT.
659 * @return HV_OK on success, or a hypervisor error code.
660 */
661HV_Errno hv_trigger_ipi(HV_Coord tile, int interrupt);
662
Chris Metcalfef06f552010-07-02 14:19:35 -0400663#endif /* !CHIP_HAS_IPI() */
Chris Metcalffb702b92010-06-25 16:41:11 -0400664
Chris Metcalf867e3592010-05-28 23:09:12 -0400665/** Store memory mapping in debug memory so that external debugger can read it.
666 * A maximum of 16 entries can be stored.
667 *
668 * @param va VA of memory that is mapped.
669 * @param len Length of mapped memory.
670 * @param pa PA of memory that is mapped.
671 * @return 0 on success, -1 if the maximum number of mappings is exceeded.
672 */
673int hv_store_mapping(HV_VirtAddr va, unsigned int len, HV_PhysAddr pa);
674
675/** Given a client PA and a length, return its real (HV) PA.
676 *
677 * @param cpa Client physical address.
678 * @param len Length of mapped memory.
679 * @return physical address, or -1 if cpa or len is not valid.
680 */
681HV_PhysAddr hv_inquire_realpa(HV_PhysAddr cpa, unsigned int len);
682
683/** RTC return flag for no RTC chip present.
684 */
685#define HV_RTC_NO_CHIP 0x1
686
687/** RTC return flag for low-voltage condition, indicating that battery had
688 * died and time read is unreliable.
689 */
690#define HV_RTC_LOW_VOLTAGE 0x2
691
692/** Date/Time of day */
693typedef struct {
694#if CHIP_WORD_SIZE() > 32
695 __hv64 tm_sec; /**< Seconds, 0-59 */
696 __hv64 tm_min; /**< Minutes, 0-59 */
697 __hv64 tm_hour; /**< Hours, 0-23 */
698 __hv64 tm_mday; /**< Day of month, 0-30 */
699 __hv64 tm_mon; /**< Month, 0-11 */
700 __hv64 tm_year; /**< Years since 1900, 0-199 */
701 __hv64 flags; /**< Return flags, 0 if no error */
702#else
703 __hv32 tm_sec; /**< Seconds, 0-59 */
704 __hv32 tm_min; /**< Minutes, 0-59 */
705 __hv32 tm_hour; /**< Hours, 0-23 */
706 __hv32 tm_mday; /**< Day of month, 0-30 */
707 __hv32 tm_mon; /**< Month, 0-11 */
708 __hv32 tm_year; /**< Years since 1900, 0-199 */
709 __hv32 flags; /**< Return flags, 0 if no error */
710#endif
711} HV_RTCTime;
712
713/** Read the current time-of-day clock.
714 * @return HV_RTCTime of current time (GMT).
715 */
716HV_RTCTime hv_get_rtc(void);
717
718
719/** Set the current time-of-day clock.
720 * @param time time to reset time-of-day to (GMT).
721 */
722void hv_set_rtc(HV_RTCTime time);
723
724/** Installs a context, comprising a page table and other attributes.
725 *
726 * Once this service completes, page_table will be used to translate
727 * subsequent virtual address references to physical memory.
728 *
729 * Installing a context does not cause an implicit TLB flush. Before
730 * reusing an ASID value for a different address space, the client is
731 * expected to flush old references from the TLB with hv_flush_asid().
732 * (Alternately, hv_flush_all() may be used to flush many ASIDs at once.)
733 * After invalidating a page table entry, changing its attributes, or
734 * changing its target CPA, the client is expected to flush old references
735 * from the TLB with hv_flush_page() or hv_flush_pages(). Making a
736 * previously invalid page valid does not require a flush.
737 *
738 * Specifying an invalid ASID, or an invalid CPA (client physical address)
739 * (either as page_table_pointer, or within the referenced table),
740 * or another page table data item documented as above as illegal may
741 * lead to client termination; since the validation of the table is
742 * done as needed, this may happen before the service returns, or at
743 * some later time, or never, depending upon the client's pattern of
744 * memory references. Page table entries which supply translations for
745 * invalid virtual addresses may result in client termination, or may
746 * be silently ignored. "Invalid" in this context means a value which
747 * was not provided to the client via the appropriate hv_inquire_* routine.
748 *
749 * To support changing the instruction VAs at the same time as
750 * installing the new page table, this call explicitly supports
751 * setting the "lr" register to a different address and then jumping
752 * directly to the hv_install_context() routine. In this case, the
753 * new page table does not need to contain any mapping for the
754 * hv_install_context address itself.
755 *
Chris Metcalfd5d14ed2012-03-29 13:58:43 -0400756 * At most one HV_CTX_PG_SM_* flag may be specified in "flags";
757 * if multiple flags are specified, HV_EINVAL is returned.
758 * Specifying none of the flags results in using the default page size.
759 * All cores participating in a given client must request the same
760 * page size, or the results are undefined.
761 *
Chris Metcalf867e3592010-05-28 23:09:12 -0400762 * @param page_table Root of the page table.
763 * @param access PTE providing info on how to read the page table. This
764 * value must be consistent between multiple tiles sharing a page table,
765 * and must also be consistent with any virtual mappings the client
766 * may be using to access the page table.
767 * @param asid HV_ASID the page table is to be used for.
768 * @param flags Context flags, denoting attributes or privileges of the
769 * current context (HV_CTX_xxx).
770 * @return Zero on success, or a hypervisor error code on failure.
771 */
772int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid,
773 __hv32 flags);
774
775#endif /* !__ASSEMBLER__ */
776
777#define HV_CTX_DIRECTIO 0x1 /**< Direct I/O requests are accepted from
778 PL0. */
779
Chris Metcalfd5d14ed2012-03-29 13:58:43 -0400780#define HV_CTX_PG_SM_4K 0x10 /**< Use 4K small pages, if available. */
781#define HV_CTX_PG_SM_16K 0x20 /**< Use 16K small pages, if available. */
782#define HV_CTX_PG_SM_64K 0x40 /**< Use 64K small pages, if available. */
783#define HV_CTX_PG_SM_MASK 0xf0 /**< Mask of all possible small pages. */
784
Chris Metcalf867e3592010-05-28 23:09:12 -0400785#ifndef __ASSEMBLER__
786
Chris Metcalf621b1952012-04-01 14:04:21 -0400787
788/** Set the number of pages ganged together by HV_PTE_SUPER at a
789 * particular level of the page table.
790 *
791 * The current TILE-Gx hardware only supports powers of four
792 * (i.e. log2_count must be a multiple of two), and the requested
793 * "super" page size must be less than the span of the next level in
794 * the page table. The largest size that can be requested is 64GB.
795 *
796 * The shift value is initially "0" for all page table levels,
797 * indicating that the HV_PTE_SUPER bit is effectively ignored.
798 *
799 * If you change the count from one non-zero value to another, the
800 * hypervisor will flush the entire TLB and TSB to avoid confusion.
801 *
802 * @param level Page table level (0, 1, or 2)
803 * @param log2_count Base-2 log of the number of pages to gang together,
804 * i.e. how much to shift left the base page size for the super page size.
805 * @return Zero on success, or a hypervisor error code on failure.
806 */
807int hv_set_pte_super_shift(int level, int log2_count);
808
809
Chris Metcalf867e3592010-05-28 23:09:12 -0400810/** Value returned from hv_inquire_context(). */
811typedef struct
812{
813 /** Physical address of page table */
814 HV_PhysAddr page_table;
815
816 /** PTE which defines access method for top of page table */
817 HV_PTE access;
818
819 /** ASID associated with this page table */
820 HV_ASID asid;
821
822 /** Context flags */
823 __hv32 flags;
824} HV_Context;
825
826/** Retrieve information about the currently installed context.
827 * @return The data passed to the last successful hv_install_context call.
828 */
829HV_Context hv_inquire_context(void);
830
831
832/** Flushes all translations associated with the named address space
833 * identifier from the TLB and any other hypervisor data structures.
834 * Translations installed with the "global" bit are not flushed.
835 *
836 * Specifying an invalid ASID may lead to client termination. "Invalid"
837 * in this context means a value which was not provided to the client
838 * via <tt>hv_inquire_asid()</tt>.
839 *
840 * @param asid HV_ASID whose entries are to be flushed.
841 * @return Zero on success, or a hypervisor error code on failure.
842*/
843int hv_flush_asid(HV_ASID asid);
844
845
846/** Flushes all translations associated with the named virtual address
847 * and page size from the TLB and other hypervisor data structures. Only
848 * pages visible to the current ASID are affected; note that this includes
849 * global pages in addition to pages specific to the current ASID.
850 *
851 * The supplied VA need not be aligned; it may be anywhere in the
852 * subject page.
853 *
854 * Specifying an invalid virtual address may lead to client termination,
855 * or may silently succeed. "Invalid" in this context means a value
856 * which was not provided to the client via hv_inquire_virtual.
857 *
858 * @param address Address of the page to flush.
859 * @param page_size Size of pages to assume.
860 * @return Zero on success, or a hypervisor error code on failure.
861 */
862int hv_flush_page(HV_VirtAddr address, HV_PageSize page_size);
863
864
865/** Flushes all translations associated with the named virtual address range
866 * and page size from the TLB and other hypervisor data structures. Only
867 * pages visible to the current ASID are affected; note that this includes
868 * global pages in addition to pages specific to the current ASID.
869 *
870 * The supplied VA need not be aligned; it may be anywhere in the
871 * subject page.
872 *
873 * Specifying an invalid virtual address may lead to client termination,
874 * or may silently succeed. "Invalid" in this context means a value
875 * which was not provided to the client via hv_inquire_virtual.
876 *
877 * @param start Address to flush.
878 * @param page_size Size of pages to assume.
879 * @param size The number of bytes to flush. Any page in the range
880 * [start, start + size) will be flushed from the TLB.
881 * @return Zero on success, or a hypervisor error code on failure.
882 */
883int hv_flush_pages(HV_VirtAddr start, HV_PageSize page_size,
884 unsigned long size);
885
886
887/** Flushes all non-global translations (if preserve_global is true),
888 * or absolutely all translations (if preserve_global is false).
889 *
890 * @param preserve_global Non-zero if we want to preserve "global" mappings.
891 * @return Zero on success, or a hypervisor error code on failure.
892*/
893int hv_flush_all(int preserve_global);
894
895
896/** Restart machine with optional restart command and optional args.
897 * @param cmd Const pointer to command to restart with, or NULL
898 * @param args Const pointer to argument string to restart with, or NULL
899 */
900void hv_restart(HV_VirtAddr cmd, HV_VirtAddr args);
901
902
903/** Halt machine. */
904void hv_halt(void);
905
906
907/** Power off machine. */
908void hv_power_off(void);
909
910
911/** Re-enter virtual-is-physical memory translation mode and restart
912 * execution at a given address.
913 * @param entry Client physical address at which to begin execution.
914 * @return A hypervisor error code on failure; if the operation is
915 * successful the call does not return.
916 */
917int hv_reexec(HV_PhysAddr entry);
918
919
920/** Chip topology */
921typedef struct
922{
923 /** Relative coordinates of the querying tile */
924 HV_Coord coord;
925
926 /** Width of the querying supervisor's tile rectangle. */
927 int width;
928
929 /** Height of the querying supervisor's tile rectangle. */
930 int height;
931
932} HV_Topology;
933
934/** Returns information about the tile coordinate system.
935 *
936 * Each supervisor is given a rectangle of tiles it potentially controls.
937 * These tiles are labeled using a relative coordinate system with (0,0) as
938 * the upper left tile regardless of their physical location on the chip.
939 *
940 * This call returns both the size of that rectangle and the position
941 * within that rectangle of the querying tile.
942 *
943 * Not all tiles within that rectangle may be available to the supervisor;
944 * to get the precise set of available tiles, you must also call
945 * hv_inquire_tiles(HV_INQ_TILES_AVAIL, ...).
946 **/
947HV_Topology hv_inquire_topology(void);
948
949/** Sets of tiles we can retrieve with hv_inquire_tiles().
950 *
951 * These numbers are part of the binary API and guaranteed not to change.
952 */
953typedef enum {
954 /** An invalid value; do not use. */
955 _HV_INQ_TILES_RESERVED = 0,
956
957 /** All available tiles within the supervisor's tile rectangle. */
958 HV_INQ_TILES_AVAIL = 1,
959
960 /** The set of tiles used for hash-for-home caching. */
961 HV_INQ_TILES_HFH_CACHE = 2,
962
963 /** The set of tiles that can be legally used as a LOTAR for a PTE. */
Chris Metcalf128f3cb2015-03-30 16:33:00 -0400964 HV_INQ_TILES_LOTAR = 3,
965
966 /** The set of "shared" driver tiles that the hypervisor may
967 * periodically interrupt. */
968 HV_INQ_TILES_SHARED = 4
Chris Metcalf867e3592010-05-28 23:09:12 -0400969} HV_InqTileSet;
970
971/** Returns specific information about various sets of tiles within the
972 * supervisor's tile rectangle.
973 *
974 * @param set Which set of tiles to retrieve.
975 * @param cpumask Pointer to a returned bitmask (in row-major order,
976 * supervisor-relative) of tiles. The low bit of the first word
977 * corresponds to the tile at the upper left-hand corner of the
978 * supervisor's rectangle. In order for the supervisor to know the
979 * buffer length to supply, it should first call hv_inquire_topology.
980 * @param length Number of bytes available for the returned bitmask.
981 **/
982HV_Errno hv_inquire_tiles(HV_InqTileSet set, HV_VirtAddr cpumask, int length);
983
984
985/** An identifier for a memory controller. Multiple memory controllers
986 * may be connected to one chip, and this uniquely identifies each one.
987 */
988typedef int HV_MemoryController;
989
990/** A range of physical memory. */
991typedef struct
992{
993 HV_PhysAddr start; /**< Starting address. */
994 __hv64 size; /**< Size in bytes. */
995 HV_MemoryController controller; /**< Which memory controller owns this. */
996} HV_PhysAddrRange;
997
998/** Returns information about a range of physical memory.
999 *
1000 * hv_inquire_physical() returns one of the ranges of client
1001 * physical addresses which are available to this client.
1002 *
1003 * The first range is retrieved by specifying an idx of 0, and
1004 * successive ranges are returned with subsequent idx values. Ranges
1005 * are ordered by increasing start address (i.e., as idx increases,
1006 * so does start), do not overlap, and do not touch (i.e., the
1007 * available memory is described with the fewest possible ranges).
1008 *
1009 * If an out-of-range idx value is specified, the returned size will be zero.
1010 * A client can count the number of ranges by increasing idx until the
1011 * returned size is zero. There will always be at least one valid range.
1012 *
1013 * Some clients might not be prepared to deal with more than one
1014 * physical address range; they still ought to call this routine and
1015 * issue a warning message if they're given more than one range, on the
1016 * theory that whoever configured the hypervisor to provide that memory
1017 * should know that it's being wasted.
1018 */
1019HV_PhysAddrRange hv_inquire_physical(int idx);
1020
Chris Metcalf5c770752011-03-01 13:01:49 -05001021/** Possible DIMM types. */
1022typedef enum
1023{
1024 NO_DIMM = 0, /**< No DIMM */
1025 DDR2 = 1, /**< DDR2 */
1026 DDR3 = 2 /**< DDR3 */
1027} HV_DIMM_Type;
1028
1029#ifdef __tilegx__
1030
1031/** Log2 of minimum DIMM bytes supported by the memory controller. */
1032#define HV_MSH_MIN_DIMM_SIZE_SHIFT 29
1033
1034/** Max number of DIMMs contained by one memory controller. */
1035#define HV_MSH_MAX_DIMMS 8
1036
1037#else
1038
1039/** Log2 of minimum DIMM bytes supported by the memory controller. */
1040#define HV_MSH_MIN_DIMM_SIZE_SHIFT 26
1041
1042/** Max number of DIMMs contained by one memory controller. */
1043#define HV_MSH_MAX_DIMMS 2
1044
1045#endif
1046
1047/** Number of bits to right-shift to get the DIMM type. */
1048#define HV_DIMM_TYPE_SHIFT 0
1049
1050/** Bits to mask to get the DIMM type. */
1051#define HV_DIMM_TYPE_MASK 0xf
1052
1053/** Number of bits to right-shift to get the DIMM size. */
1054#define HV_DIMM_SIZE_SHIFT 4
1055
1056/** Bits to mask to get the DIMM size. */
1057#define HV_DIMM_SIZE_MASK 0xf
Chris Metcalf867e3592010-05-28 23:09:12 -04001058
1059/** Memory controller information. */
1060typedef struct
1061{
1062 HV_Coord coord; /**< Relative tile coordinates of the port used by a
1063 specified tile to communicate with this controller. */
1064 __hv64 speed; /**< Speed of this controller in bytes per second. */
1065} HV_MemoryControllerInfo;
1066
1067/** Returns information about a particular memory controller.
1068 *
1069 * hv_inquire_memory_controller(coord,idx) returns information about a
1070 * particular controller. Two pieces of information are returned:
1071 * - The relative coordinates of the port on the controller that the specified
1072 * tile would use to contact it. The relative coordinates may lie
1073 * outside the supervisor's rectangle, i.e. the controller may not
1074 * be attached to a node managed by the querying node's supervisor.
1075 * In particular note that x or y may be negative.
1076 * - The speed of the memory controller. (This is a not-to-exceed value
1077 * based on the raw hardware data rate, and may not be achievable in
1078 * practice; it is provided to give clients information on the relative
1079 * performance of the available controllers.)
1080 *
1081 * Clients should avoid calling this interface with invalid values.
1082 * A client who does may be terminated.
1083 * @param coord Tile for which to calculate the relative port position.
1084 * @param controller Index of the controller; identical to value returned
1085 * from other routines like hv_inquire_physical.
1086 * @return Information about the controller.
1087 */
1088HV_MemoryControllerInfo hv_inquire_memory_controller(HV_Coord coord,
1089 int controller);
1090
1091
1092/** A range of virtual memory. */
1093typedef struct
1094{
1095 HV_VirtAddr start; /**< Starting address. */
1096 __hv64 size; /**< Size in bytes. */
1097} HV_VirtAddrRange;
1098
1099/** Returns information about a range of virtual memory.
1100 *
1101 * hv_inquire_virtual() returns one of the ranges of client
1102 * virtual addresses which are available to this client.
1103 *
1104 * The first range is retrieved by specifying an idx of 0, and
1105 * successive ranges are returned with subsequent idx values. Ranges
1106 * are ordered by increasing start address (i.e., as idx increases,
1107 * so does start), do not overlap, and do not touch (i.e., the
1108 * available memory is described with the fewest possible ranges).
1109 *
1110 * If an out-of-range idx value is specified, the returned size will be zero.
1111 * A client can count the number of ranges by increasing idx until the
1112 * returned size is zero. There will always be at least one valid range.
1113 *
1114 * Some clients may well have various virtual addresses hardwired
1115 * into themselves; for instance, their instruction stream may
1116 * have been compiled expecting to live at a particular address.
1117 * Such clients should use this interface to verify they've been
1118 * given the virtual address space they expect, and issue a (potentially
1119 * fatal) warning message otherwise.
1120 *
1121 * Note that the returned size is a __hv64, not a __hv32, so it is
1122 * possible to express a single range spanning the entire 32-bit
1123 * address space.
1124 */
1125HV_VirtAddrRange hv_inquire_virtual(int idx);
1126
1127
1128/** A range of ASID values. */
1129typedef struct
1130{
1131 HV_ASID start; /**< First ASID in the range. */
1132 unsigned int size; /**< Number of ASIDs. Zero for an invalid range. */
1133} HV_ASIDRange;
1134
1135/** Returns information about a range of ASIDs.
1136 *
1137 * hv_inquire_asid() returns one of the ranges of address
1138 * space identifiers which are available to this client.
1139 *
1140 * The first range is retrieved by specifying an idx of 0, and
1141 * successive ranges are returned with subsequent idx values. Ranges
1142 * are ordered by increasing start value (i.e., as idx increases,
1143 * so does start), do not overlap, and do not touch (i.e., the
1144 * available ASIDs are described with the fewest possible ranges).
1145 *
1146 * If an out-of-range idx value is specified, the returned size will be zero.
1147 * A client can count the number of ranges by increasing idx until the
1148 * returned size is zero. There will always be at least one valid range.
1149 */
1150HV_ASIDRange hv_inquire_asid(int idx);
1151
1152
1153/** Waits for at least the specified number of nanoseconds then returns.
1154 *
Chris Metcalf13371732011-02-28 13:21:52 -05001155 * NOTE: this deprecated function currently assumes a 750 MHz clock,
1156 * and is thus not generally suitable for use. New code should call
1157 * hv_sysconf(HV_SYSCONF_CPU_SPEED), compute a cycle count to wait for,
1158 * and delay by looping while checking the cycle counter SPR.
1159 *
Chris Metcalf867e3592010-05-28 23:09:12 -04001160 * @param nanosecs The number of nanoseconds to sleep.
1161 */
1162void hv_nanosleep(int nanosecs);
1163
1164
1165/** Reads a character from the console without blocking.
1166 *
1167 * @return A value from 0-255 indicates the value successfully read.
1168 * A negative value means no value was ready.
1169 */
1170int hv_console_read_if_ready(void);
1171
1172
1173/** Writes a character to the console, blocking if the console is busy.
1174 *
1175 * This call cannot fail. If the console is broken for some reason,
1176 * output will simply vanish.
1177 * @param byte Character to write.
1178 */
1179void hv_console_putc(int byte);
1180
1181
1182/** Writes a string to the console, blocking if the console is busy.
1183 * @param bytes Pointer to characters to write.
1184 * @param len Number of characters to write.
1185 * @return Number of characters written, or HV_EFAULT if the buffer is invalid.
1186 */
1187int hv_console_write(HV_VirtAddr bytes, int len);
1188
1189
1190/** Dispatch the next interrupt from the client downcall mechanism.
1191 *
1192 * The hypervisor uses downcalls to notify the client of asynchronous
1193 * events. Some of these events are hypervisor-created (like incoming
1194 * messages). Some are regular interrupts which initially occur in
1195 * the hypervisor, and are normally handled directly by the client;
1196 * when these occur in a client's interrupt critical section, they must
1197 * be delivered through the downcall mechanism.
1198 *
Chris Metcalfa78c9422010-10-14 16:23:03 -04001199 * A downcall is initially delivered to the client as an INTCTRL_CL
1200 * interrupt, where CL is the client's PL. Upon entry to the INTCTRL_CL
1201 * vector, the client must immediately invoke the hv_downcall_dispatch
1202 * service. This service will not return; instead it will cause one of
1203 * the client's actual downcall-handling interrupt vectors to be entered.
1204 * The EX_CONTEXT registers in the client will be set so that when the
1205 * client irets, it will return to the code which was interrupted by the
1206 * INTCTRL_CL interrupt.
Chris Metcalf867e3592010-05-28 23:09:12 -04001207 *
Chris Metcalfa78c9422010-10-14 16:23:03 -04001208 * Under some circumstances, the firing of INTCTRL_CL can race with
Chris Metcalffb702b92010-06-25 16:41:11 -04001209 * the lowering of a device interrupt. In such a case, the
1210 * hv_downcall_dispatch service may issue an iret instruction instead
1211 * of entering one of the client's actual downcall-handling interrupt
1212 * vectors. This will return execution to the location that was
Chris Metcalfa78c9422010-10-14 16:23:03 -04001213 * interrupted by INTCTRL_CL.
Chris Metcalffb702b92010-06-25 16:41:11 -04001214 *
Chris Metcalf867e3592010-05-28 23:09:12 -04001215 * Any saving of registers should be done by the actual handling
Chris Metcalfa78c9422010-10-14 16:23:03 -04001216 * vectors; no registers should be changed by the INTCTRL_CL handler.
Chris Metcalf867e3592010-05-28 23:09:12 -04001217 * In particular, the client should not use a jal instruction to invoke
1218 * the hv_downcall_dispatch service, as that would overwrite the client's
1219 * lr register. Note that the hv_downcall_dispatch service may overwrite
1220 * one or more of the client's system save registers.
1221 *
Chris Metcalfa78c9422010-10-14 16:23:03 -04001222 * The client must not modify the INTCTRL_CL_STATUS SPR. The hypervisor
Chris Metcalf867e3592010-05-28 23:09:12 -04001223 * will set this register to cause a downcall to happen, and will clear
1224 * it when no further downcalls are pending.
1225 *
Chris Metcalfa78c9422010-10-14 16:23:03 -04001226 * When a downcall vector is entered, the INTCTRL_CL interrupt will be
Chris Metcalf867e3592010-05-28 23:09:12 -04001227 * masked. When the client is done processing a downcall, and is ready
1228 * to accept another, it must unmask this interrupt; if more downcalls
Chris Metcalfa78c9422010-10-14 16:23:03 -04001229 * are pending, this will cause the INTCTRL_CL vector to be reentered.
Chris Metcalf867e3592010-05-28 23:09:12 -04001230 * Currently the following interrupt vectors can be entered through a
1231 * downcall:
1232 *
1233 * INT_MESSAGE_RCV_DWNCL (hypervisor message available)
Chris Metcalf5c770752011-03-01 13:01:49 -05001234 * INT_DEV_INTR_DWNCL (device interrupt)
Chris Metcalf867e3592010-05-28 23:09:12 -04001235 * INT_DMATLB_MISS_DWNCL (DMA TLB miss)
1236 * INT_SNITLB_MISS_DWNCL (SNI TLB miss)
1237 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
1238 */
1239void hv_downcall_dispatch(void);
1240
1241#endif /* !__ASSEMBLER__ */
1242
1243/** We use actual interrupt vectors which never occur (they're only there
1244 * to allow setting MPLs for related SPRs) for our downcall vectors.
1245 */
1246/** Message receive downcall interrupt vector */
1247#define INT_MESSAGE_RCV_DWNCL INT_BOOT_ACCESS
1248/** DMA TLB miss downcall interrupt vector */
1249#define INT_DMATLB_MISS_DWNCL INT_DMA_ASID
1250/** Static nework processor instruction TLB miss interrupt vector */
1251#define INT_SNITLB_MISS_DWNCL INT_SNI_ASID
1252/** DMA TLB access violation downcall interrupt vector */
1253#define INT_DMATLB_ACCESS_DWNCL INT_DMA_CPL
1254/** Device interrupt downcall interrupt vector */
1255#define INT_DEV_INTR_DWNCL INT_WORLD_ACCESS
1256
1257#ifndef __ASSEMBLER__
1258
1259/** Requests the inode for a specific full pathname.
1260 *
1261 * Performs a lookup in the hypervisor filesystem for a given filename.
1262 * Multiple calls with the same filename will always return the same inode.
1263 * If there is no such filename, HV_ENOENT is returned.
1264 * A bad filename pointer may result in HV_EFAULT instead.
1265 *
1266 * @param filename Constant pointer to name of requested file
1267 * @return Inode of requested file
1268 */
1269int hv_fs_findfile(HV_VirtAddr filename);
1270
1271
1272/** Data returned from an fstat request.
1273 * Note that this structure should be no more than 40 bytes in size so
1274 * that it can always be returned completely in registers.
1275 */
1276typedef struct
1277{
1278 int size; /**< Size of file (or HV_Errno on error) */
1279 unsigned int flags; /**< Flags (see HV_FS_FSTAT_FLAGS) */
1280} HV_FS_StatInfo;
1281
1282/** Bitmask flags for fstat request */
1283typedef enum
1284{
1285 HV_FS_ISDIR = 0x0001 /**< Is the entry a directory? */
1286} HV_FS_FSTAT_FLAGS;
1287
1288/** Get stat information on a given file inode.
1289 *
1290 * Return information on the file with the given inode.
1291 *
1292 * IF the HV_FS_ISDIR bit is set, the "file" is a directory. Reading
1293 * it will return NUL-separated filenames (no directory part) relative
1294 * to the path to the inode of the directory "file". These can be
1295 * appended to the path to the directory "file" after a forward slash
1296 * to create additional filenames. Note that it is not required
1297 * that all valid paths be decomposable into valid parent directories;
1298 * a filesystem may validly have just a few files, none of which have
1299 * HV_FS_ISDIR set. However, if clients may wish to enumerate the
1300 * files in the filesystem, it is recommended to include all the
1301 * appropriate parent directory "files" to give a consistent view.
1302 *
1303 * An invalid file inode will cause an HV_EBADF error to be returned.
1304 *
1305 * @param inode The inode number of the query
1306 * @return An HV_FS_StatInfo structure
1307 */
1308HV_FS_StatInfo hv_fs_fstat(int inode);
1309
1310
1311/** Read data from a specific hypervisor file.
1312 * On error, may return HV_EBADF for a bad inode or HV_EFAULT for a bad buf.
1313 * Reads near the end of the file will return fewer bytes than requested.
1314 * Reads at or beyond the end of a file will return zero.
1315 *
1316 * @param inode the hypervisor file to read
1317 * @param buf the buffer to read data into
1318 * @param length the number of bytes of data to read
1319 * @param offset the offset into the file to read the data from
1320 * @return number of bytes successfully read, or an HV_Errno code
1321 */
1322int hv_fs_pread(int inode, HV_VirtAddr buf, int length, int offset);
1323
1324
1325/** Read a 64-bit word from the specified physical address.
1326 * The address must be 8-byte aligned.
1327 * Specifying an invalid physical address will lead to client termination.
1328 * @param addr The physical address to read
1329 * @param access The PTE describing how to read the memory
1330 * @return The 64-bit value read from the given address
1331 */
1332unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access);
1333
1334
1335/** Write a 64-bit word to the specified physical address.
1336 * The address must be 8-byte aligned.
1337 * Specifying an invalid physical address will lead to client termination.
1338 * @param addr The physical address to write
1339 * @param access The PTE that says how to write the memory
1340 * @param val The 64-bit value to write to the given address
1341 */
1342void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access,
1343 unsigned long long val);
1344
1345
1346/** Get the value of the command-line for the supervisor, if any.
1347 * This will not include the filename of the booted supervisor, but may
1348 * include configured-in boot arguments or the hv_restart() arguments.
1349 * If the buffer is not long enough the hypervisor will NUL the first
1350 * character of the buffer but not write any other data.
1351 * @param buf The virtual address to write the command-line string to.
1352 * @param length The length of buf, in characters.
1353 * @return The actual length of the command line, including the trailing NUL
1354 * (may be larger than "length").
1355 */
1356int hv_get_command_line(HV_VirtAddr buf, int length);
1357
1358
1359/** Set a new value for the command-line for the supervisor, which will
1360 * be returned from subsequent invocations of hv_get_command_line() on
1361 * this tile.
1362 * @param buf The virtual address to read the command-line string from.
1363 * @param length The length of buf, in characters; must be no more than
1364 * HV_COMMAND_LINE_LEN.
1365 * @return Zero if successful, or a hypervisor error code.
1366 */
1367HV_Errno hv_set_command_line(HV_VirtAddr buf, int length);
1368
1369/** Maximum size of a command line passed to hv_set_command_line(); note
1370 * that a line returned from hv_get_command_line() could be larger than
1371 * this.*/
1372#define HV_COMMAND_LINE_LEN 256
1373
1374/** Tell the hypervisor how to cache non-priority pages
1375 * (its own as well as pages explicitly represented in page tables).
1376 * Normally these will be represented as red/black pages, but
1377 * when the supervisor starts to allocate "priority" pages in the PTE
1378 * the hypervisor will need to start marking those pages as (e.g.) "red"
1379 * and non-priority pages as either "black" (if they cache-alias
1380 * with the existing priority pages) or "red/black" (if they don't).
1381 * The bitmask provides information on which parts of the cache
1382 * have been used for pinned pages so far on this tile; if (1 << N)
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04001383 * appears in the bitmask, that indicates that a 4KB region of the
1384 * cache starting at (N * 4KB) is in use by a "priority" page.
1385 * The portion of cache used by a particular page can be computed
1386 * by taking the page's PA, modulo CHIP_L2_CACHE_SIZE(), and setting
1387 * all the "4KB" bits corresponding to the actual page size.
Chris Metcalf867e3592010-05-28 23:09:12 -04001388 * @param bitmask A bitmap of priority page set values
1389 */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04001390void hv_set_caching(unsigned long bitmask);
Chris Metcalf867e3592010-05-28 23:09:12 -04001391
1392
1393/** Zero out a specified number of pages.
1394 * The va and size must both be multiples of 4096.
1395 * Caches are bypassed and memory is directly set to zero.
1396 * This API is implemented only in the magic hypervisor and is intended
1397 * to provide a performance boost to the minimal supervisor by
1398 * giving it a fast way to zero memory pages when allocating them.
1399 * @param va Virtual address where the page has been mapped
1400 * @param size Number of bytes (must be a page size multiple)
1401 */
1402void hv_bzero_page(HV_VirtAddr va, unsigned int size);
1403
1404
1405/** State object for the hypervisor messaging subsystem. */
1406typedef struct
1407{
1408#if CHIP_VA_WIDTH() > 32
1409 __hv64 opaque[2]; /**< No user-serviceable parts inside */
1410#else
1411 __hv32 opaque[2]; /**< No user-serviceable parts inside */
1412#endif
1413}
1414HV_MsgState;
1415
1416/** Register to receive incoming messages.
1417 *
1418 * This routine configures the current tile so that it can receive
1419 * incoming messages. It must be called before the client can receive
1420 * messages with the hv_receive_message routine, and must be called on
1421 * each tile which will receive messages.
1422 *
1423 * msgstate is the virtual address of a state object of type HV_MsgState.
1424 * Once the state is registered, the client must not read or write the
1425 * state object; doing so will cause undefined results.
1426 *
1427 * If this routine is called with msgstate set to 0, the client's message
1428 * state will be freed and it will no longer be able to receive messages.
1429 * Note that this may cause the loss of any as-yet-undelivered messages
1430 * for the client.
1431 *
1432 * If another client attempts to send a message to a client which has
1433 * not yet called hv_register_message_state, or which has freed its
1434 * message state, the message will not be delivered, as if the client
1435 * had insufficient buffering.
1436 *
1437 * This routine returns HV_OK if the registration was successful, and
1438 * HV_EINVAL if the supplied state object is unsuitable. Note that some
1439 * errors may not be detected during this routine, but might be detected
1440 * during a subsequent message delivery.
1441 * @param msgstate State object.
1442 **/
1443HV_Errno hv_register_message_state(HV_MsgState* msgstate);
1444
1445/** Possible message recipient states. */
1446typedef enum
1447{
1448 HV_TO_BE_SENT, /**< Not sent (not attempted, or recipient not ready) */
1449 HV_SENT, /**< Successfully sent */
1450 HV_BAD_RECIP /**< Bad recipient coordinates (permanent error) */
1451} HV_Recip_State;
1452
1453/** Message recipient. */
1454typedef struct
1455{
1456 /** X coordinate, relative to supervisor's top-left coordinate */
1457 unsigned int x:11;
1458
1459 /** Y coordinate, relative to supervisor's top-left coordinate */
1460 unsigned int y:11;
1461
1462 /** Status of this recipient */
1463 HV_Recip_State state:10;
1464} HV_Recipient;
1465
1466/** Send a message to a set of recipients.
1467 *
1468 * This routine sends a message to a set of recipients.
1469 *
1470 * recips is an array of HV_Recipient structures. Each specifies a tile,
1471 * and a message state; initially, it is expected that the state will
1472 * be set to HV_TO_BE_SENT. nrecip specifies the number of recipients
1473 * in the recips array.
1474 *
1475 * For each recipient whose state is HV_TO_BE_SENT, the hypervisor attempts
1476 * to send that tile the specified message. In order to successfully
1477 * receive the message, the receiver must be a valid tile to which the
1478 * sender has access, must not be the sending tile itself, and must have
1479 * sufficient free buffer space. (The hypervisor guarantees that each
1480 * tile which has called hv_register_message_state() will be able to
1481 * buffer one message from every other tile which can legally send to it;
1482 * more space may be provided but is not guaranteed.) If an invalid tile
1483 * is specified, the recipient's state is set to HV_BAD_RECIP; this is a
1484 * permanent delivery error. If the message is successfully delivered
1485 * to the recipient's buffer, the recipient's state is set to HV_SENT.
1486 * Otherwise, the recipient's state is unchanged. Message delivery is
1487 * synchronous; all attempts to send messages are completed before this
1488 * routine returns.
1489 *
1490 * If no permanent delivery errors were encountered, the routine returns
1491 * the number of messages successfully sent: that is, the number of
1492 * recipients whose states changed from HV_TO_BE_SENT to HV_SENT during
1493 * this operation. If any permanent delivery errors were encountered,
1494 * the routine returns HV_ERECIP. In the event of permanent delivery
1495 * errors, it may be the case that delivery was not attempted to all
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001496 * recipients; if any messages were successfully delivered, however,
Chris Metcalf867e3592010-05-28 23:09:12 -04001497 * recipients' state values will be updated appropriately.
1498 *
1499 * It is explicitly legal to specify a recipient structure whose state
1500 * is not HV_TO_BE_SENT; such a recipient is ignored. One suggested way
1501 * of using hv_send_message to send a message to multiple tiles is to set
1502 * up a list of recipients, and then call the routine repeatedly with the
1503 * same list, each time accumulating the number of messages successfully
1504 * sent, until all messages are sent, a permanent error is encountered,
1505 * or the desired number of attempts have been made. When used in this
1506 * way, the routine will deliver each message no more than once to each
1507 * recipient.
1508 *
1509 * Note that a message being successfully delivered to the recipient's
1510 * buffer space does not guarantee that it is received by the recipient,
1511 * either immediately or at any time in the future; the recipient might
1512 * never call hv_receive_message, or could register a different state
1513 * buffer, losing the message.
1514 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001515 * Specifying the same recipient more than once in the recipient list
Chris Metcalf867e3592010-05-28 23:09:12 -04001516 * is an error, which will not result in an error return but which may
1517 * or may not result in more than one message being delivered to the
1518 * recipient tile.
1519 *
1520 * buf and buflen specify the message to be sent. buf is a virtual address
1521 * which must be currently mapped in the client's page table; if not, the
1522 * routine returns HV_EFAULT. buflen must be greater than zero and less
1523 * than or equal to HV_MAX_MESSAGE_SIZE, and nrecip must be less than the
1524 * number of tiles to which the sender has access; if not, the routine
1525 * returns HV_EINVAL.
1526 * @param recips List of recipients.
1527 * @param nrecip Number of recipients.
1528 * @param buf Address of message data.
1529 * @param buflen Length of message data.
1530 **/
1531int hv_send_message(HV_Recipient *recips, int nrecip,
1532 HV_VirtAddr buf, int buflen);
1533
1534/** Maximum hypervisor message size, in bytes */
1535#define HV_MAX_MESSAGE_SIZE 28
1536
1537
1538/** Return value from hv_receive_message() */
1539typedef struct
1540{
1541 int msglen; /**< Message length in bytes, or an error code */
1542 __hv32 source; /**< Code identifying message sender (HV_MSG_xxx) */
1543} HV_RcvMsgInfo;
1544
1545#define HV_MSG_TILE 0x0 /**< Message source is another tile */
1546#define HV_MSG_INTR 0x1 /**< Message source is a driver interrupt */
1547
1548/** Receive a message.
1549 *
1550 * This routine retrieves a message from the client's incoming message
1551 * buffer.
1552 *
1553 * Multiple messages sent from a particular sending tile to a particular
1554 * receiving tile are received in the order that they were sent; however,
1555 * no ordering is guaranteed between messages sent by different tiles.
1556 *
1557 * Whenever the a client's message buffer is empty, the first message
1558 * subsequently received will cause the client's MESSAGE_RCV_DWNCL
1559 * interrupt vector to be invoked through the interrupt downcall mechanism
1560 * (see the description of the hv_downcall_dispatch() routine for details
1561 * on downcalls).
1562 *
1563 * Another message-available downcall will not occur until a call to
1564 * this routine is made when the message buffer is empty, and a message
1565 * subsequently arrives. Note that such a downcall could occur while
1566 * this routine is executing. If the calling code does not wish this
1567 * to happen, it is recommended that this routine be called with the
1568 * INTCTRL_1 interrupt masked, or inside an interrupt critical section.
1569 *
1570 * msgstate is the value previously passed to hv_register_message_state().
1571 * buf is the virtual address of the buffer into which the message will
1572 * be written; buflen is the length of the buffer.
1573 *
1574 * This routine returns an HV_RcvMsgInfo structure. The msglen member
1575 * of that structure is the length of the message received, zero if no
1576 * message is available, or HV_E2BIG if the message is too large for the
1577 * specified buffer. If the message is too large, it is not consumed,
1578 * and may be retrieved by a subsequent call to this routine specifying
1579 * a sufficiently large buffer. A buffer which is HV_MAX_MESSAGE_SIZE
1580 * bytes long is guaranteed to be able to receive any possible message.
1581 *
1582 * The source member of the HV_RcvMsgInfo structure describes the sender
1583 * of the message. For messages sent by another client tile via an
1584 * hv_send_message() call, this value is HV_MSG_TILE; for messages sent
1585 * as a result of a device interrupt, this value is HV_MSG_INTR.
1586 */
1587
1588HV_RcvMsgInfo hv_receive_message(HV_MsgState msgstate, HV_VirtAddr buf,
1589 int buflen);
1590
1591
1592/** Start remaining tiles owned by this supervisor. Initially, only one tile
1593 * executes the client program; after it calls this service, the other tiles
1594 * are started. This allows the initial tile to do one-time configuration
1595 * of shared data structures without having to lock them against simultaneous
1596 * access.
1597 */
1598void hv_start_all_tiles(void);
1599
1600
1601/** Open a hypervisor device.
1602 *
1603 * This service initializes an I/O device and its hypervisor driver software,
1604 * and makes it available for use. The open operation is per-device per-chip;
1605 * once it has been performed, the device handle returned may be used in other
1606 * device services calls made by any tile.
1607 *
1608 * @param name Name of the device. A base device name is just a text string
1609 * (say, "pcie"). If there is more than one instance of a device, the
1610 * base name is followed by a slash and a device number (say, "pcie/0").
1611 * Some devices may support further structure beneath those components;
1612 * most notably, devices which require control operations do so by
1613 * supporting reads and/or writes to a control device whose name
1614 * includes a trailing "/ctl" (say, "pcie/0/ctl").
1615 * @param flags Flags (HV_DEV_xxx).
1616 * @return A positive integer device handle, or a negative error code.
1617 */
1618int hv_dev_open(HV_VirtAddr name, __hv32 flags);
1619
1620
1621/** Close a hypervisor device.
1622 *
1623 * This service uninitializes an I/O device and its hypervisor driver
1624 * software, and makes it unavailable for use. The close operation is
1625 * per-device per-chip; once it has been performed, the device is no longer
1626 * available. Normally there is no need to ever call the close service.
1627 *
1628 * @param devhdl Device handle of the device to be closed.
1629 * @return Zero if the close is successful, otherwise, a negative error code.
1630 */
1631int hv_dev_close(int devhdl);
1632
1633
1634/** Read data from a hypervisor device synchronously.
1635 *
1636 * This service transfers data from a hypervisor device to a memory buffer.
1637 * When the service returns, the data has been written from the memory buffer,
1638 * and the buffer will not be further modified by the driver.
1639 *
1640 * No ordering is guaranteed between requests issued from different tiles.
1641 *
1642 * Devices may choose to support both the synchronous and asynchronous read
1643 * operations, only one of them, or neither of them.
1644 *
1645 * @param devhdl Device handle of the device to be read from.
1646 * @param flags Flags (HV_DEV_xxx).
1647 * @param va Virtual address of the target data buffer. This buffer must
1648 * be mapped in the currently installed page table; if not, HV_EFAULT
1649 * may be returned.
1650 * @param len Number of bytes to be transferred.
1651 * @param offset Driver-dependent offset. For a random-access device, this is
1652 * often a byte offset from the beginning of the device; in other cases,
1653 * like on a control device, it may have a different meaning.
1654 * @return A non-negative value if the read was at least partially successful;
1655 * otherwise, a negative error code. The precise interpretation of
1656 * the return value is driver-dependent, but many drivers will return
1657 * the number of bytes successfully transferred.
1658 */
1659int hv_dev_pread(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
1660 __hv64 offset);
1661
1662#define HV_DEV_NB_EMPTY 0x1 /**< Don't block when no bytes of data can
1663 be transferred. */
1664#define HV_DEV_NB_PARTIAL 0x2 /**< Don't block when some bytes, but not all
1665 of the requested bytes, can be
1666 transferred. */
1667#define HV_DEV_NOCACHE 0x4 /**< The caller warrants that none of the
1668 cache lines which might contain data
1669 from the requested buffer are valid.
1670 Useful with asynchronous operations
1671 only. */
1672
1673#define HV_DEV_ALLFLAGS (HV_DEV_NB_EMPTY | HV_DEV_NB_PARTIAL | \
1674 HV_DEV_NOCACHE) /**< All HV_DEV_xxx flags */
1675
1676/** Write data to a hypervisor device synchronously.
1677 *
1678 * This service transfers data from a memory buffer to a hypervisor device.
1679 * When the service returns, the data has been read from the memory buffer,
1680 * and the buffer may be overwritten by the client; the data may not
1681 * necessarily have been conveyed to the actual hardware I/O interface.
1682 *
1683 * No ordering is guaranteed between requests issued from different tiles.
1684 *
1685 * Devices may choose to support both the synchronous and asynchronous write
1686 * operations, only one of them, or neither of them.
1687 *
1688 * @param devhdl Device handle of the device to be written to.
1689 * @param flags Flags (HV_DEV_xxx).
1690 * @param va Virtual address of the source data buffer. This buffer must
1691 * be mapped in the currently installed page table; if not, HV_EFAULT
1692 * may be returned.
1693 * @param len Number of bytes to be transferred.
1694 * @param offset Driver-dependent offset. For a random-access device, this is
1695 * often a byte offset from the beginning of the device; in other cases,
1696 * like on a control device, it may have a different meaning.
1697 * @return A non-negative value if the write was at least partially successful;
1698 * otherwise, a negative error code. The precise interpretation of
1699 * the return value is driver-dependent, but many drivers will return
1700 * the number of bytes successfully transferred.
1701 */
1702int hv_dev_pwrite(int devhdl, __hv32 flags, HV_VirtAddr va, __hv32 len,
1703 __hv64 offset);
1704
1705
1706/** Interrupt arguments, used in the asynchronous I/O interfaces. */
1707#if CHIP_VA_WIDTH() > 32
1708typedef __hv64 HV_IntArg;
1709#else
1710typedef __hv32 HV_IntArg;
1711#endif
1712
1713/** Interrupt messages are delivered via the mechanism as normal messages,
1714 * but have a message source of HV_DEV_INTR. The message is formatted
1715 * as an HV_IntrMsg structure.
1716 */
1717
1718typedef struct
1719{
1720 HV_IntArg intarg; /**< Interrupt argument, passed to the poll/preada/pwritea
1721 services */
1722 HV_IntArg intdata; /**< Interrupt-specific interrupt data */
1723} HV_IntrMsg;
1724
1725/** Request an interrupt message when a device condition is satisfied.
1726 *
1727 * This service requests that an interrupt message be delivered to the
1728 * requesting tile when a device becomes readable or writable, or when any
1729 * data queued to the device via previous write operations from this tile
1730 * has been actually sent out on the hardware I/O interface. Devices may
1731 * choose to support any, all, or none of the available conditions.
1732 *
1733 * If multiple conditions are specified, only one message will be
1734 * delivered. If the event mask delivered to that interrupt handler
1735 * indicates that some of the conditions have not yet occurred, the
1736 * client must issue another poll() call if it wishes to wait for those
1737 * conditions.
1738 *
1739 * Only one poll may be outstanding per device handle per tile. If more than
1740 * one tile is polling on the same device and condition, they will all be
1741 * notified when it happens. Because of this, clients may not assume that
1742 * the condition signaled is necessarily still true when they request a
1743 * subsequent service; for instance, the readable data which caused the
1744 * poll call to interrupt may have been read by another tile in the interim.
1745 *
1746 * The notification interrupt message could come directly, or via the
1747 * downcall (intctrl1) method, depending on what the tile is doing
1748 * when the condition is satisfied. Note that it is possible for the
1749 * requested interrupt to be delivered after this service is called but
1750 * before it returns.
1751 *
1752 * @param devhdl Device handle of the device to be polled.
1753 * @param events Flags denoting the events which will cause the interrupt to
1754 * be delivered (HV_DEVPOLL_xxx).
1755 * @param intarg Value which will be delivered as the intarg member of the
1756 * eventual interrupt message; the intdata member will be set to a
1757 * mask of HV_DEVPOLL_xxx values indicating which conditions have been
1758 * satisifed.
1759 * @return Zero if the interrupt was successfully scheduled; otherwise, a
1760 * negative error code.
1761 */
1762int hv_dev_poll(int devhdl, __hv32 events, HV_IntArg intarg);
1763
1764#define HV_DEVPOLL_READ 0x1 /**< Test device for readability */
1765#define HV_DEVPOLL_WRITE 0x2 /**< Test device for writability */
1766#define HV_DEVPOLL_FLUSH 0x4 /**< Test device for output drained */
1767
1768
1769/** Cancel a request for an interrupt when a device event occurs.
1770 *
1771 * This service requests that no interrupt be delivered when the events
1772 * noted in the last-issued poll() call happen. Once this service returns,
1773 * the interrupt has been canceled; however, it is possible for the interrupt
1774 * to be delivered after this service is called but before it returns.
1775 *
1776 * @param devhdl Device handle of the device on which to cancel polling.
1777 * @return Zero if the poll was successfully canceled; otherwise, a negative
1778 * error code.
1779 */
1780int hv_dev_poll_cancel(int devhdl);
1781
1782
1783/** Scatter-gather list for preada/pwritea calls. */
1784typedef struct
1785#if CHIP_VA_WIDTH() <= 32
1786__attribute__ ((packed, aligned(4)))
1787#endif
1788{
1789 HV_PhysAddr pa; /**< Client physical address of the buffer segment. */
1790 HV_PTE pte; /**< Page table entry describing the caching and location
1791 override characteristics of the buffer segment. Some
1792 drivers ignore this element and will require that
1793 the NOCACHE flag be set on their requests. */
1794 __hv32 len; /**< Length of the buffer segment. */
1795} HV_SGL;
1796
1797#define HV_SGL_MAXLEN 16 /**< Maximum number of entries in a scatter-gather
1798 list */
1799
1800/** Read data from a hypervisor device asynchronously.
1801 *
1802 * This service transfers data from a hypervisor device to a memory buffer.
1803 * When the service returns, the read has been scheduled. When the read
1804 * completes, an interrupt message will be delivered, and the buffer will
1805 * not be further modified by the driver.
1806 *
1807 * The number of possible outstanding asynchronous requests is defined by
1808 * each driver, but it is recommended that it be at least two requests
1809 * per tile per device.
1810 *
1811 * No ordering is guaranteed between synchronous and asynchronous requests,
1812 * even those issued on the same tile.
1813 *
1814 * The completion interrupt message could come directly, or via the downcall
1815 * (intctrl1) method, depending on what the tile is doing when the read
1816 * completes. Interrupts do not coalesce; one is delivered for each
1817 * asynchronous I/O request. Note that it is possible for the requested
1818 * interrupt to be delivered after this service is called but before it
1819 * returns.
1820 *
1821 * Devices may choose to support both the synchronous and asynchronous read
1822 * operations, only one of them, or neither of them.
1823 *
1824 * @param devhdl Device handle of the device to be read from.
1825 * @param flags Flags (HV_DEV_xxx).
1826 * @param sgl_len Number of elements in the scatter-gather list.
1827 * @param sgl Scatter-gather list describing the memory to which data will be
1828 * written.
1829 * @param offset Driver-dependent offset. For a random-access device, this is
1830 * often a byte offset from the beginning of the device; in other cases,
1831 * like on a control device, it may have a different meaning.
1832 * @param intarg Value which will be delivered as the intarg member of the
1833 * eventual interrupt message; the intdata member will be set to the
1834 * normal return value from the read request.
1835 * @return Zero if the read was successfully scheduled; otherwise, a negative
1836 * error code. Note that some drivers may choose to pre-validate
1837 * their arguments, and may thus detect certain device error
1838 * conditions at this time rather than when the completion notification
1839 * occurs, but this is not required.
1840 */
1841int hv_dev_preada(int devhdl, __hv32 flags, __hv32 sgl_len,
1842 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
1843
1844
1845/** Write data to a hypervisor device asynchronously.
1846 *
1847 * This service transfers data from a memory buffer to a hypervisor
1848 * device. When the service returns, the write has been scheduled.
1849 * When the write completes, an interrupt message will be delivered,
1850 * and the buffer may be overwritten by the client; the data may not
1851 * necessarily have been conveyed to the actual hardware I/O interface.
1852 *
1853 * The number of possible outstanding asynchronous requests is defined by
1854 * each driver, but it is recommended that it be at least two requests
1855 * per tile per device.
1856 *
1857 * No ordering is guaranteed between synchronous and asynchronous requests,
1858 * even those issued on the same tile.
1859 *
1860 * The completion interrupt message could come directly, or via the downcall
1861 * (intctrl1) method, depending on what the tile is doing when the read
1862 * completes. Interrupts do not coalesce; one is delivered for each
1863 * asynchronous I/O request. Note that it is possible for the requested
1864 * interrupt to be delivered after this service is called but before it
1865 * returns.
1866 *
1867 * Devices may choose to support both the synchronous and asynchronous write
1868 * operations, only one of them, or neither of them.
1869 *
1870 * @param devhdl Device handle of the device to be read from.
1871 * @param flags Flags (HV_DEV_xxx).
1872 * @param sgl_len Number of elements in the scatter-gather list.
1873 * @param sgl Scatter-gather list describing the memory from which data will be
1874 * read.
1875 * @param offset Driver-dependent offset. For a random-access device, this is
1876 * often a byte offset from the beginning of the device; in other cases,
1877 * like on a control device, it may have a different meaning.
1878 * @param intarg Value which will be delivered as the intarg member of the
1879 * eventual interrupt message; the intdata member will be set to the
1880 * normal return value from the write request.
1881 * @return Zero if the write was successfully scheduled; otherwise, a negative
1882 * error code. Note that some drivers may choose to pre-validate
1883 * their arguments, and may thus detect certain device error
1884 * conditions at this time rather than when the completion notification
1885 * occurs, but this is not required.
1886 */
1887int hv_dev_pwritea(int devhdl, __hv32 flags, __hv32 sgl_len,
1888 HV_SGL sgl[/* sgl_len */], __hv64 offset, HV_IntArg intarg);
1889
1890
1891/** Define a pair of tile and ASID to identify a user process context. */
1892typedef struct
1893{
1894 /** X coordinate, relative to supervisor's top-left coordinate */
1895 unsigned int x:11;
1896
1897 /** Y coordinate, relative to supervisor's top-left coordinate */
1898 unsigned int y:11;
1899
1900 /** ASID of the process on this x,y tile */
1901 HV_ASID asid:10;
1902} HV_Remote_ASID;
1903
1904/** Flush cache and/or TLB state on remote tiles.
1905 *
1906 * @param cache_pa Client physical address to flush from cache (ignored if
1907 * the length encoded in cache_control is zero, or if
1908 * HV_FLUSH_EVICT_L2 is set, or if cache_cpumask is NULL).
1909 * @param cache_control This argument allows you to specify a length of
1910 * physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN).
1911 * You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache.
Chris Metcalfc745a8a2010-08-13 08:52:19 -04001912 * You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache.
Chris Metcalf867e3592010-05-28 23:09:12 -04001913 * HV_FLUSH_ALL flushes all caches.
1914 * @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of
1915 * tile indices to perform cache flush on. The low bit of the first
1916 * word corresponds to the tile at the upper left-hand corner of the
1917 * supervisor's rectangle. If passed as a NULL pointer, equivalent
1918 * to an empty bitmask. On chips which support hash-for-home caching,
1919 * if passed as -1, equivalent to a mask containing tiles which could
1920 * be doing hash-for-home caching.
1921 * @param tlb_va Virtual address to flush from TLB (ignored if
1922 * tlb_length is zero or tlb_cpumask is NULL).
1923 * @param tlb_length Number of bytes of data to flush from the TLB.
1924 * @param tlb_pgsize Page size to use for TLB flushes.
1925 * tlb_va and tlb_length need not be aligned to this size.
1926 * @param tlb_cpumask Bitmask for tlb flush, like cache_cpumask.
1927 * If passed as a NULL pointer, equivalent to an empty bitmask.
1928 * @param asids Pointer to an HV_Remote_ASID array of tile/ASID pairs to flush.
1929 * @param asidcount Number of HV_Remote_ASID entries in asids[].
1930 * @return Zero for success, or else HV_EINVAL or HV_EFAULT for errors that
1931 * are detected while parsing the arguments.
1932 */
1933int hv_flush_remote(HV_PhysAddr cache_pa, unsigned long cache_control,
1934 unsigned long* cache_cpumask,
1935 HV_VirtAddr tlb_va, unsigned long tlb_length,
1936 unsigned long tlb_pgsize, unsigned long* tlb_cpumask,
1937 HV_Remote_ASID* asids, int asidcount);
1938
1939/** Include in cache_control to ensure a flush of the entire L2. */
1940#define HV_FLUSH_EVICT_L2 (1UL << 31)
1941
1942/** Include in cache_control to ensure a flush of the entire L1I. */
1943#define HV_FLUSH_EVICT_L1I (1UL << 30)
1944
1945/** Maximum legal size to use for the "length" component of cache_control. */
1946#define HV_FLUSH_MAX_CACHE_LEN ((1UL << 30) - 1)
1947
1948/** Use for cache_control to ensure a flush of all caches. */
1949#define HV_FLUSH_ALL -1UL
1950
1951#else /* __ASSEMBLER__ */
1952
1953/** Include in cache_control to ensure a flush of the entire L2. */
1954#define HV_FLUSH_EVICT_L2 (1 << 31)
1955
1956/** Include in cache_control to ensure a flush of the entire L1I. */
1957#define HV_FLUSH_EVICT_L1I (1 << 30)
1958
1959/** Maximum legal size to use for the "length" component of cache_control. */
1960#define HV_FLUSH_MAX_CACHE_LEN ((1 << 30) - 1)
1961
1962/** Use for cache_control to ensure a flush of all caches. */
1963#define HV_FLUSH_ALL -1
1964
1965#endif /* __ASSEMBLER__ */
1966
1967#ifndef __ASSEMBLER__
1968
1969/** Return a 64-bit value corresponding to the PTE if needed */
1970#define hv_pte_val(pte) ((pte).val)
1971
1972/** Cast a 64-bit value to an HV_PTE */
1973#define hv_pte(val) ((HV_PTE) { val })
1974
1975#endif /* !__ASSEMBLER__ */
1976
1977
1978/** Bits in the size of an HV_PTE */
1979#define HV_LOG2_PTE_SIZE 3
1980
1981/** Size of an HV_PTE */
1982#define HV_PTE_SIZE (1 << HV_LOG2_PTE_SIZE)
1983
1984
1985/* Bits in HV_PTE's low word. */
1986#define HV_PTE_INDEX_PRESENT 0 /**< PTE is valid */
1987#define HV_PTE_INDEX_MIGRATING 1 /**< Page is migrating */
1988#define HV_PTE_INDEX_CLIENT0 2 /**< Page client state 0 */
1989#define HV_PTE_INDEX_CLIENT1 3 /**< Page client state 1 */
1990#define HV_PTE_INDEX_NC 4 /**< L1$/L2$ incoherent with L3$ */
1991#define HV_PTE_INDEX_NO_ALLOC_L1 5 /**< Page is uncached in local L1$ */
1992#define HV_PTE_INDEX_NO_ALLOC_L2 6 /**< Page is uncached in local L2$ */
1993#define HV_PTE_INDEX_CACHED_PRIORITY 7 /**< Page is priority cached */
1994#define HV_PTE_INDEX_PAGE 8 /**< PTE describes a page */
1995#define HV_PTE_INDEX_GLOBAL 9 /**< Page is global */
1996#define HV_PTE_INDEX_USER 10 /**< Page is user-accessible */
1997#define HV_PTE_INDEX_ACCESSED 11 /**< Page has been accessed */
1998#define HV_PTE_INDEX_DIRTY 12 /**< Page has been written */
Chris Metcalf621b1952012-04-01 14:04:21 -04001999 /* Bits 13-14 are reserved for
Chris Metcalf867e3592010-05-28 23:09:12 -04002000 future use. */
Chris Metcalf621b1952012-04-01 14:04:21 -04002001#define HV_PTE_INDEX_SUPER 15 /**< Pages ganged together for TLB */
Chris Metcalf867e3592010-05-28 23:09:12 -04002002#define HV_PTE_INDEX_MODE 16 /**< Page mode; see HV_PTE_MODE_xxx */
2003#define HV_PTE_MODE_BITS 3 /**< Number of bits in mode */
Chris Metcalf73636b12012-03-28 13:59:18 -04002004#define HV_PTE_INDEX_CLIENT2 19 /**< Page client state 2 */
Chris Metcalf867e3592010-05-28 23:09:12 -04002005#define HV_PTE_INDEX_LOTAR 20 /**< Page's LOTAR; must be high bits
2006 of word */
2007#define HV_PTE_LOTAR_BITS 12 /**< Number of bits in a LOTAR */
2008
2009/* Bits in HV_PTE's high word. */
2010#define HV_PTE_INDEX_READABLE 32 /**< Page is readable */
2011#define HV_PTE_INDEX_WRITABLE 33 /**< Page is writable */
2012#define HV_PTE_INDEX_EXECUTABLE 34 /**< Page is executable */
2013#define HV_PTE_INDEX_PTFN 35 /**< Page's PTFN; must be high bits
2014 of word */
2015#define HV_PTE_PTFN_BITS 29 /**< Number of bits in a PTFN */
2016
Chris Metcalf867e3592010-05-28 23:09:12 -04002017/*
2018 * Legal values for the PTE's mode field
2019 */
2020/** Data is not resident in any caches; loads and stores access memory
2021 * directly.
2022 */
2023#define HV_PTE_MODE_UNCACHED 1
2024
2025/** Data is resident in the tile's local L1 and/or L2 caches; if a load
2026 * or store misses there, it goes to memory.
2027 *
2028 * The copy in the local L1$/L2$ is not invalidated when the copy in
2029 * memory is changed.
2030 */
2031#define HV_PTE_MODE_CACHE_NO_L3 2
2032
2033/** Data is resident in the tile's local L1 and/or L2 caches. If a load
2034 * or store misses there, it goes to an L3 cache in a designated tile;
2035 * if it misses there, it goes to memory.
2036 *
2037 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
2038 * when the copy in the remote L3$ is changed. Otherwise, such
2039 * invalidation will not occur.
2040 *
2041 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
2042 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
2043 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
2044 */
2045#define HV_PTE_MODE_CACHE_TILE_L3 3
2046
2047/** Data is resident in the tile's local L1 and/or L2 caches. If a load
2048 * or store misses there, it goes to an L3 cache in one of a set of
2049 * designated tiles; if it misses there, it goes to memory. Which tile
2050 * is chosen from the set depends upon a hash function applied to the
2051 * physical address. This mode is not supported on chips for which
2052 * CHIP_HAS_CBOX_HOME_MAP() is 0.
2053 *
2054 * If the NC bit is not set, the copy in the local L1$/L2$ is invalidated
2055 * when the copy in the remote L3$ is changed. Otherwise, such
2056 * invalidation will not occur.
2057 *
2058 * Chips for which CHIP_HAS_COHERENT_LOCAL_CACHE() is 0 do not support
2059 * invalidation from an L3$ to another tile's L1$/L2$. If the NC bit is
2060 * clear on such a chip, no copy is kept in the local L1$/L2$ in this mode.
2061 */
2062#define HV_PTE_MODE_CACHE_HASH_L3 4
2063
2064/** Data is not resident in memory; accesses are instead made to an I/O
2065 * device, whose tile coordinates are given by the PTE's LOTAR field.
2066 * This mode is only supported on chips for which CHIP_HAS_MMIO() is 1.
2067 * The EXECUTABLE bit may not be set in an MMIO PTE.
2068 */
2069#define HV_PTE_MODE_MMIO 5
2070
2071
2072/* C wants 1ULL so it is typed as __hv64, but the assembler needs just numbers.
2073 * The assembler can't handle shifts greater than 31, but treats them
2074 * as shifts mod 32, so assembler code must be aware of which word
2075 * the bit belongs in when using these macros.
2076 */
2077#ifdef __ASSEMBLER__
2078#define __HV_PTE_ONE 1 /**< One, for assembler */
2079#else
2080#define __HV_PTE_ONE 1ULL /**< One, for C */
2081#endif
2082
2083/** Is this PTE present?
2084 *
2085 * If this bit is set, this PTE represents a valid translation or level-2
2086 * page table pointer. Otherwise, the page table does not contain a
2087 * translation for the subject virtual pages.
2088 *
2089 * If this bit is not set, the other bits in the PTE are not
2090 * interpreted by the hypervisor, and may contain any value.
2091 */
2092#define HV_PTE_PRESENT (__HV_PTE_ONE << HV_PTE_INDEX_PRESENT)
2093
2094/** Does this PTE map a page?
2095 *
Chris Metcalf621b1952012-04-01 14:04:21 -04002096 * If this bit is set in a level-0 page table, the entry should be
2097 * interpreted as a level-2 page table entry mapping a jumbo page.
2098 *
2099 * If this bit is set in a level-1 page table, the entry should be
Chris Metcalf867e3592010-05-28 23:09:12 -04002100 * interpreted as a level-2 page table entry mapping a large page.
2101 *
2102 * This bit should not be modified by the client while PRESENT is set, as
2103 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
2104 *
2105 * In a level-2 page table, this bit is ignored and must be zero.
2106 */
2107#define HV_PTE_PAGE (__HV_PTE_ONE << HV_PTE_INDEX_PAGE)
2108
Chris Metcalf621b1952012-04-01 14:04:21 -04002109/** Does this PTE implicitly reference multiple pages?
2110 *
2111 * If this bit is set in the page table (either in the level-2 page table,
2112 * or in a higher level page table in conjunction with the PAGE bit)
2113 * then the PTE specifies a range of contiguous pages, not a single page.
2114 * The hv_set_pte_super_shift() allows you to specify the count for
2115 * each level of the page table.
2116 *
2117 * Note: this bit is not supported on TILEPro systems.
2118 */
2119#define HV_PTE_SUPER (__HV_PTE_ONE << HV_PTE_INDEX_SUPER)
2120
Chris Metcalf867e3592010-05-28 23:09:12 -04002121/** Is this a global (non-ASID) mapping?
2122 *
2123 * If this bit is set, the translations established by this PTE will
2124 * not be flushed from the TLB by the hv_flush_asid() service; they
2125 * will be flushed by the hv_flush_page() or hv_flush_pages() services.
2126 *
2127 * Setting this bit for translations which are identical in all page
2128 * tables (for instance, code and data belonging to a client OS) can
2129 * be very beneficial, as it will reduce the number of TLB misses.
2130 * Note that, while it is not an error which will be detected by the
2131 * hypervisor, it is an extremely bad idea to set this bit for
2132 * translations which are _not_ identical in all page tables.
2133 *
2134 * This bit should not be modified by the client while PRESENT is set, as
2135 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
2136 *
2137 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2138 */
2139#define HV_PTE_GLOBAL (__HV_PTE_ONE << HV_PTE_INDEX_GLOBAL)
2140
2141/** Is this mapping accessible to users?
2142 *
2143 * If this bit is set, code running at any PL will be permitted to
2144 * access the virtual addresses mapped by this PTE. Otherwise, only
2145 * code running at PL 1 or above will be allowed to do so.
2146 *
2147 * This bit should not be modified by the client while PRESENT is set, as
2148 * doing so may race with the hypervisor's update of ACCESSED and DIRTY bits.
2149 *
2150 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2151 */
2152#define HV_PTE_USER (__HV_PTE_ONE << HV_PTE_INDEX_USER)
2153
2154/** Has this mapping been accessed?
2155 *
2156 * This bit is set by the hypervisor when the memory described by the
2157 * translation is accessed for the first time. It is never cleared by
2158 * the hypervisor, but may be cleared by the client. After the bit
2159 * has been cleared, subsequent references are not guaranteed to set
2160 * it again until the translation has been flushed from the TLB.
2161 *
2162 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2163 */
2164#define HV_PTE_ACCESSED (__HV_PTE_ONE << HV_PTE_INDEX_ACCESSED)
2165
2166/** Is this mapping dirty?
2167 *
2168 * This bit is set by the hypervisor when the memory described by the
2169 * translation is written for the first time. It is never cleared by
2170 * the hypervisor, but may be cleared by the client. After the bit
2171 * has been cleared, subsequent references are not guaranteed to set
2172 * it again until the translation has been flushed from the TLB.
2173 *
2174 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2175 */
2176#define HV_PTE_DIRTY (__HV_PTE_ONE << HV_PTE_INDEX_DIRTY)
2177
2178/** Migrating bit in PTE.
2179 *
2180 * This bit is guaranteed not to be inspected or modified by the
2181 * hypervisor. The name is indicative of the suggested use by the client
2182 * to tag pages whose L3 cache is being migrated from one cpu to another.
2183 */
2184#define HV_PTE_MIGRATING (__HV_PTE_ONE << HV_PTE_INDEX_MIGRATING)
2185
2186/** Client-private bit in PTE.
2187 *
2188 * This bit is guaranteed not to be inspected or modified by the
2189 * hypervisor.
2190 */
2191#define HV_PTE_CLIENT0 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT0)
2192
2193/** Client-private bit in PTE.
2194 *
2195 * This bit is guaranteed not to be inspected or modified by the
2196 * hypervisor.
2197 */
2198#define HV_PTE_CLIENT1 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT1)
2199
Chris Metcalf73636b12012-03-28 13:59:18 -04002200/** Client-private bit in PTE.
2201 *
2202 * This bit is guaranteed not to be inspected or modified by the
2203 * hypervisor.
2204 */
2205#define HV_PTE_CLIENT2 (__HV_PTE_ONE << HV_PTE_INDEX_CLIENT2)
2206
Chris Metcalf867e3592010-05-28 23:09:12 -04002207/** Non-coherent (NC) bit in PTE.
2208 *
2209 * If this bit is set, the mapping that is set up will be non-coherent
2210 * (also known as non-inclusive). This means that changes to the L3
2211 * cache will not cause a local copy to be invalidated. It is generally
2212 * recommended only for read-only mappings.
2213 *
2214 * In level-1 PTEs, if the Page bit is clear, this bit determines how the
2215 * level-2 page table is accessed.
2216 */
2217#define HV_PTE_NC (__HV_PTE_ONE << HV_PTE_INDEX_NC)
2218
2219/** Is this page prevented from filling the L1$?
2220 *
2221 * If this bit is set, the page described by the PTE will not be cached
2222 * the local cpu's L1 cache.
2223 *
2224 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
2225 * it is illegal to use this attribute, and may cause client termination.
2226 *
2227 * In level-1 PTEs, if the Page bit is clear, this bit
2228 * determines how the level-2 page table is accessed.
2229 */
2230#define HV_PTE_NO_ALLOC_L1 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L1)
2231
2232/** Is this page prevented from filling the L2$?
2233 *
2234 * If this bit is set, the page described by the PTE will not be cached
2235 * the local cpu's L2 cache.
2236 *
2237 * If CHIP_HAS_NC_AND_NOALLOC_BITS() is not true in <chip.h> for this chip,
2238 * it is illegal to use this attribute, and may cause client termination.
2239 *
2240 * In level-1 PTEs, if the Page bit is clear, this bit determines how the
2241 * level-2 page table is accessed.
2242 */
2243#define HV_PTE_NO_ALLOC_L2 (__HV_PTE_ONE << HV_PTE_INDEX_NO_ALLOC_L2)
2244
2245/** Is this a priority page?
2246 *
2247 * If this bit is set, the page described by the PTE will be given
2248 * priority in the cache. Normally this translates into allowing the
2249 * page to use only the "red" half of the cache. The client may wish to
2250 * then use the hv_set_caching service to specify that other pages which
2251 * alias this page will use only the "black" half of the cache.
2252 *
2253 * If the Cached Priority bit is clear, the hypervisor uses the
2254 * current hv_set_caching() value to choose how to cache the page.
2255 *
2256 * It is illegal to set the Cached Priority bit if the Non-Cached bit
2257 * is set and the Cached Remotely bit is clear, i.e. if requests to
2258 * the page map directly to memory.
2259 *
2260 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2261 */
2262#define HV_PTE_CACHED_PRIORITY (__HV_PTE_ONE << \
2263 HV_PTE_INDEX_CACHED_PRIORITY)
2264
2265/** Is this a readable mapping?
2266 *
2267 * If this bit is set, code will be permitted to read from (e.g.,
2268 * issue load instructions against) the virtual addresses mapped by
2269 * this PTE.
2270 *
2271 * It is illegal for this bit to be clear if the Writable bit is set.
2272 *
2273 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2274 */
2275#define HV_PTE_READABLE (__HV_PTE_ONE << HV_PTE_INDEX_READABLE)
2276
2277/** Is this a writable mapping?
2278 *
2279 * If this bit is set, code will be permitted to write to (e.g., issue
2280 * store instructions against) the virtual addresses mapped by this
2281 * PTE.
2282 *
2283 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2284 */
2285#define HV_PTE_WRITABLE (__HV_PTE_ONE << HV_PTE_INDEX_WRITABLE)
2286
2287/** Is this an executable mapping?
2288 *
2289 * If this bit is set, code will be permitted to execute from
2290 * (e.g., jump to) the virtual addresses mapped by this PTE.
2291 *
2292 * This bit applies to any processor on the tile, if there are more
2293 * than one.
2294 *
2295 * This bit is ignored in level-1 PTEs unless the Page bit is set.
2296 */
2297#define HV_PTE_EXECUTABLE (__HV_PTE_ONE << HV_PTE_INDEX_EXECUTABLE)
2298
2299/** The width of a LOTAR's x or y bitfield. */
2300#define HV_LOTAR_WIDTH 11
2301
2302/** Converts an x,y pair to a LOTAR value. */
2303#define HV_XY_TO_LOTAR(x, y) ((HV_LOTAR)(((x) << HV_LOTAR_WIDTH) | (y)))
2304
2305/** Extracts the X component of a lotar. */
2306#define HV_LOTAR_X(lotar) ((lotar) >> HV_LOTAR_WIDTH)
2307
2308/** Extracts the Y component of a lotar. */
2309#define HV_LOTAR_Y(lotar) ((lotar) & ((1 << HV_LOTAR_WIDTH) - 1))
2310
2311#ifndef __ASSEMBLER__
2312
2313/** Define accessor functions for a PTE bit. */
2314#define _HV_BIT(name, bit) \
2315static __inline int \
2316hv_pte_get_##name(HV_PTE pte) \
2317{ \
2318 return (pte.val >> HV_PTE_INDEX_##bit) & 1; \
2319} \
2320 \
2321static __inline HV_PTE \
2322hv_pte_set_##name(HV_PTE pte) \
2323{ \
2324 pte.val |= 1ULL << HV_PTE_INDEX_##bit; \
2325 return pte; \
2326} \
2327 \
2328static __inline HV_PTE \
2329hv_pte_clear_##name(HV_PTE pte) \
2330{ \
2331 pte.val &= ~(1ULL << HV_PTE_INDEX_##bit); \
2332 return pte; \
2333}
2334
2335/* Generate accessors to get, set, and clear various PTE flags.
2336 */
2337_HV_BIT(present, PRESENT)
2338_HV_BIT(page, PAGE)
Chris Metcalf621b1952012-04-01 14:04:21 -04002339_HV_BIT(super, SUPER)
Chris Metcalf867e3592010-05-28 23:09:12 -04002340_HV_BIT(client0, CLIENT0)
2341_HV_BIT(client1, CLIENT1)
Chris Metcalf73636b12012-03-28 13:59:18 -04002342_HV_BIT(client2, CLIENT2)
Chris Metcalf867e3592010-05-28 23:09:12 -04002343_HV_BIT(migrating, MIGRATING)
2344_HV_BIT(nc, NC)
2345_HV_BIT(readable, READABLE)
2346_HV_BIT(writable, WRITABLE)
2347_HV_BIT(executable, EXECUTABLE)
2348_HV_BIT(accessed, ACCESSED)
2349_HV_BIT(dirty, DIRTY)
2350_HV_BIT(no_alloc_l1, NO_ALLOC_L1)
2351_HV_BIT(no_alloc_l2, NO_ALLOC_L2)
2352_HV_BIT(cached_priority, CACHED_PRIORITY)
2353_HV_BIT(global, GLOBAL)
2354_HV_BIT(user, USER)
2355
2356#undef _HV_BIT
2357
2358/** Get the page mode from the PTE.
2359 *
2360 * This field generally determines whether and how accesses to the page
2361 * are cached; the HV_PTE_MODE_xxx symbols define the legal values for the
2362 * page mode. The NC, NO_ALLOC_L1, and NO_ALLOC_L2 bits modify this
2363 * general policy.
2364 */
2365static __inline unsigned int
2366hv_pte_get_mode(const HV_PTE pte)
2367{
2368 return (((__hv32) pte.val) >> HV_PTE_INDEX_MODE) &
2369 ((1 << HV_PTE_MODE_BITS) - 1);
2370}
2371
2372/** Set the page mode into a PTE. See hv_pte_get_mode. */
2373static __inline HV_PTE
2374hv_pte_set_mode(HV_PTE pte, unsigned int val)
2375{
2376 pte.val &= ~(((1ULL << HV_PTE_MODE_BITS) - 1) << HV_PTE_INDEX_MODE);
2377 pte.val |= val << HV_PTE_INDEX_MODE;
2378 return pte;
2379}
2380
2381/** Get the page frame number from the PTE.
2382 *
2383 * This field contains the upper bits of the CPA (client physical
2384 * address) of the target page; the complete CPA is this field with
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002385 * HV_LOG2_PAGE_TABLE_ALIGN zero bits appended to it.
Chris Metcalf867e3592010-05-28 23:09:12 -04002386 *
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002387 * For all PTEs in the lowest-level page table, and for all PTEs with
2388 * the Page bit set in all page tables, the CPA must be aligned modulo
2389 * the relevant page size.
Chris Metcalf867e3592010-05-28 23:09:12 -04002390 */
2391static __inline unsigned long
2392hv_pte_get_ptfn(const HV_PTE pte)
2393{
2394 return pte.val >> HV_PTE_INDEX_PTFN;
2395}
2396
Chris Metcalf867e3592010-05-28 23:09:12 -04002397/** Set the page table frame number into a PTE. See hv_pte_get_ptfn. */
2398static __inline HV_PTE
2399hv_pte_set_ptfn(HV_PTE pte, unsigned long val)
2400{
2401 pte.val &= ~(((1ULL << HV_PTE_PTFN_BITS)-1) << HV_PTE_INDEX_PTFN);
2402 pte.val |= (__hv64) val << HV_PTE_INDEX_PTFN;
2403 return pte;
2404}
2405
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002406/** Get the client physical address from the PTE. See hv_pte_set_ptfn. */
2407static __inline HV_PhysAddr
2408hv_pte_get_pa(const HV_PTE pte)
2409{
2410 return (__hv64) hv_pte_get_ptfn(pte) << HV_LOG2_PAGE_TABLE_ALIGN;
2411}
2412
2413/** Set the client physical address into a PTE. See hv_pte_get_ptfn. */
2414static __inline HV_PTE
2415hv_pte_set_pa(HV_PTE pte, HV_PhysAddr pa)
2416{
2417 return hv_pte_set_ptfn(pte, pa >> HV_LOG2_PAGE_TABLE_ALIGN);
2418}
2419
Chris Metcalf867e3592010-05-28 23:09:12 -04002420
2421/** Get the remote tile caching this page.
2422 *
2423 * Specifies the remote tile which is providing the L3 cache for this page.
2424 *
2425 * This field is ignored unless the page mode is HV_PTE_MODE_CACHE_TILE_L3.
2426 *
2427 * In level-1 PTEs, if the Page bit is clear, this field determines how the
2428 * level-2 page table is accessed.
2429 */
2430static __inline unsigned int
2431hv_pte_get_lotar(const HV_PTE pte)
2432{
2433 unsigned int lotar = ((__hv32) pte.val) >> HV_PTE_INDEX_LOTAR;
2434
2435 return HV_XY_TO_LOTAR( (lotar >> (HV_PTE_LOTAR_BITS / 2)),
2436 (lotar & ((1 << (HV_PTE_LOTAR_BITS / 2)) - 1)) );
2437}
2438
2439
2440/** Set the remote tile caching a page into a PTE. See hv_pte_get_lotar. */
2441static __inline HV_PTE
2442hv_pte_set_lotar(HV_PTE pte, unsigned int val)
2443{
2444 unsigned int x = HV_LOTAR_X(val);
2445 unsigned int y = HV_LOTAR_Y(val);
2446
2447 pte.val &= ~(((1ULL << HV_PTE_LOTAR_BITS)-1) << HV_PTE_INDEX_LOTAR);
2448 pte.val |= (x << (HV_PTE_INDEX_LOTAR + HV_PTE_LOTAR_BITS / 2)) |
2449 (y << HV_PTE_INDEX_LOTAR);
2450 return pte;
2451}
2452
2453#endif /* !__ASSEMBLER__ */
2454
Chris Metcalf867e3592010-05-28 23:09:12 -04002455/** Converts a client physical address to a ptfn. */
2456#define HV_CPA_TO_PTFN(p) ((p) >> HV_LOG2_PAGE_TABLE_ALIGN)
2457
2458/** Converts a ptfn to a client physical address. */
2459#define HV_PTFN_TO_CPA(p) (((HV_PhysAddr)(p)) << HV_LOG2_PAGE_TABLE_ALIGN)
2460
Chris Metcalf867e3592010-05-28 23:09:12 -04002461#if CHIP_VA_WIDTH() > 32
2462
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002463/*
2464 * Note that we currently do not allow customizing the page size
2465 * of the L0 pages, but fix them at 4GB, so we do not use the
2466 * "_HV_xxx" nomenclature for the L0 macros.
2467 */
2468
Chris Metcalf867e3592010-05-28 23:09:12 -04002469/** Log number of HV_PTE entries in L0 page table */
2470#define HV_LOG2_L0_ENTRIES (CHIP_VA_WIDTH() - HV_LOG2_L1_SPAN)
2471
2472/** Number of HV_PTE entries in L0 page table */
2473#define HV_L0_ENTRIES (1 << HV_LOG2_L0_ENTRIES)
2474
2475/** Log size of L0 page table in bytes */
2476#define HV_LOG2_L0_SIZE (HV_LOG2_PTE_SIZE + HV_LOG2_L0_ENTRIES)
2477
2478/** Size of L0 page table in bytes */
2479#define HV_L0_SIZE (1 << HV_LOG2_L0_SIZE)
2480
2481#ifdef __ASSEMBLER__
2482
2483/** Index in L0 for a specific VA */
2484#define HV_L0_INDEX(va) \
2485 (((va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
2486
2487#else
2488
2489/** Index in L1 for a specific VA */
2490#define HV_L0_INDEX(va) \
2491 (((HV_VirtAddr)(va) >> HV_LOG2_L1_SPAN) & (HV_L0_ENTRIES - 1))
2492
2493#endif
2494
2495#endif /* CHIP_VA_WIDTH() > 32 */
2496
2497/** Log number of HV_PTE entries in L1 page table */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002498#define _HV_LOG2_L1_ENTRIES(log2_page_size_large) \
2499 (HV_LOG2_L1_SPAN - log2_page_size_large)
Chris Metcalf867e3592010-05-28 23:09:12 -04002500
2501/** Number of HV_PTE entries in L1 page table */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002502#define _HV_L1_ENTRIES(log2_page_size_large) \
2503 (1 << _HV_LOG2_L1_ENTRIES(log2_page_size_large))
Chris Metcalf867e3592010-05-28 23:09:12 -04002504
2505/** Log size of L1 page table in bytes */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002506#define _HV_LOG2_L1_SIZE(log2_page_size_large) \
2507 (HV_LOG2_PTE_SIZE + _HV_LOG2_L1_ENTRIES(log2_page_size_large))
Chris Metcalf867e3592010-05-28 23:09:12 -04002508
2509/** Size of L1 page table in bytes */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002510#define _HV_L1_SIZE(log2_page_size_large) \
2511 (1 << _HV_LOG2_L1_SIZE(log2_page_size_large))
Chris Metcalf867e3592010-05-28 23:09:12 -04002512
2513/** Log number of HV_PTE entries in level-2 page table */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002514#define _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \
2515 (log2_page_size_large - log2_page_size_small)
Chris Metcalf867e3592010-05-28 23:09:12 -04002516
2517/** Number of HV_PTE entries in level-2 page table */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002518#define _HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) \
2519 (1 << _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small))
Chris Metcalf867e3592010-05-28 23:09:12 -04002520
2521/** Log size of level-2 page table in bytes */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002522#define _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small) \
2523 (HV_LOG2_PTE_SIZE + \
2524 _HV_LOG2_L2_ENTRIES(log2_page_size_large, log2_page_size_small))
Chris Metcalf867e3592010-05-28 23:09:12 -04002525
2526/** Size of level-2 page table in bytes */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002527#define _HV_L2_SIZE(log2_page_size_large, log2_page_size_small) \
2528 (1 << _HV_LOG2_L2_SIZE(log2_page_size_large, log2_page_size_small))
Chris Metcalf867e3592010-05-28 23:09:12 -04002529
2530#ifdef __ASSEMBLER__
2531
2532#if CHIP_VA_WIDTH() > 32
2533
2534/** Index in L1 for a specific VA */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002535#define _HV_L1_INDEX(va, log2_page_size_large) \
2536 (((va) >> log2_page_size_large) & (_HV_L1_ENTRIES(log2_page_size_large) - 1))
Chris Metcalf867e3592010-05-28 23:09:12 -04002537
2538#else /* CHIP_VA_WIDTH() > 32 */
2539
2540/** Index in L1 for a specific VA */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002541#define _HV_L1_INDEX(va, log2_page_size_large) \
2542 (((va) >> log2_page_size_large))
Chris Metcalf867e3592010-05-28 23:09:12 -04002543
2544#endif /* CHIP_VA_WIDTH() > 32 */
2545
2546/** Index in level-2 page table for a specific VA */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002547#define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \
2548 (((va) >> log2_page_size_small) & \
2549 (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1))
Chris Metcalf867e3592010-05-28 23:09:12 -04002550
2551#else /* __ASSEMBLER __ */
2552
2553#if CHIP_VA_WIDTH() > 32
2554
2555/** Index in L1 for a specific VA */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002556#define _HV_L1_INDEX(va, log2_page_size_large) \
2557 (((HV_VirtAddr)(va) >> log2_page_size_large) & \
2558 (_HV_L1_ENTRIES(log2_page_size_large) - 1))
Chris Metcalf867e3592010-05-28 23:09:12 -04002559
2560#else /* CHIP_VA_WIDTH() > 32 */
2561
2562/** Index in L1 for a specific VA */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002563#define _HV_L1_INDEX(va, log2_page_size_large) \
2564 (((HV_VirtAddr)(va) >> log2_page_size_large))
Chris Metcalf867e3592010-05-28 23:09:12 -04002565
2566#endif /* CHIP_VA_WIDTH() > 32 */
2567
2568/** Index in level-2 page table for a specific VA */
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002569#define _HV_L2_INDEX(va, log2_page_size_large, log2_page_size_small) \
2570 (((HV_VirtAddr)(va) >> log2_page_size_small) & \
2571 (_HV_L2_ENTRIES(log2_page_size_large, log2_page_size_small) - 1))
Chris Metcalf867e3592010-05-28 23:09:12 -04002572
2573#endif /* __ASSEMBLER __ */
2574
Chris Metcalfd5d14ed2012-03-29 13:58:43 -04002575/** Position of the PFN field within the PTE (subset of the PTFN). */
2576#define _HV_PTE_INDEX_PFN(log2_page_size) \
2577 (HV_PTE_INDEX_PTFN + (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2578
2579/** Length of the PFN field within the PTE (subset of the PTFN). */
2580#define _HV_PTE_INDEX_PFN_BITS(log2_page_size) \
2581 (HV_PTE_INDEX_PTFN_BITS - (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2582
2583/** Converts a client physical address to a pfn. */
2584#define _HV_CPA_TO_PFN(p, log2_page_size) ((p) >> log2_page_size)
2585
2586/** Converts a pfn to a client physical address. */
2587#define _HV_PFN_TO_CPA(p, log2_page_size) \
2588 (((HV_PhysAddr)(p)) << log2_page_size)
2589
2590/** Converts a ptfn to a pfn. */
2591#define _HV_PTFN_TO_PFN(p, log2_page_size) \
2592 ((p) >> (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2593
2594/** Converts a pfn to a ptfn. */
2595#define _HV_PFN_TO_PTFN(p, log2_page_size) \
2596 ((p) << (log2_page_size - HV_LOG2_PAGE_TABLE_ALIGN))
2597
2598#endif /* _HV_HV_H */