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Andreas Herrmann512d1022011-05-25 20:43:31 +02001/*
2 * fam15h_power.c - AMD Family 15h processor power monitoring
3 *
4 * Copyright (c) 2011 Advanced Micro Devices, Inc.
Andreas Herrmannd034fbf2012-10-29 18:50:47 +01005 * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
Andreas Herrmann512d1022011-05-25 20:43:31 +02006 *
7 *
8 * This driver is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This driver is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/err.h>
22#include <linux/hwmon.h>
23#include <linux/hwmon-sysfs.h>
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/bitops.h>
28#include <asm/processor.h>
Huang Rui3b5ea472015-10-30 17:56:57 +080029#include <asm/msr.h>
Andreas Herrmann512d1022011-05-25 20:43:31 +020030
31MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
Andreas Herrmannd034fbf2012-10-29 18:50:47 +010032MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
Andreas Herrmann512d1022011-05-25 20:43:31 +020033MODULE_LICENSE("GPL");
34
35/* D18F3 */
36#define REG_NORTHBRIDGE_CAP 0xe8
37
38/* D18F4 */
39#define REG_PROCESSOR_TDP 0x1b8
40
41/* D18F5 */
42#define REG_TDP_RUNNING_AVERAGE 0xe0
43#define REG_TDP_LIMIT3 0xe8
44
Huang Rui7deb14b2015-10-30 17:56:55 +080045#define FAM15H_MIN_NUM_ATTRS 2
46#define FAM15H_NUM_GROUPS 2
47
Huang Rui3b5ea472015-10-30 17:56:57 +080048#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
49
Huang Ruieff2a942015-12-10 11:56:10 +080050#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
51
Andreas Herrmann512d1022011-05-25 20:43:31 +020052struct fam15h_power_data {
Axel Lin562dc972014-06-19 23:29:11 +080053 struct pci_dev *pdev;
Andreas Herrmann512d1022011-05-25 20:43:31 +020054 unsigned int tdp_to_watts;
55 unsigned int base_tdp;
56 unsigned int processor_pwr_watts;
Huang Rui1ed32162015-08-27 16:07:38 +080057 unsigned int cpu_pwr_sample_ratio;
Huang Rui7deb14b2015-10-30 17:56:55 +080058 const struct attribute_group *groups[FAM15H_NUM_GROUPS];
59 struct attribute_group group;
Huang Rui3b5ea472015-10-30 17:56:57 +080060 /* maximum accumulated power of a compute unit */
61 u64 max_cu_acc_power;
Andreas Herrmann512d1022011-05-25 20:43:31 +020062};
63
64static ssize_t show_power(struct device *dev,
65 struct device_attribute *attr, char *buf)
66{
67 u32 val, tdp_limit, running_avg_range;
68 s32 running_avg_capture;
69 u64 curr_pwr_watts;
Andreas Herrmann512d1022011-05-25 20:43:31 +020070 struct fam15h_power_data *data = dev_get_drvdata(dev);
Axel Lin562dc972014-06-19 23:29:11 +080071 struct pci_dev *f4 = data->pdev;
Andreas Herrmann512d1022011-05-25 20:43:31 +020072
73 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
74 REG_TDP_RUNNING_AVERAGE, &val);
Huang Ruie9cd4d552015-08-27 16:07:35 +080075
76 /*
77 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
78 * is extended to 4:31 from 4:25.
79 */
80 if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60) {
81 running_avg_capture = val >> 4;
82 running_avg_capture = sign_extend32(running_avg_capture, 27);
83 } else {
84 running_avg_capture = (val >> 4) & 0x3fffff;
85 running_avg_capture = sign_extend32(running_avg_capture, 21);
86 }
87
Andre Przywara941a9562012-03-23 10:02:17 +010088 running_avg_range = (val & 0xf) + 1;
Andreas Herrmann512d1022011-05-25 20:43:31 +020089
90 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
91 REG_TDP_LIMIT3, &val);
92
Gioh Kim60dee3c2016-01-27 12:02:09 +010093 /*
94 * On Carrizo and later platforms, ApmTdpLimit bit field
95 * is extended to 16:31 from 16:28.
96 */
97 if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60)
98 tdp_limit = val >> 16;
99 else
100 tdp_limit = (val >> 16) & 0x1fff;
101
Guenter Roeck62867d42012-06-21 06:26:12 -0700102 curr_pwr_watts = ((u64)(tdp_limit +
103 data->base_tdp)) << running_avg_range;
Andre Przywara941a9562012-03-23 10:02:17 +0100104 curr_pwr_watts -= running_avg_capture;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200105 curr_pwr_watts *= data->tdp_to_watts;
106
107 /*
108 * Convert to microWatt
109 *
110 * power is in Watt provided as fixed point integer with
111 * scaling factor 1/(2^16). For conversion we use
112 * (10^6)/(2^16) = 15625/(2^10)
113 */
Andre Przywara941a9562012-03-23 10:02:17 +0100114 curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
Andreas Herrmann512d1022011-05-25 20:43:31 +0200115 return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
116}
117static DEVICE_ATTR(power1_input, S_IRUGO, show_power, NULL);
118
119static ssize_t show_power_crit(struct device *dev,
120 struct device_attribute *attr, char *buf)
121{
122 struct fam15h_power_data *data = dev_get_drvdata(dev);
123
124 return sprintf(buf, "%u\n", data->processor_pwr_watts);
125}
126static DEVICE_ATTR(power1_crit, S_IRUGO, show_power_crit, NULL);
127
Huang Rui7deb14b2015-10-30 17:56:55 +0800128static int fam15h_power_init_attrs(struct pci_dev *pdev,
129 struct fam15h_power_data *data)
Aravind Gopalakrishnan961a2372014-09-16 14:58:04 -0500130{
Huang Rui7deb14b2015-10-30 17:56:55 +0800131 int n = FAM15H_MIN_NUM_ATTRS;
132 struct attribute **fam15h_power_attrs;
Huang Rui46f29c22015-10-30 17:56:56 +0800133 struct cpuinfo_x86 *c = &boot_cpu_data;
Aravind Gopalakrishnan961a2372014-09-16 14:58:04 -0500134
Huang Rui46f29c22015-10-30 17:56:56 +0800135 if (c->x86 == 0x15 &&
136 (c->x86_model <= 0xf ||
Huang Ruieff2a942015-12-10 11:56:10 +0800137 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
Huang Rui7deb14b2015-10-30 17:56:55 +0800138 n += 1;
139
140 fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
141 sizeof(*fam15h_power_attrs),
142 GFP_KERNEL);
143
144 if (!fam15h_power_attrs)
145 return -ENOMEM;
146
147 n = 0;
148 fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
Huang Rui46f29c22015-10-30 17:56:56 +0800149 if (c->x86 == 0x15 &&
150 (c->x86_model <= 0xf ||
Huang Ruieff2a942015-12-10 11:56:10 +0800151 (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
Huang Rui7deb14b2015-10-30 17:56:55 +0800152 fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
153
154 data->group.attrs = fam15h_power_attrs;
155
156 return 0;
Aravind Gopalakrishnan961a2372014-09-16 14:58:04 -0500157}
158
Huang Ruid83e92b2015-08-27 16:07:33 +0800159static bool should_load_on_this_node(struct pci_dev *f4)
Andreas Herrmann512d1022011-05-25 20:43:31 +0200160{
161 u32 val;
162
163 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
164 REG_NORTHBRIDGE_CAP, &val);
165 if ((val & BIT(29)) && ((val >> 30) & 3))
166 return false;
167
168 return true;
169}
170
Andre Przywara00250ec2012-04-09 18:16:34 -0400171/*
172 * Newer BKDG versions have an updated recommendation on how to properly
173 * initialize the running average range (was: 0xE, now: 0x9). This avoids
174 * counter saturations resulting in bogus power readings.
175 * We correct this value ourselves to cope with older BIOSes.
176 */
Andreas Herrmann5f0ecb92012-09-23 20:27:32 +0200177static const struct pci_device_id affected_device[] = {
Guenter Roeckc3e40a92012-04-25 13:44:20 -0700178 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
179 { 0 }
180};
181
Andreas Herrmann5f0ecb92012-09-23 20:27:32 +0200182static void tweak_runavg_range(struct pci_dev *pdev)
Andre Przywara00250ec2012-04-09 18:16:34 -0400183{
184 u32 val;
Andre Przywara00250ec2012-04-09 18:16:34 -0400185
186 /*
187 * let this quirk apply only to the current version of the
188 * northbridge, since future versions may change the behavior
189 */
Guenter Roeckc3e40a92012-04-25 13:44:20 -0700190 if (!pci_match_id(affected_device, pdev))
Andre Przywara00250ec2012-04-09 18:16:34 -0400191 return;
192
193 pci_bus_read_config_dword(pdev->bus,
194 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
195 REG_TDP_RUNNING_AVERAGE, &val);
196 if ((val & 0xf) != 0xe)
197 return;
198
199 val &= ~0xf;
200 val |= 0x9;
201 pci_bus_write_config_dword(pdev->bus,
202 PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
203 REG_TDP_RUNNING_AVERAGE, val);
204}
205
Andreas Herrmann5f0ecb92012-09-23 20:27:32 +0200206#ifdef CONFIG_PM
207static int fam15h_power_resume(struct pci_dev *pdev)
208{
209 tweak_runavg_range(pdev);
210 return 0;
211}
212#else
213#define fam15h_power_resume NULL
214#endif
215
Huang Rui7deb14b2015-10-30 17:56:55 +0800216static int fam15h_power_init_data(struct pci_dev *f4,
217 struct fam15h_power_data *data)
Andreas Herrmann512d1022011-05-25 20:43:31 +0200218{
Huang Rui1ed32162015-08-27 16:07:38 +0800219 u32 val, eax, ebx, ecx, edx;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200220 u64 tmp;
Huang Rui7deb14b2015-10-30 17:56:55 +0800221 int ret;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200222
223 pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
224 data->base_tdp = val >> 16;
225 tmp = val & 0xffff;
226
227 pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
228 REG_TDP_LIMIT3, &val);
229
230 data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
231 tmp *= data->tdp_to_watts;
232
233 /* result not allowed to be >= 256W */
234 if ((tmp >> 16) >= 256)
Guenter Roeckb55f3752013-01-10 10:01:24 -0800235 dev_warn(&f4->dev,
236 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
Andreas Herrmann512d1022011-05-25 20:43:31 +0200237 (unsigned int) (tmp >> 16));
238
239 /* convert to microWatt */
240 data->processor_pwr_watts = (tmp * 15625) >> 10;
Huang Rui1ed32162015-08-27 16:07:38 +0800241
Huang Rui7deb14b2015-10-30 17:56:55 +0800242 ret = fam15h_power_init_attrs(f4, data);
243 if (ret)
244 return ret;
245
Huang Rui1ed32162015-08-27 16:07:38 +0800246 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
247
248 /* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
249 if (!(edx & BIT(12)))
Huang Rui7deb14b2015-10-30 17:56:55 +0800250 return 0;
Huang Rui1ed32162015-08-27 16:07:38 +0800251
252 /*
253 * determine the ratio of the compute unit power accumulator
254 * sample period to the PTSC counter period by executing CPUID
255 * Fn8000_0007:ECX
256 */
257 data->cpu_pwr_sample_ratio = ecx;
Huang Rui7deb14b2015-10-30 17:56:55 +0800258
Huang Rui3b5ea472015-10-30 17:56:57 +0800259 if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
260 pr_err("Failed to read max compute unit power accumulator MSR\n");
261 return -ENODEV;
262 }
263
264 data->max_cu_acc_power = tmp;
265
Huang Rui7deb14b2015-10-30 17:56:55 +0800266 return 0;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200267}
268
Bill Pemberton6c931ae2012-11-19 13:22:35 -0500269static int fam15h_power_probe(struct pci_dev *pdev,
Huang Rui7deb14b2015-10-30 17:56:55 +0800270 const struct pci_device_id *id)
Andreas Herrmann512d1022011-05-25 20:43:31 +0200271{
272 struct fam15h_power_data *data;
Guenter Roeck87432a22012-06-02 09:58:06 -0700273 struct device *dev = &pdev->dev;
Axel Lin562dc972014-06-19 23:29:11 +0800274 struct device *hwmon_dev;
Huang Rui7deb14b2015-10-30 17:56:55 +0800275 int ret;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200276
Andre Przywara00250ec2012-04-09 18:16:34 -0400277 /*
278 * though we ignore every other northbridge, we still have to
279 * do the tweaking on _each_ node in MCM processors as the counters
280 * are working hand-in-hand
281 */
282 tweak_runavg_range(pdev);
283
Huang Ruid83e92b2015-08-27 16:07:33 +0800284 if (!should_load_on_this_node(pdev))
Guenter Roeck87432a22012-06-02 09:58:06 -0700285 return -ENODEV;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200286
Guenter Roeck87432a22012-06-02 09:58:06 -0700287 data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
288 if (!data)
289 return -ENOMEM;
290
Huang Rui7deb14b2015-10-30 17:56:55 +0800291 ret = fam15h_power_init_data(pdev, data);
292 if (ret)
293 return ret;
294
Axel Lin562dc972014-06-19 23:29:11 +0800295 data->pdev = pdev;
Andreas Herrmann512d1022011-05-25 20:43:31 +0200296
Huang Rui7deb14b2015-10-30 17:56:55 +0800297 data->groups[0] = &data->group;
298
Axel Lin562dc972014-06-19 23:29:11 +0800299 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
300 data,
Huang Rui7deb14b2015-10-30 17:56:55 +0800301 &data->groups[0]);
Axel Lin562dc972014-06-19 23:29:11 +0800302 return PTR_ERR_OR_ZERO(hwmon_dev);
Andreas Herrmann512d1022011-05-25 20:43:31 +0200303}
304
Jingoo Hancd9bb052013-12-03 07:10:29 +0000305static const struct pci_device_id fam15h_power_id_table[] = {
Andreas Herrmann512d1022011-05-25 20:43:31 +0200306 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
Aravind Gopalakrishnan0a0039a2014-09-16 14:58:16 -0500307 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
Huang Rui5dc08722015-08-27 16:07:32 +0800308 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
Huang Ruieff2a942015-12-10 11:56:10 +0800309 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
Boris Ostrovsky22e32f42012-12-05 06:12:42 -0500310 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
Aravind Gopalakrishnan0bd52942014-11-04 11:49:02 -0600311 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
Andreas Herrmann512d1022011-05-25 20:43:31 +0200312 {}
313};
314MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
315
316static struct pci_driver fam15h_power_driver = {
317 .name = "fam15h_power",
318 .id_table = fam15h_power_id_table,
319 .probe = fam15h_power_probe,
Andreas Herrmann5f0ecb92012-09-23 20:27:32 +0200320 .resume = fam15h_power_resume,
Andreas Herrmann512d1022011-05-25 20:43:31 +0200321};
322
Axel Linf71f5a52012-04-02 21:25:46 -0400323module_pci_driver(fam15h_power_driver);