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Daniel Vetterff7cdd62010-04-14 00:29:51 +02001/*
2 * Common Intel AGPGART and GTT definitions.
3 */
Zhenyu Wang93f5f7f2010-08-27 11:06:48 +08004#ifndef _INTEL_AGP_H
5#define _INTEL_AGP_H
Daniel Vetterff7cdd62010-04-14 00:29:51 +02006
7/* Intel registers */
8#define INTEL_APSIZE 0xb4
9#define INTEL_ATTBASE 0xb8
10#define INTEL_AGPCTRL 0xb0
11#define INTEL_NBXCFG 0x50
12#define INTEL_ERRSTS 0x91
13
14/* Intel i830 registers */
15#define I830_GMCH_CTRL 0x52
16#define I830_GMCH_ENABLED 0x4
17#define I830_GMCH_MEM_MASK 0x1
18#define I830_GMCH_MEM_64M 0x1
19#define I830_GMCH_MEM_128M 0
20#define I830_GMCH_GMS_MASK 0x70
21#define I830_GMCH_GMS_DISABLED 0x00
22#define I830_GMCH_GMS_LOCAL 0x10
23#define I830_GMCH_GMS_STOLEN_512 0x20
24#define I830_GMCH_GMS_STOLEN_1024 0x30
25#define I830_GMCH_GMS_STOLEN_8192 0x40
26#define I830_RDRAM_CHANNEL_TYPE 0x03010
27#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
28#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
29
30/* This one is for I830MP w. an external graphic card */
31#define INTEL_I830_ERRSTS 0x92
32
33/* Intel 855GM/852GM registers */
34#define I855_GMCH_GMS_MASK 0xF0
35#define I855_GMCH_GMS_STOLEN_0M 0x0
36#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
37#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
38#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
39#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
40#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
41#define I85X_CAPID 0x44
42#define I85X_VARIANT_MASK 0x7
43#define I85X_VARIANT_SHIFT 5
44#define I855_GME 0x0
45#define I855_GM 0x4
46#define I852_GME 0x2
47#define I852_GM 0x5
48
49/* Intel i845 registers */
50#define INTEL_I845_AGPM 0x51
51#define INTEL_I845_ERRSTS 0xc8
52
53/* Intel i860 registers */
54#define INTEL_I860_MCHCFG 0x50
55#define INTEL_I860_ERRSTS 0xc8
56
57/* Intel i810 registers */
Yinghai Lu545b0a72014-01-03 18:28:06 -070058#define I810_GMADR_BAR 0
Bjorn Helgaas5ef6d8f42014-01-03 18:28:31 -070059#define I810_MMADR_BAR 1
Daniel Vetterff7cdd62010-04-14 00:29:51 +020060#define I810_PTE_BASE 0x10000
61#define I810_PTE_MAIN_UNCACHED 0x00000000
62#define I810_PTE_LOCAL 0x00000002
63#define I810_PTE_VALID 0x00000001
64#define I830_PTE_SYSTEM_CACHED 0x00000006
Zhenyu Wanga2757b62010-07-09 10:45:17 -070065
Daniel Vetterff7cdd62010-04-14 00:29:51 +020066#define I810_SMRAM_MISCC 0x70
67#define I810_GFX_MEM_WIN_SIZE 0x00010000
68#define I810_GFX_MEM_WIN_32M 0x00010000
69#define I810_GMS 0x000000c0
70#define I810_GMS_DISABLE 0x00000000
71#define I810_PGETBL_CTL 0x2020
72#define I810_PGETBL_ENABLED 0x00000001
Daniel Vetter20172842010-09-24 18:25:59 +020073/* Note: PGETBL_CTL2 has a different offset on G33. */
74#define I965_PGETBL_CTL2 0x20c4
Daniel Vetterff7cdd62010-04-14 00:29:51 +020075#define I965_PGETBL_SIZE_MASK 0x0000000e
76#define I965_PGETBL_SIZE_512KB (0 << 1)
77#define I965_PGETBL_SIZE_256KB (1 << 1)
78#define I965_PGETBL_SIZE_128KB (2 << 1)
79#define I965_PGETBL_SIZE_1MB (3 << 1)
80#define I965_PGETBL_SIZE_2MB (4 << 1)
81#define I965_PGETBL_SIZE_1_5MB (5 << 1)
Daniel Vetter20172842010-09-24 18:25:59 +020082#define G33_GMCH_SIZE_MASK (3 << 8)
83#define G33_GMCH_SIZE_1M (1 << 8)
84#define G33_GMCH_SIZE_2M (2 << 8)
85#define G4x_GMCH_SIZE_MASK (0xf << 8)
86#define G4x_GMCH_SIZE_1M (0x1 << 8)
87#define G4x_GMCH_SIZE_2M (0x3 << 8)
Chris Wilson780d7cc2011-07-12 23:38:18 +010088#define G4x_GMCH_SIZE_VT_EN (0x8 << 8)
89#define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN)
90#define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN)
91#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
Daniel Vetterff7cdd62010-04-14 00:29:51 +020092
Chris Wilsonc97689d2010-12-23 10:40:38 +000093#define GFX_FLSH_CNTL 0x2170 /* 915+ */
94
Daniel Vetterff7cdd62010-04-14 00:29:51 +020095#define I810_DRAM_CTL 0x3000
96#define I810_DRAM_ROW_0 0x00000001
97#define I810_DRAM_ROW_0_SDRAM 0x00000001
98
99/* Intel 815 register */
100#define INTEL_815_APCONT 0x51
101#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
102
103/* Intel i820 registers */
104#define INTEL_I820_RDCR 0x51
105#define INTEL_I820_ERRSTS 0xc8
106
107/* Intel i840 registers */
108#define INTEL_I840_MCHCFG 0x50
109#define INTEL_I840_ERRSTS 0xc8
110
111/* Intel i850 registers */
112#define INTEL_I850_MCHCFG 0x50
113#define INTEL_I850_ERRSTS 0xc8
114
115/* intel 915G registers */
Yinghai Lu545b0a72014-01-03 18:28:06 -0700116#define I915_GMADR_BAR 2
Bjorn Helgaas5ef6d8f42014-01-03 18:28:31 -0700117#define I915_MMADR_BAR 0
Bjorn Helgaasb5e350f2014-01-03 18:29:00 -0700118#define I915_PTE_BAR 3
Daniel Vetterff7cdd62010-04-14 00:29:51 +0200119#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
120#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
121#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
122#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
123#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
124#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
125#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
126#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
127
128#define I915_IFPADDR 0x60
Chris Wilsonbdb8b972010-12-22 11:37:09 +0000129#define I830_HIC 0x70
Daniel Vetterff7cdd62010-04-14 00:29:51 +0200130
131/* Intel 965G registers */
132#define I965_MSAC 0x62
133#define I965_IFPADDR 0x70
134
135/* Intel 7505 registers */
136#define INTEL_I7505_APSIZE 0x74
137#define INTEL_I7505_NCAPID 0x60
138#define INTEL_I7505_NISTAT 0x6c
139#define INTEL_I7505_ATTBASE 0x78
140#define INTEL_I7505_ERRSTS 0x42
141#define INTEL_I7505_AGPCTRL 0x70
142#define INTEL_I7505_MCHCFG 0x50
143
Daniel Vetterff7cdd62010-04-14 00:29:51 +0200144/* pci devices ids */
145#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
146#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
147#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
148#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
149#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
150#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
151#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
152#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
153#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
154#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
155#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
156#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
157#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
158#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
159#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
160#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
161#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
162#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
163#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
164#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
165#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
166#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
167#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
168#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
169#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
170#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
171#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
172#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
Chris Wilson41a51422010-09-17 08:22:30 +0100173#define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90
174#define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92
Daniel Vetterff7cdd62010-04-14 00:29:51 +0200175#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
176#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
177#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
178#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
179#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
180#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
181#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
182#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
183#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
184#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
185#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
Eugeni Dodonov67384fe2012-06-06 11:59:06 -0300186#define PCI_DEVICE_ID_INTEL_IRONLAKE_D2_HB 0x0069
Daniel Vetterff7cdd62010-04-14 00:29:51 +0200187#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
188#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
189#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
190#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
191#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
Daniel Vetterff7cdd62010-04-14 00:29:51 +0200192
Zhenyu Wang93f5f7f2010-08-27 11:06:48 +0800193#endif