Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
Uwe Zeisberger | f30c226 | 2006-10-03 23:01:26 +0200 | [diff] [blame] | 2 | * arch/arm/mach-omap2/serial.c |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * OMAP2 serial support. |
| 5 | * |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 6 | * Copyright (C) 2005-2008 Nokia Corporation |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 7 | * Author: Paul Mundt <paul.mundt@nokia.com> |
| 8 | * |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 9 | * Major rework for PM support by Kevin Hilman |
| 10 | * |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 11 | * Based off of arch/arm/mach-omap/omap1/serial.c |
| 12 | * |
Santosh Shilimkar | 4416907 | 2009-05-28 14:16:04 -0700 | [diff] [blame] | 13 | * Copyright (C) 2009 Texas Instruments |
| 14 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com |
| 15 | * |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 16 | * This file is subject to the terms and conditions of the GNU General Public |
| 17 | * License. See the file "COPYING" in the main directory of this archive |
| 18 | * for more details. |
| 19 | */ |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/init.h> |
| 22 | #include <linux/serial_8250.h> |
| 23 | #include <linux/serial_reg.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 24 | #include <linux/clk.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 26 | #include <linux/delay.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 27 | |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 28 | #include <plat/common.h> |
| 29 | #include <plat/board.h> |
| 30 | #include <plat/clock.h> |
| 31 | #include <plat/control.h> |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 32 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 33 | #include "prm.h" |
| 34 | #include "pm.h" |
| 35 | #include "prm-regbits-34xx.h" |
| 36 | |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 37 | #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52 |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 38 | #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
| 39 | |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 40 | #define UART_ERRATA_FIFO_FULL_ABORT (0x1 << 0) |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 41 | #define UART_ERRATA_i202_MDR1_ACCESS (0x1 << 1) |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 42 | |
Tony Lindgren | 301fe8e | 2010-02-01 12:34:31 -0800 | [diff] [blame] | 43 | /* |
| 44 | * NOTE: By default the serial timeout is disabled as it causes lost characters |
| 45 | * over the serial ports. This means that the UART clocks will stay on until |
| 46 | * disabled via sysfs. This also causes that any deeper omap sleep states are |
| 47 | * blocked. |
| 48 | */ |
| 49 | #define DEFAULT_TIMEOUT 0 |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 50 | |
| 51 | struct omap_uart_state { |
| 52 | int num; |
| 53 | int can_sleep; |
| 54 | struct timer_list timer; |
| 55 | u32 timeout; |
| 56 | |
| 57 | void __iomem *wk_st; |
| 58 | void __iomem *wk_en; |
| 59 | u32 wk_mask; |
| 60 | u32 padconf; |
| 61 | |
| 62 | struct clk *ick; |
| 63 | struct clk *fck; |
| 64 | int clocked; |
| 65 | |
| 66 | struct plat_serial8250_port *p; |
| 67 | struct list_head node; |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 68 | struct platform_device pdev; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 69 | |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 70 | u32 errata; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 71 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
| 72 | int context_valid; |
| 73 | |
| 74 | /* Registers to be saved/restored for OFF-mode */ |
| 75 | u16 dll; |
| 76 | u16 dlh; |
| 77 | u16 ier; |
| 78 | u16 sysc; |
| 79 | u16 scr; |
| 80 | u16 wer; |
Govindraj R | 5ade4ff | 2010-08-02 13:18:11 +0300 | [diff] [blame] | 81 | u16 mcr; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 82 | #endif |
| 83 | }; |
| 84 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 85 | static LIST_HEAD(uart_list); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 86 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 87 | static struct plat_serial8250_port serial_platform_data0[] = { |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 88 | { |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 89 | .irq = 72, |
| 90 | .flags = UPF_BOOT_AUTOCONF, |
| 91 | .iotype = UPIO_MEM, |
| 92 | .regshift = 2, |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 93 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 94 | }, { |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 95 | .flags = 0 |
| 96 | } |
| 97 | }; |
| 98 | |
| 99 | static struct plat_serial8250_port serial_platform_data1[] = { |
| 100 | { |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 101 | .irq = 73, |
| 102 | .flags = UPF_BOOT_AUTOCONF, |
| 103 | .iotype = UPIO_MEM, |
| 104 | .regshift = 2, |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 105 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 106 | }, { |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 107 | .flags = 0 |
| 108 | } |
| 109 | }; |
| 110 | |
| 111 | static struct plat_serial8250_port serial_platform_data2[] = { |
| 112 | { |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 113 | .irq = 74, |
| 114 | .flags = UPF_BOOT_AUTOCONF, |
| 115 | .iotype = UPIO_MEM, |
| 116 | .regshift = 2, |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 117 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 118 | }, { |
| 119 | .flags = 0 |
| 120 | } |
| 121 | }; |
| 122 | |
Santosh Shilimkar | 0e3eaad | 2009-08-22 13:30:11 +0530 | [diff] [blame] | 123 | static struct plat_serial8250_port serial_platform_data3[] = { |
| 124 | { |
Santosh Shilimkar | 0e3eaad | 2009-08-22 13:30:11 +0530 | [diff] [blame] | 125 | .irq = 70, |
| 126 | .flags = UPF_BOOT_AUTOCONF, |
| 127 | .iotype = UPIO_MEM, |
| 128 | .regshift = 2, |
| 129 | .uartclk = OMAP24XX_BASE_BAUD * 16, |
| 130 | }, { |
| 131 | .flags = 0 |
| 132 | } |
| 133 | }; |
Tony Lindgren | a3a9b36 | 2010-02-15 09:27:25 -0800 | [diff] [blame] | 134 | |
Tony Lindgren | 4f2c49f | 2010-02-15 08:48:53 -0800 | [diff] [blame] | 135 | void __init omap2_set_globals_uart(struct omap_globals *omap2_globals) |
| 136 | { |
| 137 | serial_platform_data0[0].mapbase = omap2_globals->uart1_phys; |
| 138 | serial_platform_data1[0].mapbase = omap2_globals->uart2_phys; |
| 139 | serial_platform_data2[0].mapbase = omap2_globals->uart3_phys; |
Sergio Aguirre | 4b1bbd3 | 2010-02-26 19:58:47 -0600 | [diff] [blame] | 140 | serial_platform_data3[0].mapbase = omap2_globals->uart4_phys; |
Tony Lindgren | 4f2c49f | 2010-02-15 08:48:53 -0800 | [diff] [blame] | 141 | } |
| 142 | |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 143 | static inline unsigned int __serial_read_reg(struct uart_port *up, |
| 144 | int offset) |
| 145 | { |
| 146 | offset <<= up->regshift; |
| 147 | return (unsigned int)__raw_readb(up->membase + offset); |
| 148 | } |
| 149 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 150 | static inline unsigned int serial_read_reg(struct plat_serial8250_port *up, |
| 151 | int offset) |
| 152 | { |
| 153 | offset <<= up->regshift; |
| 154 | return (unsigned int)__raw_readb(up->membase + offset); |
| 155 | } |
| 156 | |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 157 | static inline void __serial_write_reg(struct uart_port *up, int offset, |
| 158 | int value) |
| 159 | { |
| 160 | offset <<= up->regshift; |
| 161 | __raw_writeb(value, up->membase + offset); |
| 162 | } |
| 163 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 164 | static inline void serial_write_reg(struct plat_serial8250_port *p, int offset, |
| 165 | int value) |
| 166 | { |
| 167 | offset <<= p->regshift; |
Russell King | e8a91c9 | 2008-09-01 22:07:37 +0100 | [diff] [blame] | 168 | __raw_writeb(value, p->membase + offset); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | /* |
| 172 | * Internal UARTs need to be initialized for the 8250 autoconfig to work |
| 173 | * properly. Note that the TX watermark initialization may not be needed |
| 174 | * once the 8250.c watermark handling code is merged. |
| 175 | */ |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 176 | static inline void __init omap_uart_reset(struct omap_uart_state *uart) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 177 | { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 178 | struct plat_serial8250_port *p = uart->p; |
| 179 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 180 | serial_write_reg(p, UART_OMAP_MDR1, 0x07); |
| 181 | serial_write_reg(p, UART_OMAP_SCR, 0x08); |
| 182 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); |
Juha Yrjola | 671c723 | 2006-12-06 17:13:49 -0800 | [diff] [blame] | 183 | serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 184 | } |
| 185 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 186 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) |
| 187 | |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 188 | /* |
| 189 | * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6) |
| 190 | * The access to uart register after MDR1 Access |
| 191 | * causes UART to corrupt data. |
| 192 | * |
| 193 | * Need a delay = |
| 194 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) |
| 195 | * give 10 times as much |
| 196 | */ |
| 197 | static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val, |
| 198 | u8 fcr_val) |
| 199 | { |
| 200 | struct plat_serial8250_port *p = uart->p; |
| 201 | u8 timeout = 255; |
| 202 | |
| 203 | serial_write_reg(p, UART_OMAP_MDR1, mdr1_val); |
| 204 | udelay(2); |
| 205 | serial_write_reg(p, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT | |
| 206 | UART_FCR_CLEAR_RCVR); |
| 207 | /* |
| 208 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and |
| 209 | * TX_FIFO_E bit is 1. |
| 210 | */ |
| 211 | while (UART_LSR_THRE != (serial_read_reg(p, UART_LSR) & |
| 212 | (UART_LSR_THRE | UART_LSR_DR))) { |
| 213 | timeout--; |
| 214 | if (!timeout) { |
| 215 | /* Should *never* happen. we warn and carry on */ |
| 216 | dev_crit(&uart->pdev.dev, "Errata i202: timedout %x\n", |
| 217 | serial_read_reg(p, UART_LSR)); |
| 218 | break; |
| 219 | } |
| 220 | udelay(1); |
| 221 | } |
| 222 | } |
| 223 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 224 | static void omap_uart_save_context(struct omap_uart_state *uart) |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 225 | { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 226 | u16 lcr = 0; |
| 227 | struct plat_serial8250_port *p = uart->p; |
| 228 | |
| 229 | if (!enable_off_mode) |
| 230 | return; |
| 231 | |
| 232 | lcr = serial_read_reg(p, UART_LCR); |
| 233 | serial_write_reg(p, UART_LCR, 0xBF); |
| 234 | uart->dll = serial_read_reg(p, UART_DLL); |
| 235 | uart->dlh = serial_read_reg(p, UART_DLM); |
| 236 | serial_write_reg(p, UART_LCR, lcr); |
| 237 | uart->ier = serial_read_reg(p, UART_IER); |
| 238 | uart->sysc = serial_read_reg(p, UART_OMAP_SYSC); |
| 239 | uart->scr = serial_read_reg(p, UART_OMAP_SCR); |
| 240 | uart->wer = serial_read_reg(p, UART_OMAP_WER); |
Govindraj R | 5ade4ff | 2010-08-02 13:18:11 +0300 | [diff] [blame] | 241 | serial_write_reg(p, UART_LCR, 0x80); |
| 242 | uart->mcr = serial_read_reg(p, UART_MCR); |
| 243 | serial_write_reg(p, UART_LCR, lcr); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 244 | |
| 245 | uart->context_valid = 1; |
| 246 | } |
| 247 | |
| 248 | static void omap_uart_restore_context(struct omap_uart_state *uart) |
| 249 | { |
| 250 | u16 efr = 0; |
| 251 | struct plat_serial8250_port *p = uart->p; |
| 252 | |
| 253 | if (!enable_off_mode) |
| 254 | return; |
| 255 | |
| 256 | if (!uart->context_valid) |
| 257 | return; |
| 258 | |
| 259 | uart->context_valid = 0; |
| 260 | |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 261 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
| 262 | omap_uart_mdr1_errataset(uart, 0x07, 0xA0); |
| 263 | else |
| 264 | serial_write_reg(p, UART_OMAP_MDR1, 0x7); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 265 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ |
| 266 | efr = serial_read_reg(p, UART_EFR); |
| 267 | serial_write_reg(p, UART_EFR, UART_EFR_ECB); |
| 268 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ |
| 269 | serial_write_reg(p, UART_IER, 0x0); |
| 270 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ |
| 271 | serial_write_reg(p, UART_DLL, uart->dll); |
| 272 | serial_write_reg(p, UART_DLM, uart->dlh); |
| 273 | serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */ |
| 274 | serial_write_reg(p, UART_IER, uart->ier); |
Govindraj R | 5ade4ff | 2010-08-02 13:18:11 +0300 | [diff] [blame] | 275 | serial_write_reg(p, UART_LCR, 0x80); |
| 276 | serial_write_reg(p, UART_MCR, uart->mcr); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 277 | serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */ |
| 278 | serial_write_reg(p, UART_EFR, efr); |
| 279 | serial_write_reg(p, UART_LCR, UART_LCR_WLEN8); |
| 280 | serial_write_reg(p, UART_OMAP_SCR, uart->scr); |
| 281 | serial_write_reg(p, UART_OMAP_WER, uart->wer); |
| 282 | serial_write_reg(p, UART_OMAP_SYSC, uart->sysc); |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 283 | if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) |
| 284 | omap_uart_mdr1_errataset(uart, 0x00, 0xA1); |
| 285 | else |
| 286 | serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */ |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 287 | } |
| 288 | #else |
| 289 | static inline void omap_uart_save_context(struct omap_uart_state *uart) {} |
| 290 | static inline void omap_uart_restore_context(struct omap_uart_state *uart) {} |
| 291 | #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */ |
| 292 | |
| 293 | static inline void omap_uart_enable_clocks(struct omap_uart_state *uart) |
| 294 | { |
| 295 | if (uart->clocked) |
| 296 | return; |
| 297 | |
| 298 | clk_enable(uart->ick); |
| 299 | clk_enable(uart->fck); |
| 300 | uart->clocked = 1; |
| 301 | omap_uart_restore_context(uart); |
| 302 | } |
| 303 | |
| 304 | #ifdef CONFIG_PM |
| 305 | |
| 306 | static inline void omap_uart_disable_clocks(struct omap_uart_state *uart) |
| 307 | { |
| 308 | if (!uart->clocked) |
| 309 | return; |
| 310 | |
| 311 | omap_uart_save_context(uart); |
| 312 | uart->clocked = 0; |
| 313 | clk_disable(uart->ick); |
| 314 | clk_disable(uart->fck); |
| 315 | } |
| 316 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 317 | static void omap_uart_enable_wakeup(struct omap_uart_state *uart) |
| 318 | { |
| 319 | /* Set wake-enable bit */ |
| 320 | if (uart->wk_en && uart->wk_mask) { |
| 321 | u32 v = __raw_readl(uart->wk_en); |
| 322 | v |= uart->wk_mask; |
| 323 | __raw_writel(v, uart->wk_en); |
| 324 | } |
| 325 | |
| 326 | /* Ensure IOPAD wake-enables are set */ |
| 327 | if (cpu_is_omap34xx() && uart->padconf) { |
| 328 | u16 v = omap_ctrl_readw(uart->padconf); |
| 329 | v |= OMAP3_PADCONF_WAKEUPENABLE0; |
| 330 | omap_ctrl_writew(v, uart->padconf); |
| 331 | } |
| 332 | } |
| 333 | |
| 334 | static void omap_uart_disable_wakeup(struct omap_uart_state *uart) |
| 335 | { |
| 336 | /* Clear wake-enable bit */ |
| 337 | if (uart->wk_en && uart->wk_mask) { |
| 338 | u32 v = __raw_readl(uart->wk_en); |
| 339 | v &= ~uart->wk_mask; |
| 340 | __raw_writel(v, uart->wk_en); |
| 341 | } |
| 342 | |
| 343 | /* Ensure IOPAD wake-enables are cleared */ |
| 344 | if (cpu_is_omap34xx() && uart->padconf) { |
| 345 | u16 v = omap_ctrl_readw(uart->padconf); |
| 346 | v &= ~OMAP3_PADCONF_WAKEUPENABLE0; |
| 347 | omap_ctrl_writew(v, uart->padconf); |
| 348 | } |
| 349 | } |
| 350 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 351 | static void omap_uart_smart_idle_enable(struct omap_uart_state *uart, |
| 352 | int enable) |
| 353 | { |
| 354 | struct plat_serial8250_port *p = uart->p; |
| 355 | u16 sysc; |
| 356 | |
| 357 | sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7; |
| 358 | if (enable) |
| 359 | sysc |= 0x2 << 3; |
| 360 | else |
| 361 | sysc |= 0x1 << 3; |
| 362 | |
| 363 | serial_write_reg(p, UART_OMAP_SYSC, sysc); |
| 364 | } |
| 365 | |
| 366 | static void omap_uart_block_sleep(struct omap_uart_state *uart) |
| 367 | { |
| 368 | omap_uart_enable_clocks(uart); |
| 369 | |
| 370 | omap_uart_smart_idle_enable(uart, 0); |
| 371 | uart->can_sleep = 0; |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 372 | if (uart->timeout) |
| 373 | mod_timer(&uart->timer, jiffies + uart->timeout); |
| 374 | else |
| 375 | del_timer(&uart->timer); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 376 | } |
| 377 | |
| 378 | static void omap_uart_allow_sleep(struct omap_uart_state *uart) |
| 379 | { |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 380 | if (device_may_wakeup(&uart->pdev.dev)) |
| 381 | omap_uart_enable_wakeup(uart); |
| 382 | else |
| 383 | omap_uart_disable_wakeup(uart); |
| 384 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 385 | if (!uart->clocked) |
| 386 | return; |
| 387 | |
| 388 | omap_uart_smart_idle_enable(uart, 1); |
| 389 | uart->can_sleep = 1; |
| 390 | del_timer(&uart->timer); |
| 391 | } |
| 392 | |
| 393 | static void omap_uart_idle_timer(unsigned long data) |
| 394 | { |
| 395 | struct omap_uart_state *uart = (struct omap_uart_state *)data; |
| 396 | |
| 397 | omap_uart_allow_sleep(uart); |
| 398 | } |
| 399 | |
| 400 | void omap_uart_prepare_idle(int num) |
| 401 | { |
| 402 | struct omap_uart_state *uart; |
| 403 | |
| 404 | list_for_each_entry(uart, &uart_list, node) { |
| 405 | if (num == uart->num && uart->can_sleep) { |
| 406 | omap_uart_disable_clocks(uart); |
| 407 | return; |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 408 | } |
| 409 | } |
| 410 | } |
| 411 | |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 412 | void omap_uart_resume_idle(int num) |
| 413 | { |
| 414 | struct omap_uart_state *uart; |
| 415 | |
| 416 | list_for_each_entry(uart, &uart_list, node) { |
| 417 | if (num == uart->num) { |
| 418 | omap_uart_enable_clocks(uart); |
| 419 | |
| 420 | /* Check for IO pad wakeup */ |
| 421 | if (cpu_is_omap34xx() && uart->padconf) { |
| 422 | u16 p = omap_ctrl_readw(uart->padconf); |
| 423 | |
| 424 | if (p & OMAP3_PADCONF_WAKEUPEVENT0) |
| 425 | omap_uart_block_sleep(uart); |
| 426 | } |
| 427 | |
| 428 | /* Check for normal UART wakeup */ |
| 429 | if (__raw_readl(uart->wk_st) & uart->wk_mask) |
| 430 | omap_uart_block_sleep(uart); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 431 | return; |
| 432 | } |
| 433 | } |
| 434 | } |
| 435 | |
| 436 | void omap_uart_prepare_suspend(void) |
| 437 | { |
| 438 | struct omap_uart_state *uart; |
| 439 | |
| 440 | list_for_each_entry(uart, &uart_list, node) { |
| 441 | omap_uart_allow_sleep(uart); |
| 442 | } |
| 443 | } |
| 444 | |
| 445 | int omap_uart_can_sleep(void) |
| 446 | { |
| 447 | struct omap_uart_state *uart; |
| 448 | int can_sleep = 1; |
| 449 | |
| 450 | list_for_each_entry(uart, &uart_list, node) { |
| 451 | if (!uart->clocked) |
| 452 | continue; |
| 453 | |
| 454 | if (!uart->can_sleep) { |
| 455 | can_sleep = 0; |
| 456 | continue; |
| 457 | } |
| 458 | |
| 459 | /* This UART can now safely sleep. */ |
| 460 | omap_uart_allow_sleep(uart); |
| 461 | } |
| 462 | |
| 463 | return can_sleep; |
| 464 | } |
| 465 | |
| 466 | /** |
| 467 | * omap_uart_interrupt() |
| 468 | * |
| 469 | * This handler is used only to detect that *any* UART interrupt has |
| 470 | * occurred. It does _nothing_ to handle the interrupt. Rather, |
| 471 | * any UART interrupt will trigger the inactivity timer so the |
| 472 | * UART will not idle or sleep for its timeout period. |
| 473 | * |
| 474 | **/ |
| 475 | static irqreturn_t omap_uart_interrupt(int irq, void *dev_id) |
| 476 | { |
| 477 | struct omap_uart_state *uart = dev_id; |
| 478 | |
| 479 | omap_uart_block_sleep(uart); |
| 480 | |
| 481 | return IRQ_NONE; |
| 482 | } |
| 483 | |
| 484 | static void omap_uart_idle_init(struct omap_uart_state *uart) |
| 485 | { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 486 | struct plat_serial8250_port *p = uart->p; |
| 487 | int ret; |
| 488 | |
| 489 | uart->can_sleep = 0; |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 490 | uart->timeout = DEFAULT_TIMEOUT; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 491 | setup_timer(&uart->timer, omap_uart_idle_timer, |
| 492 | (unsigned long) uart); |
Tony Lindgren | 301fe8e | 2010-02-01 12:34:31 -0800 | [diff] [blame] | 493 | if (uart->timeout) |
| 494 | mod_timer(&uart->timer, jiffies + uart->timeout); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 495 | omap_uart_smart_idle_enable(uart, 0); |
| 496 | |
| 497 | if (cpu_is_omap34xx()) { |
| 498 | u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD; |
| 499 | u32 wk_mask = 0; |
| 500 | u32 padconf = 0; |
| 501 | |
| 502 | uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); |
| 503 | uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); |
| 504 | switch (uart->num) { |
| 505 | case 0: |
| 506 | wk_mask = OMAP3430_ST_UART1_MASK; |
| 507 | padconf = 0x182; |
| 508 | break; |
| 509 | case 1: |
| 510 | wk_mask = OMAP3430_ST_UART2_MASK; |
| 511 | padconf = 0x17a; |
| 512 | break; |
| 513 | case 2: |
| 514 | wk_mask = OMAP3430_ST_UART3_MASK; |
| 515 | padconf = 0x19e; |
| 516 | break; |
| 517 | } |
| 518 | uart->wk_mask = wk_mask; |
| 519 | uart->padconf = padconf; |
| 520 | } else if (cpu_is_omap24xx()) { |
| 521 | u32 wk_mask = 0; |
| 522 | |
| 523 | if (cpu_is_omap2430()) { |
| 524 | uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1); |
| 525 | uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1); |
| 526 | } else if (cpu_is_omap2420()) { |
| 527 | uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1); |
| 528 | uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1); |
| 529 | } |
| 530 | switch (uart->num) { |
| 531 | case 0: |
| 532 | wk_mask = OMAP24XX_ST_UART1_MASK; |
| 533 | break; |
| 534 | case 1: |
| 535 | wk_mask = OMAP24XX_ST_UART2_MASK; |
| 536 | break; |
| 537 | case 2: |
| 538 | wk_mask = OMAP24XX_ST_UART3_MASK; |
| 539 | break; |
| 540 | } |
| 541 | uart->wk_mask = wk_mask; |
| 542 | } else { |
Nishanth Menon | c54bae1 | 2010-08-02 13:18:11 +0300 | [diff] [blame] | 543 | uart->wk_en = NULL; |
| 544 | uart->wk_st = NULL; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 545 | uart->wk_mask = 0; |
| 546 | uart->padconf = 0; |
| 547 | } |
| 548 | |
Vikram Pandita | c426df8 | 2009-08-28 11:24:08 -0700 | [diff] [blame] | 549 | p->irqflags |= IRQF_SHARED; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 550 | ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED, |
| 551 | "serial idle", (void *)uart); |
| 552 | WARN_ON(ret); |
| 553 | } |
| 554 | |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 555 | void omap_uart_enable_irqs(int enable) |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 556 | { |
Tero Kristo | 2466211 | 2009-03-05 16:32:23 +0200 | [diff] [blame] | 557 | int ret; |
| 558 | struct omap_uart_state *uart; |
| 559 | |
| 560 | list_for_each_entry(uart, &uart_list, node) { |
| 561 | if (enable) |
| 562 | ret = request_irq(uart->p->irq, omap_uart_interrupt, |
| 563 | IRQF_SHARED, "serial idle", (void *)uart); |
| 564 | else |
| 565 | free_irq(uart->p->irq, (void *)uart); |
| 566 | } |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 567 | } |
| 568 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 569 | static ssize_t sleep_timeout_show(struct device *dev, |
| 570 | struct device_attribute *attr, |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 571 | char *buf) |
| 572 | { |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 573 | struct platform_device *pdev = container_of(dev, |
| 574 | struct platform_device, dev); |
| 575 | struct omap_uart_state *uart = container_of(pdev, |
| 576 | struct omap_uart_state, pdev); |
| 577 | |
| 578 | return sprintf(buf, "%u\n", uart->timeout / HZ); |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 579 | } |
| 580 | |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 581 | static ssize_t sleep_timeout_store(struct device *dev, |
| 582 | struct device_attribute *attr, |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 583 | const char *buf, size_t n) |
| 584 | { |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 585 | struct platform_device *pdev = container_of(dev, |
| 586 | struct platform_device, dev); |
| 587 | struct omap_uart_state *uart = container_of(pdev, |
| 588 | struct omap_uart_state, pdev); |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 589 | unsigned int value; |
| 590 | |
| 591 | if (sscanf(buf, "%u", &value) != 1) { |
Sergio Aguirre | 10c805e | 2010-03-09 13:22:14 -0600 | [diff] [blame] | 592 | dev_err(dev, "sleep_timeout_store: Invalid value\n"); |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 593 | return -EINVAL; |
| 594 | } |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 595 | |
| 596 | uart->timeout = value * HZ; |
| 597 | if (uart->timeout) |
| 598 | mod_timer(&uart->timer, jiffies + uart->timeout); |
| 599 | else |
| 600 | /* A zero value means disable timeout feature */ |
| 601 | omap_uart_block_sleep(uart); |
| 602 | |
Jouni Hogander | ba87a9b | 2008-12-09 13:36:50 +0200 | [diff] [blame] | 603 | return n; |
| 604 | } |
| 605 | |
Nishanth Menon | bfe6977 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 606 | static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, |
| 607 | sleep_timeout_store); |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 608 | #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr)) |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 609 | #else |
| 610 | static inline void omap_uart_idle_init(struct omap_uart_state *uart) {} |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 611 | #define DEV_CREATE_FILE(dev, attr) |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 612 | #endif /* CONFIG_PM */ |
| 613 | |
Alexander Shishkin | 9d30b99 | 2009-11-22 10:10:47 -0800 | [diff] [blame] | 614 | static struct omap_uart_state omap_uart[] = { |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 615 | { |
| 616 | .pdev = { |
| 617 | .name = "serial8250", |
| 618 | .id = PLAT8250_DEV_PLATFORM, |
| 619 | .dev = { |
| 620 | .platform_data = serial_platform_data0, |
| 621 | }, |
| 622 | }, |
| 623 | }, { |
| 624 | .pdev = { |
| 625 | .name = "serial8250", |
| 626 | .id = PLAT8250_DEV_PLATFORM1, |
| 627 | .dev = { |
| 628 | .platform_data = serial_platform_data1, |
| 629 | }, |
| 630 | }, |
| 631 | }, { |
| 632 | .pdev = { |
| 633 | .name = "serial8250", |
| 634 | .id = PLAT8250_DEV_PLATFORM2, |
| 635 | .dev = { |
| 636 | .platform_data = serial_platform_data2, |
| 637 | }, |
| 638 | }, |
Vikram Pandita | 2aa57be | 2009-05-28 14:03:59 -0700 | [diff] [blame] | 639 | }, |
Tony Lindgren | a3a9b36 | 2010-02-15 09:27:25 -0800 | [diff] [blame] | 640 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) |
Santosh Shilimkar | 0e3eaad | 2009-08-22 13:30:11 +0530 | [diff] [blame] | 641 | { |
| 642 | .pdev = { |
| 643 | .name = "serial8250", |
Tony Lindgren | 61f04ee | 2009-09-24 16:23:07 -0700 | [diff] [blame] | 644 | .id = 3, |
Santosh Shilimkar | 0e3eaad | 2009-08-22 13:30:11 +0530 | [diff] [blame] | 645 | .dev = { |
| 646 | .platform_data = serial_platform_data3, |
| 647 | }, |
| 648 | }, |
| 649 | }, |
| 650 | #endif |
Vikram Pandita | 2aa57be | 2009-05-28 14:03:59 -0700 | [diff] [blame] | 651 | }; |
| 652 | |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 653 | /* |
| 654 | * Override the default 8250 read handler: mem_serial_in() |
| 655 | * Empty RX fifo read causes an abort on omap3630 and omap4 |
| 656 | * This function makes sure that an empty rx fifo is not read on these silicons |
| 657 | * (OMAP1/2/3430 are not affected) |
| 658 | */ |
| 659 | static unsigned int serial_in_override(struct uart_port *up, int offset) |
| 660 | { |
| 661 | if (UART_RX == offset) { |
| 662 | unsigned int lsr; |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 663 | lsr = __serial_read_reg(up, UART_LSR); |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 664 | if (!(lsr & UART_LSR_DR)) |
| 665 | return -EPERM; |
| 666 | } |
Alexander Shishkin | 9230372 | 2010-01-08 10:29:06 -0800 | [diff] [blame] | 667 | |
| 668 | return __serial_read_reg(up, offset); |
vikram pandita | ce13d47 | 2009-12-11 16:16:37 -0800 | [diff] [blame] | 669 | } |
| 670 | |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 671 | static void serial_out_override(struct uart_port *up, int offset, int value) |
| 672 | { |
| 673 | unsigned int status, tmout = 10000; |
| 674 | |
| 675 | status = __serial_read_reg(up, UART_LSR); |
| 676 | while (!(status & UART_LSR_THRE)) { |
| 677 | /* Wait up to 10ms for the character(s) to be sent. */ |
| 678 | if (--tmout == 0) |
| 679 | break; |
| 680 | udelay(1); |
| 681 | status = __serial_read_reg(up, UART_LSR); |
| 682 | } |
| 683 | __serial_write_reg(up, offset, value); |
| 684 | } |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 685 | void __init omap_serial_early_init(void) |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 686 | { |
Thomas Weber | 21b9034 | 2010-02-25 09:40:19 +0000 | [diff] [blame] | 687 | int i, nr_ports; |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 688 | char name[16]; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 689 | |
Thomas Weber | 21b9034 | 2010-02-25 09:40:19 +0000 | [diff] [blame] | 690 | if (!(cpu_is_omap3630() || cpu_is_omap4430())) |
| 691 | nr_ports = 3; |
| 692 | else |
| 693 | nr_ports = ARRAY_SIZE(omap_uart); |
| 694 | |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 695 | /* |
| 696 | * Make sure the serial ports are muxed on at this point. |
| 697 | * You have to mux them off in device drivers later on |
| 698 | * if not needed. |
| 699 | */ |
| 700 | |
Thomas Weber | 21b9034 | 2010-02-25 09:40:19 +0000 | [diff] [blame] | 701 | for (i = 0; i < nr_ports; i++) { |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 702 | struct omap_uart_state *uart = &omap_uart[i]; |
Kevin Hilman | fd455ea | 2009-04-27 12:27:36 -0700 | [diff] [blame] | 703 | struct platform_device *pdev = &uart->pdev; |
| 704 | struct device *dev = &pdev->dev; |
| 705 | struct plat_serial8250_port *p = dev->platform_data; |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 706 | |
Sergio Aguirre | e88d556 | 2010-02-27 14:13:43 -0600 | [diff] [blame] | 707 | /* Don't map zero-based physical address */ |
| 708 | if (p->mapbase == 0) { |
Sergio Aguirre | 10c805e | 2010-03-09 13:22:14 -0600 | [diff] [blame] | 709 | dev_warn(dev, "no physical address for uart#%d," |
| 710 | " so skipping early_init...\n", i); |
Sergio Aguirre | e88d556 | 2010-02-27 14:13:43 -0600 | [diff] [blame] | 711 | continue; |
| 712 | } |
Tony Lindgren | 84f90c9 | 2009-10-16 09:53:00 -0700 | [diff] [blame] | 713 | /* |
| 714 | * Module 4KB + L4 interconnect 4KB |
| 715 | * Static mapping, never released |
| 716 | */ |
| 717 | p->membase = ioremap(p->mapbase, SZ_8K); |
| 718 | if (!p->membase) { |
Sergio Aguirre | 10c805e | 2010-03-09 13:22:14 -0600 | [diff] [blame] | 719 | dev_err(dev, "ioremap failed for uart%i\n", i + 1); |
Tony Lindgren | 84f90c9 | 2009-10-16 09:53:00 -0700 | [diff] [blame] | 720 | continue; |
| 721 | } |
| 722 | |
Thomas Weber | 21b9034 | 2010-02-25 09:40:19 +0000 | [diff] [blame] | 723 | sprintf(name, "uart%d_ick", i + 1); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 724 | uart->ick = clk_get(NULL, name); |
| 725 | if (IS_ERR(uart->ick)) { |
Sergio Aguirre | 10c805e | 2010-03-09 13:22:14 -0600 | [diff] [blame] | 726 | dev_err(dev, "Could not get uart%d_ick\n", i + 1); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 727 | uart->ick = NULL; |
| 728 | } |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 729 | |
Jouni Hogander | 6e81176 | 2008-10-06 15:49:15 +0300 | [diff] [blame] | 730 | sprintf(name, "uart%d_fck", i+1); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 731 | uart->fck = clk_get(NULL, name); |
| 732 | if (IS_ERR(uart->fck)) { |
Sergio Aguirre | 10c805e | 2010-03-09 13:22:14 -0600 | [diff] [blame] | 733 | dev_err(dev, "Could not get uart%d_fck\n", i + 1); |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 734 | uart->fck = NULL; |
| 735 | } |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 736 | |
Santosh Shilimkar | aae290f | 2009-08-22 13:30:12 +0530 | [diff] [blame] | 737 | /* FIXME: Remove this once the clkdev is ready */ |
| 738 | if (!cpu_is_omap44xx()) { |
| 739 | if (!uart->ick || !uart->fck) |
| 740 | continue; |
| 741 | } |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 742 | |
| 743 | uart->num = i; |
| 744 | p->private_data = uart; |
| 745 | uart->p = p; |
Kevin Hilman | 4af4016 | 2009-02-04 10:51:40 -0800 | [diff] [blame] | 746 | |
Kevin Hilman | 4789998 | 2009-06-24 10:32:03 -0700 | [diff] [blame] | 747 | if (cpu_is_omap44xx()) |
| 748 | p->irq += 32; |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 749 | } |
| 750 | } |
| 751 | |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 752 | /** |
| 753 | * omap_serial_init_port() - initialize single serial port |
| 754 | * @port: serial port number (0-3) |
| 755 | * |
| 756 | * This function initialies serial driver for given @port only. |
| 757 | * Platforms can call this function instead of omap_serial_init() |
| 758 | * if they don't plan to use all available UARTs as serial ports. |
| 759 | * |
| 760 | * Don't mix calls to omap_serial_init_port() and omap_serial_init(), |
| 761 | * use only one of the two. |
| 762 | */ |
| 763 | void __init omap_serial_init_port(int port) |
| 764 | { |
| 765 | struct omap_uart_state *uart; |
| 766 | struct platform_device *pdev; |
| 767 | struct device *dev; |
| 768 | |
| 769 | BUG_ON(port < 0); |
| 770 | BUG_ON(port >= ARRAY_SIZE(omap_uart)); |
| 771 | |
| 772 | uart = &omap_uart[port]; |
| 773 | pdev = &uart->pdev; |
| 774 | dev = &pdev->dev; |
| 775 | |
Sergio Aguirre | e88d556 | 2010-02-27 14:13:43 -0600 | [diff] [blame] | 776 | /* Don't proceed if there's no clocks available */ |
| 777 | if (unlikely(!uart->ick || !uart->fck)) { |
| 778 | WARN(1, "%s: can't init uart%d, no clocks available\n", |
| 779 | kobject_name(&dev->kobj), port); |
| 780 | return; |
| 781 | } |
| 782 | |
Mika Westerberg | f2eeeae | 2009-12-14 13:59:18 +0000 | [diff] [blame] | 783 | omap_uart_enable_clocks(uart); |
| 784 | |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 785 | omap_uart_reset(uart); |
| 786 | omap_uart_idle_init(uart); |
| 787 | |
Mika Westerberg | f2eeeae | 2009-12-14 13:59:18 +0000 | [diff] [blame] | 788 | list_add_tail(&uart->node, &uart_list); |
| 789 | |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 790 | if (WARN_ON(platform_device_register(pdev))) |
| 791 | return; |
| 792 | |
| 793 | if ((cpu_is_omap34xx() && uart->padconf) || |
| 794 | (uart->wk_en && uart->wk_mask)) { |
| 795 | device_init_wakeup(dev, true); |
| 796 | DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout); |
| 797 | } |
| 798 | |
vikram pandita | 30e53bc | 2010-02-15 10:03:33 -0800 | [diff] [blame] | 799 | /* |
| 800 | * omap44xx: Never read empty UART fifo |
| 801 | * omap3xxx: Never read empty UART fifo on UARTs |
| 802 | * with IP rev >=0x52 |
| 803 | */ |
Nishanth Menon | 5a927b3 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 804 | if (cpu_is_omap44xx()) |
| 805 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
| 806 | else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF) |
| 807 | >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) |
| 808 | uart->errata |= UART_ERRATA_FIFO_FULL_ABORT; |
| 809 | |
| 810 | if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) { |
vikram pandita | 30e53bc | 2010-02-15 10:03:33 -0800 | [diff] [blame] | 811 | uart->p->serial_in = serial_in_override; |
Santosh Shilimkar | e03d37d | 2010-02-18 08:59:06 +0000 | [diff] [blame] | 812 | uart->p->serial_out = serial_out_override; |
| 813 | } |
Deepak K | 0003450 | 2010-08-02 13:18:12 +0300 | [diff] [blame] | 814 | |
| 815 | /* Enable the MDR1 errata for OMAP3 */ |
| 816 | if (cpu_is_omap34xx()) |
| 817 | uart->errata |= UART_ERRATA_i202_MDR1_ACCESS; |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | /** |
| 821 | * omap_serial_init() - intialize all supported serial ports |
| 822 | * |
| 823 | * Initializes all available UARTs as serial ports. Platforms |
| 824 | * can call this function when they want to have default behaviour |
| 825 | * for serial ports (e.g initialize them all as serial ports). |
| 826 | */ |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 827 | void __init omap_serial_init(void) |
| 828 | { |
Tony Lindgren | a3a9b36 | 2010-02-15 09:27:25 -0800 | [diff] [blame] | 829 | int i, nr_ports; |
Paul Walmsley | b3c6df3 | 2009-09-03 20:14:02 +0300 | [diff] [blame] | 830 | |
Tony Lindgren | a3a9b36 | 2010-02-15 09:27:25 -0800 | [diff] [blame] | 831 | if (!(cpu_is_omap3630() || cpu_is_omap4430())) |
| 832 | nr_ports = 3; |
| 833 | else |
| 834 | nr_ports = ARRAY_SIZE(omap_uart); |
| 835 | |
| 836 | for (i = 0; i < nr_ports; i++) |
Mika Westerberg | f62349e | 2009-12-11 16:16:35 -0800 | [diff] [blame] | 837 | omap_serial_init_port(i); |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 838 | } |