Mark Allyn | 4856ab3 | 2010-11-17 15:45:36 -0800 | [diff] [blame] | 1 | #ifndef __SEP_DEV_H__ |
| 2 | #define __SEP_DEV_H__ |
| 3 | |
| 4 | /* |
| 5 | * |
| 6 | * sep_dev.h - Security Processor Device Structures |
| 7 | * |
| 8 | * Copyright(c) 2009,2010 Intel Corporation. All rights reserved. |
| 9 | * Contributions(c) 2009,2010 Discretix. All rights reserved. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the Free |
| 13 | * Software Foundation; version 2 of the License. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 18 | * more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along with |
| 21 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 22 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 23 | * |
| 24 | * CONTACTS: |
| 25 | * |
| 26 | * Mark Allyn mark.a.allyn@intel.com |
| 27 | * Jayant Mangalampalli jayant.mangalampalli@intel.com |
| 28 | * |
| 29 | * CHANGES |
| 30 | * 2010.09.14 upgrade to Medfield |
| 31 | */ |
| 32 | |
| 33 | struct sep_device { |
| 34 | /* pointer to pci dev */ |
| 35 | struct pci_dev *pdev; |
| 36 | |
| 37 | /* character device file */ |
| 38 | struct cdev sep_cdev; |
| 39 | struct cdev sep_daemon_cdev; |
| 40 | struct cdev sep_singleton_cdev; |
| 41 | |
| 42 | /* devices (using misc dev) */ |
| 43 | struct miscdevice miscdev_sep; |
| 44 | struct miscdevice miscdev_singleton; |
| 45 | struct miscdevice miscdev_daemon; |
| 46 | |
| 47 | /* major / minor numbers of device */ |
| 48 | dev_t sep_devno; |
| 49 | dev_t sep_daemon_devno; |
| 50 | dev_t sep_singleton_devno; |
| 51 | |
| 52 | struct mutex sep_mutex; |
| 53 | struct mutex ioctl_mutex; |
| 54 | spinlock_t snd_rply_lck; |
| 55 | |
| 56 | /* flags to indicate use and lock status of sep */ |
| 57 | u32 pid_doing_transaction; |
| 58 | unsigned long in_use_flags; |
| 59 | |
| 60 | /* request daemon alread open */ |
| 61 | unsigned long request_daemon_open; |
| 62 | |
| 63 | /* 1 = Moorestown; 0 = Medfield */ |
| 64 | int mrst; |
| 65 | |
| 66 | /* address of the shared memory allocated during init for SEP driver |
| 67 | (coherent alloc) */ |
| 68 | dma_addr_t shared_bus; |
| 69 | size_t shared_size; |
| 70 | void *shared_addr; |
| 71 | |
| 72 | /* restricted access region (coherent alloc) */ |
| 73 | dma_addr_t rar_bus; |
| 74 | size_t rar_size; |
| 75 | void *rar_addr; |
| 76 | |
| 77 | /* Firmware regions; cache is at rar for Moorestown and |
| 78 | resident is at rar for Medfield */ |
| 79 | dma_addr_t cache_bus; |
| 80 | size_t cache_size; |
| 81 | void *cache_addr; |
| 82 | |
| 83 | dma_addr_t resident_bus; |
| 84 | size_t resident_size; |
| 85 | void *resident_addr; |
| 86 | |
| 87 | /* sep's scratchpad */ |
| 88 | dma_addr_t dcache_bus; |
| 89 | size_t dcache_size; |
| 90 | void *dcache_addr; |
| 91 | |
| 92 | /* Only used on Medfield */ |
| 93 | dma_addr_t extapp_bus; |
| 94 | size_t extapp_size; |
| 95 | void *extapp_addr; |
| 96 | |
| 97 | /* start address of the access to the SEP registers from driver */ |
| 98 | dma_addr_t reg_physical_addr; |
| 99 | dma_addr_t reg_physical_end; |
| 100 | void __iomem *reg_addr; |
| 101 | |
| 102 | /* wait queue head (event) of the driver */ |
| 103 | wait_queue_head_t event; |
| 104 | wait_queue_head_t event_request_daemon; |
| 105 | wait_queue_head_t event_mmap; |
| 106 | |
| 107 | struct sep_caller_id_entry |
| 108 | caller_id_table[SEP_CALLER_ID_TABLE_NUM_ENTRIES]; |
| 109 | |
| 110 | /* access flag for singleton device */ |
| 111 | unsigned long singleton_access_flag; |
| 112 | |
| 113 | /* transaction counter that coordinates the |
| 114 | transactions between SEP and HOST */ |
| 115 | unsigned long send_ct; |
| 116 | /* counter for the messages from sep */ |
| 117 | unsigned long reply_ct; |
| 118 | /* counter for the number of bytes allocated in the pool for the |
| 119 | current transaction */ |
| 120 | long data_pool_bytes_allocated; |
| 121 | |
| 122 | u32 num_of_data_allocations; |
| 123 | |
| 124 | /* number of the lli tables created in the current transaction */ |
| 125 | u32 num_lli_tables_created; |
| 126 | |
| 127 | /* number of data control blocks */ |
| 128 | u32 nr_dcb_creat; |
| 129 | |
| 130 | struct sep_dma_resource dma_res_arr[SEP_MAX_NUM_SYNC_DMA_OPS]; |
| 131 | |
| 132 | }; |
| 133 | |
| 134 | static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value) |
| 135 | { |
| 136 | void __iomem *addr = dev->reg_addr + reg; |
| 137 | writel(value, addr); |
| 138 | } |
| 139 | |
| 140 | static inline u32 sep_read_reg(struct sep_device *dev, int reg) |
| 141 | { |
| 142 | void __iomem *addr = dev->reg_addr + reg; |
| 143 | return readl(addr); |
| 144 | } |
| 145 | |
| 146 | /* wait for SRAM write complete(indirect write */ |
| 147 | static inline void sep_wait_sram_write(struct sep_device *dev) |
| 148 | { |
| 149 | u32 reg_val; |
Peter Huewe | eb6b420 | 2010-12-02 00:43:32 +0100 | [diff] [blame^] | 150 | do { |
Mark Allyn | 4856ab3 | 2010-11-17 15:45:36 -0800 | [diff] [blame] | 151 | reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR); |
Peter Huewe | eb6b420 | 2010-12-02 00:43:32 +0100 | [diff] [blame^] | 152 | } while (!(reg_val & 1)); |
Mark Allyn | 4856ab3 | 2010-11-17 15:45:36 -0800 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | |
| 156 | #endif |