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Vladimir Barinov3e062b02007-06-05 16:36:55 +01001/*
2 * TI DaVinci clock definitions
3 *
Kevin Hilmanc5b736d2009-03-20 17:29:01 -07004 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
Vladimir Barinov3e062b02007-06-05 16:36:55 +01006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13#define __ARCH_ARM_DAVINCI_CLOCK_H
14
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070015#include <linux/list.h>
16#include <asm/clkdev.h>
17
18#define DAVINCI_PLL1_BASE 0x01c40800
19#define DAVINCI_PLL2_BASE 0x01c40c00
20#define MAX_PLL 2
21
22/* PLL/Reset register offsets */
23#define PLLCTL 0x100
24#define PLLCTL_PLLEN BIT(0)
25#define PLLCTL_CLKMODE BIT(8)
26
27#define PLLM 0x110
28#define PLLM_PLLM_MASK 0xff
29
30#define PREDIV 0x114
31#define PLLDIV1 0x118
32#define PLLDIV2 0x11c
33#define PLLDIV3 0x120
34#define POSTDIV 0x128
35#define BPDIV 0x12c
36#define PLLCMD 0x138
37#define PLLSTAT 0x13c
38#define PLLALNCTL 0x140
39#define PLLDCHANGE 0x144
40#define PLLCKEN 0x148
41#define PLLCKSTAT 0x14c
42#define PLLSYSTAT 0x150
43#define PLLDIV4 0x160
44#define PLLDIV5 0x164
45#define PLLDIV6 0x168
46#define PLLDIV7 0x16c
47#define PLLDIV8 0x170
48#define PLLDIV9 0x174
49#define PLLDIV_EN BIT(15)
50#define PLLDIV_RATIO_MASK 0x1f
51
52struct pll_data {
53 u32 phys_base;
54 void __iomem *base;
55 u32 num;
56 u32 flags;
57 u32 input_rate;
58};
59#define PLL_HAS_PREDIV 0x01
60#define PLL_HAS_POSTDIV 0x02
61
Vladimir Barinov3e062b02007-06-05 16:36:55 +010062struct clk {
63 struct list_head node;
64 struct module *owner;
65 const char *name;
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070066 unsigned long rate;
67 u8 usecount;
68 u8 flags;
69 u8 lpsc;
Mark A. Greerd81d1882009-04-15 12:39:33 -070070 u8 psc_ctlr;
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070071 struct clk *parent;
72 struct pll_data *pll_data;
73 u32 div_reg;
Vladimir Barinov3e062b02007-06-05 16:36:55 +010074};
75
76/* Clock flags */
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070077#define ALWAYS_ENABLED BIT(1)
78#define CLK_PSC BIT(2)
79#define PSC_DSP BIT(3) /* PSC uses DSP domain, not ARM */
80#define CLK_PLL BIT(4) /* PLL-derived clock */
81#define PRE_PLL BIT(5) /* source is before PLL mult/div */
Vladimir Barinov3e062b02007-06-05 16:36:55 +010082
Kevin Hilmanc5b736d2009-03-20 17:29:01 -070083struct davinci_clk {
84 struct clk_lookup lk;
85};
86
87#define CLK(dev, con, ck) \
88 { \
89 .lk = { \
90 .dev_id = dev, \
91 .con_id = con, \
92 .clk = ck, \
93 }, \
94 }
95
96int davinci_clk_init(struct davinci_clk *clocks);
Kevin Hilmanfb631382009-04-29 16:23:59 -070097
98extern struct platform_device davinci_wdt_device;
99
Vladimir Barinov3e062b02007-06-05 16:36:55 +0100100#endif