blob: baaaf328de2e2d8b724a7a0b1ce18f0ced18be0c [file] [log] [blame]
Kevin Hilman95a34772009-04-29 12:10:55 -07001/*
2 * TI DaVinci DM355 chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/clk.h>
Mark A. Greer65e866a2009-03-18 12:36:08 -050014#include <linux/serial_8250.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070015#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
Mark A. Greera9949552009-04-15 12:40:35 -070017#include <linux/gpio.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070018
19#include <linux/spi/spi.h>
20
Mark A. Greer79c3c0b2009-04-15 12:38:58 -070021#include <asm/mach/map.h>
22
Kevin Hilman95a34772009-04-29 12:10:55 -070023#include <mach/dm355.h>
24#include <mach/clock.h>
25#include <mach/cputype.h>
26#include <mach/edma.h>
27#include <mach/psc.h>
28#include <mach/mux.h>
29#include <mach/irqs.h>
Mark A. Greerf64691b2009-04-15 12:40:11 -070030#include <mach/time.h>
Mark A. Greer65e866a2009-03-18 12:36:08 -050031#include <mach/serial.h>
Mark A. Greer79c3c0b2009-04-15 12:38:58 -070032#include <mach/common.h>
Kevin Hilman95a34772009-04-29 12:10:55 -070033
34#include "clock.h"
35#include "mux.h"
36
Kevin Hilman96ed2992009-04-30 11:20:24 -070037#define DM355_UART2_BASE (IO_PHYS + 0x206000)
38
Kevin Hilman95a34772009-04-29 12:10:55 -070039/*
40 * Device specific clocks
41 */
42#define DM355_REF_FREQ 24000000 /* 24 or 36 MHz */
43
44static struct pll_data pll1_data = {
45 .num = 1,
46 .phys_base = DAVINCI_PLL1_BASE,
47 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
48};
49
50static struct pll_data pll2_data = {
51 .num = 2,
52 .phys_base = DAVINCI_PLL2_BASE,
53 .flags = PLL_HAS_PREDIV,
54};
55
56static struct clk ref_clk = {
57 .name = "ref_clk",
58 /* FIXME -- crystal rate is board-specific */
59 .rate = DM355_REF_FREQ,
60};
61
62static struct clk pll1_clk = {
63 .name = "pll1",
64 .parent = &ref_clk,
65 .flags = CLK_PLL,
66 .pll_data = &pll1_data,
67};
68
69static struct clk pll1_aux_clk = {
70 .name = "pll1_aux_clk",
71 .parent = &pll1_clk,
72 .flags = CLK_PLL | PRE_PLL,
73};
74
75static struct clk pll1_sysclk1 = {
76 .name = "pll1_sysclk1",
77 .parent = &pll1_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV1,
80};
81
82static struct clk pll1_sysclk2 = {
83 .name = "pll1_sysclk2",
84 .parent = &pll1_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV2,
87};
88
89static struct clk pll1_sysclk3 = {
90 .name = "pll1_sysclk3",
91 .parent = &pll1_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV3,
94};
95
96static struct clk pll1_sysclk4 = {
97 .name = "pll1_sysclk4",
98 .parent = &pll1_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV4,
101};
102
103static struct clk pll1_sysclkbp = {
104 .name = "pll1_sysclkbp",
105 .parent = &pll1_clk,
106 .flags = CLK_PLL | PRE_PLL,
107 .div_reg = BPDIV
108};
109
110static struct clk vpss_dac_clk = {
111 .name = "vpss_dac",
112 .parent = &pll1_sysclk3,
113 .lpsc = DM355_LPSC_VPSS_DAC,
114};
115
116static struct clk vpss_master_clk = {
117 .name = "vpss_master",
118 .parent = &pll1_sysclk4,
119 .lpsc = DAVINCI_LPSC_VPSSMSTR,
120 .flags = CLK_PSC,
121};
122
123static struct clk vpss_slave_clk = {
124 .name = "vpss_slave",
125 .parent = &pll1_sysclk4,
126 .lpsc = DAVINCI_LPSC_VPSSSLV,
127};
128
129
130static struct clk clkout1_clk = {
131 .name = "clkout1",
132 .parent = &pll1_aux_clk,
133 /* NOTE: clkout1 can be externally gated by muxing GPIO-18 */
134};
135
136static struct clk clkout2_clk = {
137 .name = "clkout2",
138 .parent = &pll1_sysclkbp,
139};
140
141static struct clk pll2_clk = {
142 .name = "pll2",
143 .parent = &ref_clk,
144 .flags = CLK_PLL,
145 .pll_data = &pll2_data,
146};
147
148static struct clk pll2_sysclk1 = {
149 .name = "pll2_sysclk1",
150 .parent = &pll2_clk,
151 .flags = CLK_PLL,
152 .div_reg = PLLDIV1,
153};
154
155static struct clk pll2_sysclkbp = {
156 .name = "pll2_sysclkbp",
157 .parent = &pll2_clk,
158 .flags = CLK_PLL | PRE_PLL,
159 .div_reg = BPDIV
160};
161
162static struct clk clkout3_clk = {
163 .name = "clkout3",
164 .parent = &pll2_sysclkbp,
165 /* NOTE: clkout3 can be externally gated by muxing GPIO-16 */
166};
167
168static struct clk arm_clk = {
169 .name = "arm_clk",
170 .parent = &pll1_sysclk1,
171 .lpsc = DAVINCI_LPSC_ARM,
172 .flags = ALWAYS_ENABLED,
173};
174
175/*
176 * NOT LISTED below, and not touched by Linux
177 * - in SyncReset state by default
178 * .lpsc = DAVINCI_LPSC_TPCC,
179 * .lpsc = DAVINCI_LPSC_TPTC0,
180 * .lpsc = DAVINCI_LPSC_TPTC1,
181 * .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
182 * .lpsc = DAVINCI_LPSC_MEMSTICK,
183 * - in Enabled state by default
184 * .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
185 * .lpsc = DAVINCI_LPSC_SCR2, // "bus"
186 * .lpsc = DAVINCI_LPSC_SCR3, // "bus"
187 * .lpsc = DAVINCI_LPSC_SCR4, // "bus"
188 * .lpsc = DAVINCI_LPSC_CROSSBAR, // "emulation"
189 * .lpsc = DAVINCI_LPSC_CFG27, // "test"
190 * .lpsc = DAVINCI_LPSC_CFG3, // "test"
191 * .lpsc = DAVINCI_LPSC_CFG5, // "test"
192 */
193
194static struct clk mjcp_clk = {
195 .name = "mjcp",
196 .parent = &pll1_sysclk1,
197 .lpsc = DAVINCI_LPSC_IMCOP,
198};
199
200static struct clk uart0_clk = {
201 .name = "uart0",
202 .parent = &pll1_aux_clk,
203 .lpsc = DAVINCI_LPSC_UART0,
204};
205
206static struct clk uart1_clk = {
207 .name = "uart1",
208 .parent = &pll1_aux_clk,
209 .lpsc = DAVINCI_LPSC_UART1,
210};
211
212static struct clk uart2_clk = {
213 .name = "uart2",
214 .parent = &pll1_sysclk2,
215 .lpsc = DAVINCI_LPSC_UART2,
216};
217
218static struct clk i2c_clk = {
219 .name = "i2c",
220 .parent = &pll1_aux_clk,
221 .lpsc = DAVINCI_LPSC_I2C,
222};
223
224static struct clk asp0_clk = {
225 .name = "asp0",
226 .parent = &pll1_sysclk2,
227 .lpsc = DAVINCI_LPSC_McBSP,
228};
229
230static struct clk asp1_clk = {
231 .name = "asp1",
232 .parent = &pll1_sysclk2,
233 .lpsc = DM355_LPSC_McBSP1,
234};
235
236static struct clk mmcsd0_clk = {
237 .name = "mmcsd0",
238 .parent = &pll1_sysclk2,
239 .lpsc = DAVINCI_LPSC_MMC_SD,
240};
241
242static struct clk mmcsd1_clk = {
243 .name = "mmcsd1",
244 .parent = &pll1_sysclk2,
245 .lpsc = DM355_LPSC_MMC_SD1,
246};
247
248static struct clk spi0_clk = {
249 .name = "spi0",
250 .parent = &pll1_sysclk2,
251 .lpsc = DAVINCI_LPSC_SPI,
252};
253
254static struct clk spi1_clk = {
255 .name = "spi1",
256 .parent = &pll1_sysclk2,
257 .lpsc = DM355_LPSC_SPI1,
258};
259
260static struct clk spi2_clk = {
261 .name = "spi2",
262 .parent = &pll1_sysclk2,
263 .lpsc = DM355_LPSC_SPI2,
264};
265
266static struct clk gpio_clk = {
267 .name = "gpio",
268 .parent = &pll1_sysclk2,
269 .lpsc = DAVINCI_LPSC_GPIO,
270};
271
272static struct clk aemif_clk = {
273 .name = "aemif",
274 .parent = &pll1_sysclk2,
275 .lpsc = DAVINCI_LPSC_AEMIF,
276};
277
278static struct clk pwm0_clk = {
279 .name = "pwm0",
280 .parent = &pll1_aux_clk,
281 .lpsc = DAVINCI_LPSC_PWM0,
282};
283
284static struct clk pwm1_clk = {
285 .name = "pwm1",
286 .parent = &pll1_aux_clk,
287 .lpsc = DAVINCI_LPSC_PWM1,
288};
289
290static struct clk pwm2_clk = {
291 .name = "pwm2",
292 .parent = &pll1_aux_clk,
293 .lpsc = DAVINCI_LPSC_PWM2,
294};
295
296static struct clk pwm3_clk = {
297 .name = "pwm3",
298 .parent = &pll1_aux_clk,
299 .lpsc = DM355_LPSC_PWM3,
300};
301
302static struct clk timer0_clk = {
303 .name = "timer0",
304 .parent = &pll1_aux_clk,
305 .lpsc = DAVINCI_LPSC_TIMER0,
306};
307
308static struct clk timer1_clk = {
309 .name = "timer1",
310 .parent = &pll1_aux_clk,
311 .lpsc = DAVINCI_LPSC_TIMER1,
312};
313
314static struct clk timer2_clk = {
315 .name = "timer2",
316 .parent = &pll1_aux_clk,
317 .lpsc = DAVINCI_LPSC_TIMER2,
318 .usecount = 1, /* REVISIT: why cant' this be disabled? */
319};
320
321static struct clk timer3_clk = {
322 .name = "timer3",
323 .parent = &pll1_aux_clk,
324 .lpsc = DM355_LPSC_TIMER3,
325};
326
327static struct clk rto_clk = {
328 .name = "rto",
329 .parent = &pll1_aux_clk,
330 .lpsc = DM355_LPSC_RTO,
331};
332
333static struct clk usb_clk = {
334 .name = "usb",
335 .parent = &pll1_sysclk2,
336 .lpsc = DAVINCI_LPSC_USB,
337};
338
339static struct davinci_clk dm355_clks[] = {
340 CLK(NULL, "ref", &ref_clk),
341 CLK(NULL, "pll1", &pll1_clk),
342 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
343 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
344 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
345 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
346 CLK(NULL, "pll1_aux", &pll1_aux_clk),
347 CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
348 CLK(NULL, "vpss_dac", &vpss_dac_clk),
349 CLK(NULL, "vpss_master", &vpss_master_clk),
350 CLK(NULL, "vpss_slave", &vpss_slave_clk),
351 CLK(NULL, "clkout1", &clkout1_clk),
352 CLK(NULL, "clkout2", &clkout2_clk),
353 CLK(NULL, "pll2", &pll2_clk),
354 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
355 CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
356 CLK(NULL, "clkout3", &clkout3_clk),
357 CLK(NULL, "arm", &arm_clk),
358 CLK(NULL, "mjcp", &mjcp_clk),
359 CLK(NULL, "uart0", &uart0_clk),
360 CLK(NULL, "uart1", &uart1_clk),
361 CLK(NULL, "uart2", &uart2_clk),
362 CLK("i2c_davinci.1", NULL, &i2c_clk),
363 CLK("soc-audio.0", NULL, &asp0_clk),
364 CLK("soc-audio.1", NULL, &asp1_clk),
365 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
366 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
367 CLK(NULL, "spi0", &spi0_clk),
368 CLK(NULL, "spi1", &spi1_clk),
369 CLK(NULL, "spi2", &spi2_clk),
370 CLK(NULL, "gpio", &gpio_clk),
371 CLK(NULL, "aemif", &aemif_clk),
372 CLK(NULL, "pwm0", &pwm0_clk),
373 CLK(NULL, "pwm1", &pwm1_clk),
374 CLK(NULL, "pwm2", &pwm2_clk),
375 CLK(NULL, "pwm3", &pwm3_clk),
376 CLK(NULL, "timer0", &timer0_clk),
377 CLK(NULL, "timer1", &timer1_clk),
378 CLK("watchdog", NULL, &timer2_clk),
379 CLK(NULL, "timer3", &timer3_clk),
380 CLK(NULL, "rto", &rto_clk),
381 CLK(NULL, "usb", &usb_clk),
382 CLK(NULL, NULL, NULL),
383};
384
385/*----------------------------------------------------------------------*/
386
387static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
388
389static struct resource dm355_spi0_resources[] = {
390 {
391 .start = 0x01c66000,
392 .end = 0x01c667ff,
393 .flags = IORESOURCE_MEM,
394 },
395 {
396 .start = IRQ_DM355_SPINT0_1,
397 .flags = IORESOURCE_IRQ,
398 },
399 /* Not yet used, so not included:
400 * IORESOURCE_IRQ:
401 * - IRQ_DM355_SPINT0_0
402 * IORESOURCE_DMA:
403 * - DAVINCI_DMA_SPI_SPIX
404 * - DAVINCI_DMA_SPI_SPIR
405 */
406};
407
408static struct platform_device dm355_spi0_device = {
409 .name = "spi_davinci",
410 .id = 0,
411 .dev = {
412 .dma_mask = &dm355_spi0_dma_mask,
413 .coherent_dma_mask = DMA_BIT_MASK(32),
414 },
415 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
416 .resource = dm355_spi0_resources,
417};
418
419void __init dm355_init_spi0(unsigned chipselect_mask,
420 struct spi_board_info *info, unsigned len)
421{
422 /* for now, assume we need MISO */
423 davinci_cfg_reg(DM355_SPI0_SDI);
424
425 /* not all slaves will be wired up */
426 if (chipselect_mask & BIT(0))
427 davinci_cfg_reg(DM355_SPI0_SDENA0);
428 if (chipselect_mask & BIT(1))
429 davinci_cfg_reg(DM355_SPI0_SDENA1);
430
431 spi_register_board_info(info, len);
432
433 platform_device_register(&dm355_spi0_device);
434}
435
436/*----------------------------------------------------------------------*/
437
Mark A. Greer55700782009-04-15 12:42:06 -0700438#define PINMUX0 0x00
439#define PINMUX1 0x04
440#define PINMUX2 0x08
441#define PINMUX3 0x0c
442#define PINMUX4 0x10
443#define INTMUX 0x18
444#define EVTMUX 0x1c
445
Kevin Hilman95a34772009-04-29 12:10:55 -0700446/*
447 * Device specific mux setup
448 *
449 * soc description mux mode mode mux dbg
450 * reg offset mask mode
451 */
452static const struct mux_config dm355_pins[] = {
Mark A. Greer0e585952009-04-15 12:39:48 -0700453#ifdef CONFIG_DAVINCI_MUX
Kevin Hilman95a34772009-04-29 12:10:55 -0700454MUX_CFG(DM355, MMCSD0, 4, 2, 1, 0, false)
455
456MUX_CFG(DM355, SD1_CLK, 3, 6, 1, 1, false)
457MUX_CFG(DM355, SD1_CMD, 3, 7, 1, 1, false)
458MUX_CFG(DM355, SD1_DATA3, 3, 8, 3, 1, false)
459MUX_CFG(DM355, SD1_DATA2, 3, 10, 3, 1, false)
460MUX_CFG(DM355, SD1_DATA1, 3, 12, 3, 1, false)
461MUX_CFG(DM355, SD1_DATA0, 3, 14, 3, 1, false)
462
463MUX_CFG(DM355, I2C_SDA, 3, 19, 1, 1, false)
464MUX_CFG(DM355, I2C_SCL, 3, 20, 1, 1, false)
465
466MUX_CFG(DM355, MCBSP0_BDX, 3, 0, 1, 1, false)
467MUX_CFG(DM355, MCBSP0_X, 3, 1, 1, 1, false)
468MUX_CFG(DM355, MCBSP0_BFSX, 3, 2, 1, 1, false)
469MUX_CFG(DM355, MCBSP0_BDR, 3, 3, 1, 1, false)
470MUX_CFG(DM355, MCBSP0_R, 3, 4, 1, 1, false)
471MUX_CFG(DM355, MCBSP0_BFSR, 3, 5, 1, 1, false)
472
473MUX_CFG(DM355, SPI0_SDI, 4, 1, 1, 0, false)
474MUX_CFG(DM355, SPI0_SDENA0, 4, 0, 1, 0, false)
475MUX_CFG(DM355, SPI0_SDENA1, 3, 28, 1, 1, false)
476
477INT_CFG(DM355, INT_EDMA_CC, 2, 1, 1, false)
478INT_CFG(DM355, INT_EDMA_TC0_ERR, 3, 1, 1, false)
479INT_CFG(DM355, INT_EDMA_TC1_ERR, 4, 1, 1, false)
480
481EVT_CFG(DM355, EVT8_ASP1_TX, 0, 1, 0, false)
482EVT_CFG(DM355, EVT9_ASP1_RX, 1, 1, 0, false)
483EVT_CFG(DM355, EVT26_MMC0_RX, 2, 1, 0, false)
Mark A. Greer0e585952009-04-15 12:39:48 -0700484#endif
Kevin Hilman95a34772009-04-29 12:10:55 -0700485};
486
Mark A. Greer673dd362009-04-15 12:40:00 -0700487static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
488 [IRQ_DM355_CCDC_VDINT0] = 2,
489 [IRQ_DM355_CCDC_VDINT1] = 6,
490 [IRQ_DM355_CCDC_VDINT2] = 6,
491 [IRQ_DM355_IPIPE_HST] = 6,
492 [IRQ_DM355_H3AINT] = 6,
493 [IRQ_DM355_IPIPE_SDR] = 6,
494 [IRQ_DM355_IPIPEIFINT] = 6,
495 [IRQ_DM355_OSDINT] = 7,
496 [IRQ_DM355_VENCINT] = 6,
497 [IRQ_ASQINT] = 6,
498 [IRQ_IMXINT] = 6,
499 [IRQ_USBINT] = 4,
500 [IRQ_DM355_RTOINT] = 4,
501 [IRQ_DM355_UARTINT2] = 7,
502 [IRQ_DM355_TINT6] = 7,
503 [IRQ_CCINT0] = 5, /* dma */
504 [IRQ_CCERRINT] = 5, /* dma */
505 [IRQ_TCERRINT0] = 5, /* dma */
506 [IRQ_TCERRINT] = 5, /* dma */
507 [IRQ_DM355_SPINT2_1] = 7,
508 [IRQ_DM355_TINT7] = 4,
509 [IRQ_DM355_SDIOINT0] = 7,
510 [IRQ_MBXINT] = 7,
511 [IRQ_MBRINT] = 7,
512 [IRQ_MMCINT] = 7,
513 [IRQ_DM355_MMCINT1] = 7,
514 [IRQ_DM355_PWMINT3] = 7,
515 [IRQ_DDRINT] = 7,
516 [IRQ_AEMIFINT] = 7,
517 [IRQ_DM355_SDIOINT1] = 4,
518 [IRQ_TINT0_TINT12] = 2, /* clockevent */
519 [IRQ_TINT0_TINT34] = 2, /* clocksource */
520 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
521 [IRQ_TINT1_TINT34] = 7, /* system tick */
522 [IRQ_PWMINT0] = 7,
523 [IRQ_PWMINT1] = 7,
524 [IRQ_PWMINT2] = 7,
525 [IRQ_I2C] = 3,
526 [IRQ_UARTINT0] = 3,
527 [IRQ_UARTINT1] = 3,
528 [IRQ_DM355_SPINT0_0] = 3,
529 [IRQ_DM355_SPINT0_1] = 3,
530 [IRQ_DM355_GPIO0] = 3,
531 [IRQ_DM355_GPIO1] = 7,
532 [IRQ_DM355_GPIO2] = 4,
533 [IRQ_DM355_GPIO3] = 4,
534 [IRQ_DM355_GPIO4] = 7,
535 [IRQ_DM355_GPIO5] = 7,
536 [IRQ_DM355_GPIO6] = 7,
537 [IRQ_DM355_GPIO7] = 7,
538 [IRQ_DM355_GPIO8] = 7,
539 [IRQ_DM355_GPIO9] = 7,
540 [IRQ_DM355_GPIOBNK0] = 7,
541 [IRQ_DM355_GPIOBNK1] = 7,
542 [IRQ_DM355_GPIOBNK2] = 7,
543 [IRQ_DM355_GPIOBNK3] = 7,
544 [IRQ_DM355_GPIOBNK4] = 7,
545 [IRQ_DM355_GPIOBNK5] = 7,
546 [IRQ_DM355_GPIOBNK6] = 7,
547 [IRQ_COMMTX] = 7,
548 [IRQ_COMMRX] = 7,
549 [IRQ_EMUINT] = 7,
550};
551
Kevin Hilman95a34772009-04-29 12:10:55 -0700552/*----------------------------------------------------------------------*/
553
554static const s8 dma_chan_dm355_no_event[] = {
555 12, 13, 24, 56, 57,
556 58, 59, 60, 61, 62,
557 63,
558 -1
559};
560
561static struct edma_soc_info dm355_edma_info = {
562 .n_channel = 64,
563 .n_region = 4,
564 .n_slot = 128,
565 .n_tc = 2,
566 .noevent = dma_chan_dm355_no_event,
567};
568
569static struct resource edma_resources[] = {
570 {
571 .name = "edma_cc",
572 .start = 0x01c00000,
573 .end = 0x01c00000 + SZ_64K - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .name = "edma_tc0",
578 .start = 0x01c10000,
579 .end = 0x01c10000 + SZ_1K - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 {
583 .name = "edma_tc1",
584 .start = 0x01c10400,
585 .end = 0x01c10400 + SZ_1K - 1,
586 .flags = IORESOURCE_MEM,
587 },
588 {
589 .start = IRQ_CCINT0,
590 .flags = IORESOURCE_IRQ,
591 },
592 {
593 .start = IRQ_CCERRINT,
594 .flags = IORESOURCE_IRQ,
595 },
596 /* not using (or muxing) TC*_ERR */
597};
598
599static struct platform_device dm355_edma_device = {
600 .name = "edma",
601 .id = -1,
602 .dev.platform_data = &dm355_edma_info,
603 .num_resources = ARRAY_SIZE(edma_resources),
604 .resource = edma_resources,
605};
606
607/*----------------------------------------------------------------------*/
608
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700609static struct map_desc dm355_io_desc[] = {
610 {
611 .virtual = IO_VIRT,
612 .pfn = __phys_to_pfn(IO_PHYS),
613 .length = IO_SIZE,
614 .type = MT_DEVICE
615 },
David Brownell0d04eb42009-04-30 17:35:48 -0700616 {
617 .virtual = SRAM_VIRT,
618 .pfn = __phys_to_pfn(0x00010000),
619 .length = SZ_32K,
620 /* MT_MEMORY_NONCACHED requires supersection alignment */
621 .type = MT_DEVICE,
622 },
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700623};
624
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700625/* Contents of JTAG ID register used to identify exact cpu type */
626static struct davinci_id dm355_ids[] = {
627 {
628 .variant = 0x0,
629 .part_no = 0xb73b,
630 .manufacturer = 0x00f,
631 .cpu_id = DAVINCI_CPU_ID_DM355,
632 .name = "dm355",
633 },
634};
635
Mark A. Greerd81d1882009-04-15 12:39:33 -0700636static void __iomem *dm355_psc_bases[] = {
637 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
638};
639
Mark A. Greerf64691b2009-04-15 12:40:11 -0700640/*
641 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
642 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
643 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
644 * T1_TOP: Timer 1, top : <unused>
645 */
646struct davinci_timer_info dm355_timer_info = {
647 .timers = davinci_timer_instance,
648 .clockevent_id = T0_BOT,
649 .clocksource_id = T0_TOP,
650};
651
Mark A. Greer65e866a2009-03-18 12:36:08 -0500652static struct plat_serial8250_port dm355_serial_platform_data[] = {
653 {
654 .mapbase = DAVINCI_UART0_BASE,
655 .irq = IRQ_UARTINT0,
656 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
657 UPF_IOREMAP,
658 .iotype = UPIO_MEM,
659 .regshift = 2,
660 },
661 {
662 .mapbase = DAVINCI_UART1_BASE,
663 .irq = IRQ_UARTINT1,
664 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
665 UPF_IOREMAP,
666 .iotype = UPIO_MEM,
667 .regshift = 2,
668 },
669 {
670 .mapbase = DM355_UART2_BASE,
671 .irq = IRQ_DM355_UARTINT2,
672 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
673 UPF_IOREMAP,
674 .iotype = UPIO_MEM,
675 .regshift = 2,
676 },
677 {
678 .flags = 0
679 },
680};
681
682static struct platform_device dm355_serial_device = {
683 .name = "serial8250",
684 .id = PLAT8250_DEV_PLATFORM,
685 .dev = {
686 .platform_data = dm355_serial_platform_data,
687 },
688};
689
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700690static struct davinci_soc_info davinci_soc_info_dm355 = {
691 .io_desc = dm355_io_desc,
692 .io_desc_num = ARRAY_SIZE(dm355_io_desc),
Mark A. Greerb9ab1272009-04-15 12:39:09 -0700693 .jtag_id_base = IO_ADDRESS(0x01c40028),
694 .ids = dm355_ids,
695 .ids_num = ARRAY_SIZE(dm355_ids),
Mark A. Greer66e0c392009-04-15 12:39:23 -0700696 .cpu_clks = dm355_clks,
Mark A. Greerd81d1882009-04-15 12:39:33 -0700697 .psc_bases = dm355_psc_bases,
698 .psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
Mark A. Greer0e585952009-04-15 12:39:48 -0700699 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
700 .pinmux_pins = dm355_pins,
701 .pinmux_pins_num = ARRAY_SIZE(dm355_pins),
Mark A. Greer673dd362009-04-15 12:40:00 -0700702 .intc_base = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
703 .intc_type = DAVINCI_INTC_TYPE_AINTC,
704 .intc_irq_prios = dm355_default_priorities,
705 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
Mark A. Greerf64691b2009-04-15 12:40:11 -0700706 .timer_info = &dm355_timer_info,
Mark A. Greer951d6f62009-04-15 12:40:21 -0700707 .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
Mark A. Greera9949552009-04-15 12:40:35 -0700708 .gpio_base = IO_ADDRESS(DAVINCI_GPIO_BASE),
709 .gpio_num = 104,
710 .gpio_irq = IRQ_DM355_GPIOBNK0,
Mark A. Greer65e866a2009-03-18 12:36:08 -0500711 .serial_dev = &dm355_serial_device,
David Brownell0d04eb42009-04-30 17:35:48 -0700712 .sram_dma = 0x00010000,
713 .sram_len = SZ_32K,
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700714};
715
Kevin Hilman95a34772009-04-29 12:10:55 -0700716void __init dm355_init(void)
717{
Mark A. Greer79c3c0b2009-04-15 12:38:58 -0700718 davinci_common_init(&davinci_soc_info_dm355);
Kevin Hilman95a34772009-04-29 12:10:55 -0700719}
720
721static int __init dm355_init_devices(void)
722{
723 if (!cpu_is_davinci_dm355())
724 return 0;
725
726 davinci_cfg_reg(DM355_INT_EDMA_CC);
727 platform_device_register(&dm355_edma_device);
728 return 0;
729}
730postcore_initcall(dm355_init_devices);