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Eddie Dong85f455f2007-07-06 12:20:49 +03001/*
2 * 8259 interrupt controller emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 * Authors:
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
26 * Port from Qemu.
27 */
28#include <linux/mm.h>
29#include "irq.h"
30
31/*
32 * set irq level. If an edge is detected, then the IRR is set to 1
33 */
34static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
35{
36 int mask;
37 mask = 1 << irq;
38 if (s->elcr & mask) /* level triggered */
39 if (level) {
40 s->irr |= mask;
41 s->last_irr |= mask;
42 } else {
43 s->irr &= ~mask;
44 s->last_irr &= ~mask;
45 }
46 else /* edge triggered */
47 if (level) {
48 if ((s->last_irr & mask) == 0)
49 s->irr |= mask;
50 s->last_irr |= mask;
51 } else
52 s->last_irr &= ~mask;
53}
54
55/*
56 * return the highest priority found in mask (highest = smallest
57 * number). Return 8 if no irq
58 */
59static inline int get_priority(struct kvm_kpic_state *s, int mask)
60{
61 int priority;
62 if (mask == 0)
63 return 8;
64 priority = 0;
65 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
66 priority++;
67 return priority;
68}
69
70/*
71 * return the pic wanted interrupt. return -1 if none
72 */
73static int pic_get_irq(struct kvm_kpic_state *s)
74{
75 int mask, cur_priority, priority;
76
77 mask = s->irr & ~s->imr;
78 priority = get_priority(s, mask);
79 if (priority == 8)
80 return -1;
81 /*
82 * compute current priority. If special fully nested mode on the
83 * master, the IRQ coming from the slave is not taken into account
84 * for the priority computation.
85 */
86 mask = s->isr;
87 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
88 mask &= ~(1 << 2);
89 cur_priority = get_priority(s, mask);
90 if (priority < cur_priority)
91 /*
92 * higher priority found: an irq should be generated
93 */
94 return (priority + s->priority_add) & 7;
95 else
96 return -1;
97}
98
99/*
100 * raise irq to CPU if necessary. must be called every time the active
101 * irq may change
102 */
103static void pic_update_irq(struct kvm_pic *s)
104{
105 int irq2, irq;
106
107 irq2 = pic_get_irq(&s->pics[1]);
108 if (irq2 >= 0) {
109 /*
110 * if irq request by slave pic, signal master PIC
111 */
112 pic_set_irq1(&s->pics[0], 2, 1);
113 pic_set_irq1(&s->pics[0], 2, 0);
114 }
115 irq = pic_get_irq(&s->pics[0]);
116 if (irq >= 0)
117 s->irq_request(s->irq_request_opaque, 1);
118 else
119 s->irq_request(s->irq_request_opaque, 0);
120}
121
He, Qing6ceb9d72007-07-26 11:05:18 +0300122void kvm_pic_update_irq(struct kvm_pic *s)
123{
124 pic_update_irq(s);
125}
126
Eddie Dong85f455f2007-07-06 12:20:49 +0300127void kvm_pic_set_irq(void *opaque, int irq, int level)
128{
129 struct kvm_pic *s = opaque;
130
131 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
132 pic_update_irq(s);
133}
134
135/*
136 * acknowledge interrupt 'irq'
137 */
138static inline void pic_intack(struct kvm_kpic_state *s, int irq)
139{
140 if (s->auto_eoi) {
141 if (s->rotate_on_auto_eoi)
142 s->priority_add = (irq + 1) & 7;
143 } else
144 s->isr |= (1 << irq);
145 /*
146 * We don't clear a level sensitive interrupt here
147 */
148 if (!(s->elcr & (1 << irq)))
149 s->irr &= ~(1 << irq);
150}
151
152int kvm_pic_read_irq(struct kvm_pic *s)
153{
154 int irq, irq2, intno;
155
156 irq = pic_get_irq(&s->pics[0]);
157 if (irq >= 0) {
158 pic_intack(&s->pics[0], irq);
159 if (irq == 2) {
160 irq2 = pic_get_irq(&s->pics[1]);
161 if (irq2 >= 0)
162 pic_intack(&s->pics[1], irq2);
163 else
164 /*
165 * spurious IRQ on slave controller
166 */
167 irq2 = 7;
168 intno = s->pics[1].irq_base + irq2;
169 irq = irq2 + 8;
170 } else
171 intno = s->pics[0].irq_base + irq;
172 } else {
173 /*
174 * spurious IRQ on host controller
175 */
176 irq = 7;
177 intno = s->pics[0].irq_base + irq;
178 }
179 pic_update_irq(s);
180
181 return intno;
182}
183
Eddie Dong2fcceae2007-10-10 12:14:25 +0200184void kvm_pic_reset(struct kvm_kpic_state *s)
Eddie Dong85f455f2007-07-06 12:20:49 +0300185{
Eddie Dong85f455f2007-07-06 12:20:49 +0300186 s->last_irr = 0;
187 s->irr = 0;
188 s->imr = 0;
189 s->isr = 0;
190 s->priority_add = 0;
191 s->irq_base = 0;
192 s->read_reg_select = 0;
193 s->poll = 0;
194 s->special_mask = 0;
195 s->init_state = 0;
196 s->auto_eoi = 0;
197 s->rotate_on_auto_eoi = 0;
198 s->special_fully_nested_mode = 0;
199 s->init4 = 0;
200}
201
202static void pic_ioport_write(void *opaque, u32 addr, u32 val)
203{
204 struct kvm_kpic_state *s = opaque;
205 int priority, cmd, irq;
206
207 addr &= 1;
208 if (addr == 0) {
209 if (val & 0x10) {
Eddie Dong2fcceae2007-10-10 12:14:25 +0200210 kvm_pic_reset(s); /* init */
Eddie Dong85f455f2007-07-06 12:20:49 +0300211 /*
212 * deassert a pending interrupt
213 */
214 s->pics_state->irq_request(s->pics_state->
215 irq_request_opaque, 0);
216 s->init_state = 1;
217 s->init4 = val & 1;
218 if (val & 0x02)
219 printk(KERN_ERR "single mode not supported");
220 if (val & 0x08)
221 printk(KERN_ERR
222 "level sensitive irq not supported");
223 } else if (val & 0x08) {
224 if (val & 0x04)
225 s->poll = 1;
226 if (val & 0x02)
227 s->read_reg_select = val & 1;
228 if (val & 0x40)
229 s->special_mask = (val >> 5) & 1;
230 } else {
231 cmd = val >> 5;
232 switch (cmd) {
233 case 0:
234 case 4:
235 s->rotate_on_auto_eoi = cmd >> 2;
236 break;
237 case 1: /* end of interrupt */
238 case 5:
239 priority = get_priority(s, s->isr);
240 if (priority != 8) {
241 irq = (priority + s->priority_add) & 7;
242 s->isr &= ~(1 << irq);
243 if (cmd == 5)
244 s->priority_add = (irq + 1) & 7;
245 pic_update_irq(s->pics_state);
246 }
247 break;
248 case 3:
249 irq = val & 7;
250 s->isr &= ~(1 << irq);
251 pic_update_irq(s->pics_state);
252 break;
253 case 6:
254 s->priority_add = (val + 1) & 7;
255 pic_update_irq(s->pics_state);
256 break;
257 case 7:
258 irq = val & 7;
259 s->isr &= ~(1 << irq);
260 s->priority_add = (irq + 1) & 7;
261 pic_update_irq(s->pics_state);
262 break;
263 default:
264 break; /* no operation */
265 }
266 }
267 } else
268 switch (s->init_state) {
269 case 0: /* normal mode */
270 s->imr = val;
271 pic_update_irq(s->pics_state);
272 break;
273 case 1:
274 s->irq_base = val & 0xf8;
275 s->init_state = 2;
276 break;
277 case 2:
278 if (s->init4)
279 s->init_state = 3;
280 else
281 s->init_state = 0;
282 break;
283 case 3:
284 s->special_fully_nested_mode = (val >> 4) & 1;
285 s->auto_eoi = (val >> 1) & 1;
286 s->init_state = 0;
287 break;
288 }
289}
290
291static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
292{
293 int ret;
294
295 ret = pic_get_irq(s);
296 if (ret >= 0) {
297 if (addr1 >> 7) {
298 s->pics_state->pics[0].isr &= ~(1 << 2);
299 s->pics_state->pics[0].irr &= ~(1 << 2);
300 }
301 s->irr &= ~(1 << ret);
302 s->isr &= ~(1 << ret);
303 if (addr1 >> 7 || ret != 2)
304 pic_update_irq(s->pics_state);
305 } else {
306 ret = 0x07;
307 pic_update_irq(s->pics_state);
308 }
309
310 return ret;
311}
312
313static u32 pic_ioport_read(void *opaque, u32 addr1)
314{
315 struct kvm_kpic_state *s = opaque;
316 unsigned int addr;
317 int ret;
318
319 addr = addr1;
320 addr &= 1;
321 if (s->poll) {
322 ret = pic_poll_read(s, addr1);
323 s->poll = 0;
324 } else
325 if (addr == 0)
326 if (s->read_reg_select)
327 ret = s->isr;
328 else
329 ret = s->irr;
330 else
331 ret = s->imr;
332 return ret;
333}
334
335static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
336{
337 struct kvm_kpic_state *s = opaque;
338 s->elcr = val & s->elcr_mask;
339}
340
341static u32 elcr_ioport_read(void *opaque, u32 addr1)
342{
343 struct kvm_kpic_state *s = opaque;
344 return s->elcr;
345}
346
347static int picdev_in_range(struct kvm_io_device *this, gpa_t addr)
348{
349 switch (addr) {
350 case 0x20:
351 case 0x21:
352 case 0xa0:
353 case 0xa1:
354 case 0x4d0:
355 case 0x4d1:
356 return 1;
357 default:
358 return 0;
359 }
360}
361
362static void picdev_write(struct kvm_io_device *this,
363 gpa_t addr, int len, const void *val)
364{
365 struct kvm_pic *s = this->private;
366 unsigned char data = *(unsigned char *)val;
367
368 if (len != 1) {
369 if (printk_ratelimit())
370 printk(KERN_ERR "PIC: non byte write\n");
371 return;
372 }
373 switch (addr) {
374 case 0x20:
375 case 0x21:
376 case 0xa0:
377 case 0xa1:
378 pic_ioport_write(&s->pics[addr >> 7], addr, data);
379 break;
380 case 0x4d0:
381 case 0x4d1:
382 elcr_ioport_write(&s->pics[addr & 1], addr, data);
383 break;
384 }
385}
386
387static void picdev_read(struct kvm_io_device *this,
388 gpa_t addr, int len, void *val)
389{
390 struct kvm_pic *s = this->private;
391 unsigned char data = 0;
392
393 if (len != 1) {
394 if (printk_ratelimit())
395 printk(KERN_ERR "PIC: non byte read\n");
396 return;
397 }
398 switch (addr) {
399 case 0x20:
400 case 0x21:
401 case 0xa0:
402 case 0xa1:
403 data = pic_ioport_read(&s->pics[addr >> 7], addr);
404 break;
405 case 0x4d0:
406 case 0x4d1:
407 data = elcr_ioport_read(&s->pics[addr & 1], addr);
408 break;
409 }
410 *(unsigned char *)val = data;
411}
412
413/*
414 * callback when PIC0 irq status changed
415 */
416static void pic_irq_request(void *opaque, int level)
417{
418 struct kvm *kvm = opaque;
Eddie Dongb6958ce2007-07-18 12:15:21 +0300419 struct kvm_vcpu *vcpu = kvm->vcpus[0];
Eddie Dong85f455f2007-07-06 12:20:49 +0300420
421 pic_irqchip(kvm)->output = level;
Eddie Dongb6958ce2007-07-18 12:15:21 +0300422 if (vcpu)
423 kvm_vcpu_kick(vcpu);
Eddie Dong85f455f2007-07-06 12:20:49 +0300424}
425
426struct kvm_pic *kvm_create_pic(struct kvm *kvm)
427{
428 struct kvm_pic *s;
429 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
430 if (!s)
431 return NULL;
432 s->pics[0].elcr_mask = 0xf8;
433 s->pics[1].elcr_mask = 0xde;
434 s->irq_request = pic_irq_request;
435 s->irq_request_opaque = kvm;
436 s->pics[0].pics_state = s;
437 s->pics[1].pics_state = s;
438
439 /*
440 * Initialize PIO device
441 */
442 s->dev.read = picdev_read;
443 s->dev.write = picdev_write;
444 s->dev.in_range = picdev_in_range;
445 s->dev.private = s;
446 kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
447 return s;
448}