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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/************************************************************************
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -07002 * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 ************************************************************************/
13#ifndef _REGS_H
14#define _REGS_H
15
16#define TBD 0
17
18typedef struct _XENA_dev_config {
19/* Convention: mHAL_XXX is mask, vHAL_XXX is value */
20
21/* General Control-Status Registers */
22 u64 general_int_status;
23#define GEN_INTR_TXPIC BIT(0)
24#define GEN_INTR_TXDMA BIT(1)
25#define GEN_INTR_TXMAC BIT(2)
26#define GEN_INTR_TXXGXS BIT(3)
27#define GEN_INTR_TXTRAFFIC BIT(8)
28#define GEN_INTR_RXPIC BIT(32)
29#define GEN_INTR_RXDMA BIT(33)
30#define GEN_INTR_RXMAC BIT(34)
31#define GEN_INTR_MC BIT(35)
32#define GEN_INTR_RXXGXS BIT(36)
33#define GEN_INTR_RXTRAFFIC BIT(40)
34#define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
35 GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
36 GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
37 GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
38 GEN_INTR_MC
39
40 u64 general_int_mask;
41
42 u8 unused0[0x100 - 0x10];
43
44 u64 sw_reset;
45/* XGXS must be removed from reset only once. */
46#define SW_RESET_XENA vBIT(0xA5,0,8)
47#define SW_RESET_FLASH vBIT(0xA5,8,8)
48#define SW_RESET_EOI vBIT(0xA5,16,8)
49#define SW_RESET_ALL (SW_RESET_XENA | \
50 SW_RESET_FLASH | \
51 SW_RESET_EOI)
52/* The SW_RESET register must read this value after a successful reset. */
53#define SW_RESET_RAW_VAL 0xA5000000
54
55
56 u64 adapter_status;
57#define ADAPTER_STATUS_TDMA_READY BIT(0)
58#define ADAPTER_STATUS_RDMA_READY BIT(1)
59#define ADAPTER_STATUS_PFC_READY BIT(2)
60#define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3)
61#define ADAPTER_STATUS_PIC_QUIESCENT BIT(5)
62#define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6)
63#define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7)
64#define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8)
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -070065#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8)
Linus Torvalds1da177e2005-04-16 15:20:36 -070066#define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8)
67#define ADAPTER_STATUS_MC_DRAM_READY BIT(24)
68#define ADAPTER_STATUS_MC_QUEUES_READY BIT(25)
69#define ADAPTER_STATUS_M_PLL_LOCK BIT(30)
70#define ADAPTER_STATUS_P_PLL_LOCK BIT(31)
71
72 u64 adapter_control;
73#define ADAPTER_CNTL_EN BIT(7)
74#define ADAPTER_EOI_TX_ON BIT(15)
75#define ADAPTER_LED_ON BIT(23)
76#define ADAPTER_UDPI(val) vBIT(val,36,4)
77#define ADAPTER_WAIT_INT BIT(48)
78#define ADAPTER_ECC_EN BIT(55)
79
80 u64 serr_source;
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070081#define SERR_SOURCE_PIC BIT(0)
82#define SERR_SOURCE_TXDMA BIT(1)
83#define SERR_SOURCE_RXDMA BIT(2)
Linus Torvalds1da177e2005-04-16 15:20:36 -070084#define SERR_SOURCE_MAC BIT(3)
85#define SERR_SOURCE_MC BIT(4)
86#define SERR_SOURCE_XGXS BIT(5)
raghavendra.koushik@neterion.com20346722005-08-03 12:24:33 -070087#define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \
88 SERR_SOURCE_TXDMA | \
89 SERR_SOURCE_RXDMA | \
90 SERR_SOURCE_MAC | \
91 SERR_SOURCE_MC | \
92 SERR_SOURCE_XGXS)
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -070094 u64 pci_mode;
95#define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60)
96#define PCI_MODE_PCI_33 0
97#define PCI_MODE_PCI_66 0x1
98#define PCI_MODE_PCIX_M1_66 0x2
99#define PCI_MODE_PCIX_M1_100 0x3
100#define PCI_MODE_PCIX_M1_133 0x4
101#define PCI_MODE_PCIX_M2_66 0x5
102#define PCI_MODE_PCIX_M2_100 0x6
103#define PCI_MODE_PCIX_M2_133 0x7
104#define PCI_MODE_UNSUPPORTED BIT(0)
105#define PCI_MODE_32_BITS BIT(8)
106#define PCI_MODE_UNKNOWN_MODE BIT(9)
107
108 u8 unused_0[0x800 - 0x128];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109
110/* PCI-X Controller registers */
111 u64 pic_int_status;
112 u64 pic_int_mask;
113#define PIC_INT_TX BIT(0)
114#define PIC_INT_FLSH BIT(1)
115#define PIC_INT_MDIO BIT(2)
116#define PIC_INT_IIC BIT(3)
117#define PIC_INT_GPIO BIT(4)
118#define PIC_INT_RX BIT(32)
119
120 u64 txpic_int_reg;
121 u64 txpic_int_mask;
122#define PCIX_INT_REG_ECC_SG_ERR BIT(0)
123#define PCIX_INT_REG_ECC_DB_ERR BIT(1)
124#define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8)
125#define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9)
126#define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10)
127#define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11)
128#define PCIX_INT_REG_TRT_FSM_SERR BIT(13)
129#define PCIX_INT_REG_SRT_FSM_SERR BIT(14)
130#define PCIX_INT_REG_PIFR_FSM_SERR BIT(15)
131#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21)
132#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23)
133#define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48)
134#define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50)
135/*
136#define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52)
137#define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54)
138#define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58)
139*/
140 u64 txpic_alarms;
141 u64 rxpic_int_reg;
142 u64 rxpic_int_mask;
143 u64 rxpic_alarms;
144
145 u64 flsh_int_reg;
146 u64 flsh_int_mask;
147#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63)
148#define PIC_FLSH_INT_REG_ERR BIT(62)
149 u64 flash_alarms;
150
151 u64 mdio_int_reg;
152 u64 mdio_int_mask;
153#define MDIO_INT_REG_MDIO_BUS_ERR BIT(0)
154#define MDIO_INT_REG_DTX_BUS_ERR BIT(8)
155#define MDIO_INT_REG_LASI BIT(39)
156 u64 mdio_alarms;
157
158 u64 iic_int_reg;
159 u64 iic_int_mask;
160#define IIC_INT_REG_BUS_FSM_ERR BIT(4)
161#define IIC_INT_REG_BIT_FSM_ERR BIT(5)
162#define IIC_INT_REG_CYCLE_FSM_ERR BIT(6)
163#define IIC_INT_REG_REQ_FSM_ERR BIT(7)
164#define IIC_INT_REG_ACK_ERR BIT(8)
165 u64 iic_alarms;
166
167 u8 unused4[0x08];
168
169 u64 gpio_int_reg;
raghavendra.koushik@neterion.coma371a072005-08-03 12:38:59 -0700170#define GPIO_INT_REG_LINK_DOWN BIT(1)
171#define GPIO_INT_REG_LINK_UP BIT(2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700172 u64 gpio_int_mask;
raghavendra.koushik@neterion.coma371a072005-08-03 12:38:59 -0700173#define GPIO_INT_MASK_LINK_DOWN BIT(1)
174#define GPIO_INT_MASK_LINK_UP BIT(2)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 u64 gpio_alarms;
176
177 u8 unused5[0x38];
178
179 u64 tx_traffic_int;
180#define TX_TRAFFIC_INT_n(n) BIT(n)
181 u64 tx_traffic_mask;
182
183 u64 rx_traffic_int;
184#define RX_TRAFFIC_INT_n(n) BIT(n)
185 u64 rx_traffic_mask;
186
187/* PIC Control registers */
188 u64 pic_control;
189#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
190#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4)
191
192 u64 swapper_ctrl;
193#define SWAPPER_CTRL_PIF_R_FE BIT(0)
194#define SWAPPER_CTRL_PIF_R_SE BIT(1)
195#define SWAPPER_CTRL_PIF_W_FE BIT(8)
196#define SWAPPER_CTRL_PIF_W_SE BIT(9)
197#define SWAPPER_CTRL_TXP_FE BIT(16)
198#define SWAPPER_CTRL_TXP_SE BIT(17)
199#define SWAPPER_CTRL_TXD_R_FE BIT(18)
200#define SWAPPER_CTRL_TXD_R_SE BIT(19)
201#define SWAPPER_CTRL_TXD_W_FE BIT(20)
202#define SWAPPER_CTRL_TXD_W_SE BIT(21)
203#define SWAPPER_CTRL_TXF_R_FE BIT(22)
204#define SWAPPER_CTRL_TXF_R_SE BIT(23)
205#define SWAPPER_CTRL_RXD_R_FE BIT(32)
206#define SWAPPER_CTRL_RXD_R_SE BIT(33)
207#define SWAPPER_CTRL_RXD_W_FE BIT(34)
208#define SWAPPER_CTRL_RXD_W_SE BIT(35)
209#define SWAPPER_CTRL_RXF_W_FE BIT(36)
210#define SWAPPER_CTRL_RXF_W_SE BIT(37)
211#define SWAPPER_CTRL_XMSI_FE BIT(40)
212#define SWAPPER_CTRL_XMSI_SE BIT(41)
213#define SWAPPER_CTRL_STATS_FE BIT(48)
214#define SWAPPER_CTRL_STATS_SE BIT(49)
215
216 u64 pif_rd_swapper_fb;
217#define IF_RD_SWAPPER_FB 0x0123456789ABCDEF
218
219 u64 scheduled_int_ctrl;
220#define SCHED_INT_CTRL_TIMER_EN BIT(0)
221#define SCHED_INT_CTRL_ONE_SHOT BIT(1)
222#define SCHED_INT_CTRL_INT2MSI TBD
223#define SCHED_INT_PERIOD TBD
224
225 u64 txreqtimeout;
226#define TXREQTO_VAL(val) vBIT(val,0,32)
227#define TXREQTO_EN BIT(63)
228
229 u64 statsreqtimeout;
230#define STATREQTO_VAL(n) TBD
231#define STATREQTO_EN BIT(63)
232
233 u64 read_retry_delay;
234 u64 read_retry_acceleration;
235 u64 write_retry_delay;
236 u64 write_retry_acceleration;
237
238 u64 xmsi_control;
239 u64 xmsi_access;
240 u64 xmsi_address;
241 u64 xmsi_data;
242
243 u64 rx_mat;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700244#define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245
246 u8 unused6[0x8];
247
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700248 u64 tx_mat0_n[0x8];
249#define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700251 u8 unused_1[0x8];
252 u64 stat_byte_cnt;
253#define STAT_BC(n) vBIT(n,4,12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254
255 /* Automated statistics collection */
256 u64 stat_cfg;
257#define STAT_CFG_STAT_EN BIT(0)
258#define STAT_CFG_ONE_SHOT_EN BIT(1)
259#define STAT_CFG_STAT_NS_EN BIT(8)
260#define STAT_CFG_STAT_RO BIT(9)
261#define STAT_TRSF_PER(n) TBD
262#define PER_SEC 0x208d5
263#define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32)
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700264#define SET_UPDT_CLICKS(val) vBIT(val, 32, 32)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
266 u64 stat_addr;
267
268 /* General Configuration */
269 u64 mdio_control;
270
271 u64 dtx_control;
272
273 u64 i2c_control;
274#define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3)
275#define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11)
276#define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2)
277#define I2C_CONTROL_READ BIT(24)
278#define I2C_CONTROL_NACK BIT(25)
279#define I2C_CONTROL_CNTL_START vBIT(0xE,28,4)
280#define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4))
281#define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF)
282#define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32)
283
284 u64 gpio_control;
285#define GPIO_CTRL_GPIO_0 BIT(8)
raghavendra.koushik@neterion.coma371a072005-08-03 12:38:59 -0700286 u64 misc_control;
287#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700288
raghavendra.koushik@neterion.coma371a072005-08-03 12:38:59 -0700289 u8 unused7_1[0x240 - 0x208];
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700290
291 u64 wreq_split_mask;
292#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
293
294 u8 unused7_2[0x800 - 0x248];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
296/* TxDMA registers */
297 u64 txdma_int_status;
298 u64 txdma_int_mask;
299#define TXDMA_PFC_INT BIT(0)
300#define TXDMA_TDA_INT BIT(1)
301#define TXDMA_PCC_INT BIT(2)
302#define TXDMA_TTI_INT BIT(3)
303#define TXDMA_LSO_INT BIT(4)
304#define TXDMA_TPA_INT BIT(5)
305#define TXDMA_SM_INT BIT(6)
306 u64 pfc_err_reg;
307 u64 pfc_err_mask;
308 u64 pfc_err_alarm;
309
310 u64 tda_err_reg;
311 u64 tda_err_mask;
312 u64 tda_err_alarm;
313
314 u64 pcc_err_reg;
315#define PCC_FB_ECC_DB_ERR vBIT(0xFF, 16, 8)
raghavendra.koushik@neterion.com5e25b9d2005-08-03 12:27:09 -0700316#define PCC_ENABLE_FOUR vBIT(0x0F,0,8)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317
318 u64 pcc_err_mask;
319 u64 pcc_err_alarm;
320
321 u64 tti_err_reg;
322 u64 tti_err_mask;
323 u64 tti_err_alarm;
324
325 u64 lso_err_reg;
326 u64 lso_err_mask;
327 u64 lso_err_alarm;
328
329 u64 tpa_err_reg;
330 u64 tpa_err_mask;
331 u64 tpa_err_alarm;
332
333 u64 sm_err_reg;
334 u64 sm_err_mask;
335 u64 sm_err_alarm;
336
337 u8 unused8[0x100 - 0xB8];
338
339/* TxDMA arbiter */
340 u64 tx_dma_wrap_stat;
341
342/* Tx FIFO controller */
343#define X_MAX_FIFOS 8
344#define X_FIFO_MAX_LEN 0x1FFF /*8191 */
345 u64 tx_fifo_partition_0;
346#define TX_FIFO_PARTITION_EN BIT(0)
347#define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3)
348#define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13)
349#define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3)
350#define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 )
351
352 u64 tx_fifo_partition_1;
353#define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3)
354#define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13)
355#define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3)
356#define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13)
357
358 u64 tx_fifo_partition_2;
359#define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3)
360#define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13)
361#define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3)
362#define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13)
363
364 u64 tx_fifo_partition_3;
365#define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3)
366#define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13)
367#define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3)
368#define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13)
369
370#define TX_FIFO_PARTITION_PRI_0 0 /* highest */
371#define TX_FIFO_PARTITION_PRI_1 1
372#define TX_FIFO_PARTITION_PRI_2 2
373#define TX_FIFO_PARTITION_PRI_3 3
374#define TX_FIFO_PARTITION_PRI_4 4
375#define TX_FIFO_PARTITION_PRI_5 5
376#define TX_FIFO_PARTITION_PRI_6 6
377#define TX_FIFO_PARTITION_PRI_7 7 /* lowest */
378
379 u64 tx_w_round_robin_0;
380 u64 tx_w_round_robin_1;
381 u64 tx_w_round_robin_2;
382 u64 tx_w_round_robin_3;
383 u64 tx_w_round_robin_4;
384
385 u64 tti_command_mem;
386#define TTI_CMD_MEM_WE BIT(7)
387#define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
388#define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15)
389#define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6)
390
391 u64 tti_data1_mem;
392#define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26)
393#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2)
394#define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38)
395#define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39)
396#define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7)
397#define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7)
398#define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7)
399
400 u64 tti_data2_mem;
401#define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16)
402#define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16)
403#define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16)
404#define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16)
405
406/* Tx Protocol assist */
407 u64 tx_pa_cfg;
408#define TX_PA_CFG_IGNORE_FRM_ERR BIT(1)
409#define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
410#define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
411#define TX_PA_CFG_IGNORE_L2_ERR BIT(6)
412
413/* Recent add, used only debug purposes. */
414 u64 pcc_enable;
415
416 u8 unused9[0x700 - 0x178];
417
418 u64 txdma_debug_ctrl;
419
420 u8 unused10[0x1800 - 0x1708];
421
422/* RxDMA Registers */
423 u64 rxdma_int_status;
424 u64 rxdma_int_mask;
425#define RXDMA_INT_RC_INT_M BIT(0)
426#define RXDMA_INT_RPA_INT_M BIT(1)
427#define RXDMA_INT_RDA_INT_M BIT(2)
428#define RXDMA_INT_RTI_INT_M BIT(3)
429
430 u64 rda_err_reg;
431 u64 rda_err_mask;
432 u64 rda_err_alarm;
433
434 u64 rc_err_reg;
435 u64 rc_err_mask;
436 u64 rc_err_alarm;
437
438 u64 prc_pcix_err_reg;
439 u64 prc_pcix_err_mask;
440 u64 prc_pcix_err_alarm;
441
442 u64 rpa_err_reg;
443 u64 rpa_err_mask;
444 u64 rpa_err_alarm;
445
446 u64 rti_err_reg;
447 u64 rti_err_mask;
448 u64 rti_err_alarm;
449
450 u8 unused11[0x100 - 0x88];
451
452/* DMA arbiter */
453 u64 rx_queue_priority;
454#define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3)
455#define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3)
456#define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3)
457#define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3)
458#define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3)
459#define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3)
460#define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3)
461#define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3)
462
463#define RX_QUEUE_PRI_0 0 /* highest */
464#define RX_QUEUE_PRI_1 1
465#define RX_QUEUE_PRI_2 2
466#define RX_QUEUE_PRI_3 3
467#define RX_QUEUE_PRI_4 4
468#define RX_QUEUE_PRI_5 5
469#define RX_QUEUE_PRI_6 6
470#define RX_QUEUE_PRI_7 7 /* lowest */
471
472 u64 rx_w_round_robin_0;
473 u64 rx_w_round_robin_1;
474 u64 rx_w_round_robin_2;
475 u64 rx_w_round_robin_3;
476 u64 rx_w_round_robin_4;
477
478 /* Per-ring controller regs */
479#define RX_MAX_RINGS 8
480#if 0
481#define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */
482#define RX_MIN_RINGS_SZ 0x3F /* 63 */
483#endif
484 u64 prc_rxd0_n[RX_MAX_RINGS];
485 u64 prc_ctrl_n[RX_MAX_RINGS];
486#define PRC_CTRL_RC_ENABLED BIT(7)
487#define PRC_CTRL_RING_MODE (BIT(14)|BIT(15))
488#define PRC_CTRL_RING_MODE_1 vBIT(0,14,2)
489#define PRC_CTRL_RING_MODE_3 vBIT(1,14,2)
490#define PRC_CTRL_RING_MODE_5 vBIT(2,14,2)
491#define PRC_CTRL_RING_MODE_x vBIT(3,14,2)
492#define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23))
493#define PRC_CTRL_NO_SNOOP_DESC BIT(22)
494#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700495#define PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
497
498 u64 prc_alarm_action;
499#define PRC_ALARM_ACTION_RR_R0_STOP BIT(3)
500#define PRC_ALARM_ACTION_RW_R0_STOP BIT(7)
501#define PRC_ALARM_ACTION_RR_R1_STOP BIT(11)
502#define PRC_ALARM_ACTION_RW_R1_STOP BIT(15)
503#define PRC_ALARM_ACTION_RR_R2_STOP BIT(19)
504#define PRC_ALARM_ACTION_RW_R2_STOP BIT(23)
505#define PRC_ALARM_ACTION_RR_R3_STOP BIT(27)
506#define PRC_ALARM_ACTION_RW_R3_STOP BIT(31)
507#define PRC_ALARM_ACTION_RR_R4_STOP BIT(35)
508#define PRC_ALARM_ACTION_RW_R4_STOP BIT(39)
509#define PRC_ALARM_ACTION_RR_R5_STOP BIT(43)
510#define PRC_ALARM_ACTION_RW_R5_STOP BIT(47)
511#define PRC_ALARM_ACTION_RR_R6_STOP BIT(51)
512#define PRC_ALARM_ACTION_RW_R6_STOP BIT(55)
513#define PRC_ALARM_ACTION_RR_R7_STOP BIT(59)
514#define PRC_ALARM_ACTION_RW_R7_STOP BIT(63)
515
516/* Receive traffic interrupts */
517 u64 rti_command_mem;
518#define RTI_CMD_MEM_WE BIT(7)
519#define RTI_CMD_MEM_STROBE BIT(15)
520#define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15)
521#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15)
522#define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3)
523
524 u64 rti_data1_mem;
525#define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29)
526#define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38)
527#define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39)
528#define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7)
529#define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7)
530#define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7)
531
532 u64 rti_data2_mem;
533#define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16)
534#define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16)
535#define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16)
536#define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16)
537
538 u64 rx_pa_cfg;
539#define RX_PA_CFG_IGNORE_FRM_ERR BIT(1)
540#define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2)
541#define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3)
542#define RX_PA_CFG_IGNORE_L2_ERR BIT(6)
543
544 u8 unused12[0x700 - 0x1D8];
545
546 u64 rxdma_debug_ctrl;
547
548 u8 unused13[0x2000 - 0x1f08];
549
550/* Media Access Controller Register */
551 u64 mac_int_status;
552 u64 mac_int_mask;
553#define MAC_INT_STATUS_TMAC_INT BIT(0)
554#define MAC_INT_STATUS_RMAC_INT BIT(1)
555
556 u64 mac_tmac_err_reg;
557#define TMAC_ERR_REG_TMAC_ECC_DB_ERR BIT(15)
558#define TMAC_ERR_REG_TMAC_TX_BUF_OVRN BIT(23)
559#define TMAC_ERR_REG_TMAC_TX_CRI_ERR BIT(31)
560 u64 mac_tmac_err_mask;
561 u64 mac_tmac_err_alarm;
562
563 u64 mac_rmac_err_reg;
564#define RMAC_ERR_REG_RX_BUFF_OVRN BIT(0)
565#define RMAC_ERR_REG_RTS_ECC_DB_ERR BIT(14)
566#define RMAC_ERR_REG_ECC_DB_ERR BIT(15)
567#define RMAC_LINK_STATE_CHANGE_INT BIT(31)
568 u64 mac_rmac_err_mask;
569 u64 mac_rmac_err_alarm;
570
571 u8 unused14[0x100 - 0x40];
572
573 u64 mac_cfg;
574#define MAC_CFG_TMAC_ENABLE BIT(0)
575#define MAC_CFG_RMAC_ENABLE BIT(1)
576#define MAC_CFG_LAN_NOT_WAN BIT(2)
577#define MAC_CFG_TMAC_LOOPBACK BIT(3)
578#define MAC_CFG_TMAC_APPEND_PAD BIT(4)
579#define MAC_CFG_RMAC_STRIP_FCS BIT(5)
580#define MAC_CFG_RMAC_STRIP_PAD BIT(6)
581#define MAC_CFG_RMAC_PROM_ENABLE BIT(7)
582#define MAC_RMAC_DISCARD_PFRM BIT(8)
583#define MAC_RMAC_BCAST_ENABLE BIT(9)
584#define MAC_RMAC_ALL_ADDR_ENABLE BIT(10)
585#define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8)
586
587 u64 tmac_avg_ipg;
588#define TMAC_AVG_IPG(val) vBIT(val,0,8)
589
590 u64 rmac_max_pyld_len;
591#define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14)
592#define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14)
593#define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14)
594
595 u64 rmac_err_cfg;
596#define RMAC_ERR_FCS BIT(0)
597#define RMAC_ERR_FCS_ACCEPT BIT(1)
598#define RMAC_ERR_TOO_LONG BIT(1)
599#define RMAC_ERR_TOO_LONG_ACCEPT BIT(1)
600#define RMAC_ERR_RUNT BIT(2)
601#define RMAC_ERR_RUNT_ACCEPT BIT(2)
602#define RMAC_ERR_LEN_MISMATCH BIT(3)
603#define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3)
604
605 u64 rmac_cfg_key;
606#define RMAC_CFG_KEY(val) vBIT(val,0,16)
607
608#define MAX_MAC_ADDRESSES 16
609#define MAX_MC_ADDRESSES 32 /* Multicast addresses */
610#define MAC_MAC_ADDR_START_OFFSET 0
611#define MAC_MC_ADDR_START_OFFSET 16
612#define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */
613 u64 rmac_addr_cmd_mem;
614#define RMAC_ADDR_CMD_MEM_WE BIT(7)
615#define RMAC_ADDR_CMD_MEM_RD 0
616#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15)
617#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15)
618#define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6)
619
620 u64 rmac_addr_data0_mem;
621#define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48)
622#define RMAC_ADDR_DATA0_MEM_USER BIT(48)
623
624 u64 rmac_addr_data1_mem;
625#define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48)
626
627 u8 unused15[0x8];
628
629/*
630 u64 rmac_addr_cfg;
631#define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n)
632#define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n)
633#define RMAC_ADDR_BCAST_EN vBIT(0)_48
634#define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49
635*/
636 u64 tmac_ipg_cfg;
637
638 u64 rmac_pause_cfg;
639#define RMAC_PAUSE_GEN BIT(0)
640#define RMAC_PAUSE_GEN_ENABLE BIT(0)
641#define RMAC_PAUSE_RX BIT(1)
642#define RMAC_PAUSE_RX_ENABLE BIT(1)
643#define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16)
644#define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16)
645
646 u64 rmac_red_cfg;
647
648 u64 rmac_red_rate_q0q3;
649 u64 rmac_red_rate_q4q7;
650
651 u64 mac_link_util;
652#define MAC_TX_LINK_UTIL vBIT(0xFE,1,7)
653#define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4)
654#define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4)
655#define MAC_RX_LINK_UTIL vBIT(0xFE,33,7)
656#define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4)
657#define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4)
658
659#define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \
660 MAC_RX_LINK_UTIL_DISABLE
661
662 u64 rmac_invalid_ipg;
663
664/* rx traffic steering */
665#define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14)
666 u64 rts_frm_len_n[8];
667
668 u64 rts_qos_steering;
669
670#define MAX_DIX_MAP 4
671 u64 rts_dix_map_n[MAX_DIX_MAP];
672#define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16)
673#define RTS_DIX_MAP_SCW(val) BIT(val,21)
674
675 u64 rts_q_alternates;
676 u64 rts_default_q;
677
678 u64 rts_ctrl;
679#define RTS_CTRL_IGNORE_SNAP_OUI BIT(2)
680#define RTS_CTRL_IGNORE_LLC_CTRL BIT(3)
681
682 u64 rts_pn_cam_ctrl;
683#define RTS_PN_CAM_CTRL_WE BIT(7)
684#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15)
685#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15)
686#define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8)
687 u64 rts_pn_cam_data;
688#define RTS_PN_CAM_DATA_TCP_SELECT BIT(7)
689#define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16)
690#define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8)
691
692 u64 rts_ds_mem_ctrl;
693#define RTS_DS_MEM_CTRL_WE BIT(7)
694#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15)
695#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15)
696#define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6)
697 u64 rts_ds_mem_data;
698#define RTS_DS_MEM_DATA(n) vBIT(n,0,8)
699
700 u8 unused16[0x700 - 0x220];
701
702 u64 mac_debug_ctrl;
703#define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL
704
705 u8 unused17[0x2800 - 0x2708];
706
707/* memory controller registers */
708 u64 mc_int_status;
709#define MC_INT_STATUS_MC_INT BIT(0)
710 u64 mc_int_mask;
711#define MC_INT_MASK_MC_INT BIT(0)
712
713 u64 mc_err_reg;
714#define MC_ERR_REG_ECC_DB_ERR_L BIT(14)
715#define MC_ERR_REG_ECC_DB_ERR_U BIT(15)
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700716#define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18)
717#define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718#define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22)
719#define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23)
720#define MC_ERR_REG_SM_ERR BIT(31)
ravinandan.arakali@neterion.com776bd202005-09-06 21:36:56 -0700721#define MC_ERR_REG_ECC_ALL_SNG (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\
722 BIT(6) | BIT(7) | BIT(17) | BIT(19))
723#define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\
724 BIT(13) | BIT(14) | BIT(15) |\
725 BIT(18) | BIT(20))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 u64 mc_err_mask;
727 u64 mc_err_alarm;
728
729 u8 unused18[0x100 - 0x28];
730
731/* MC configuration */
732 u64 rx_queue_cfg;
733#define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8)
734#define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8)
735#define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8)
736#define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8)
737#define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8)
738#define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8)
739#define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8)
740#define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8)
741
742 u64 mc_rldram_mrs;
743#define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39)
744#define MC_RLDRAM_MRS_ENABLE BIT(47)
745
746 u64 mc_rldram_interleave;
747
748 u64 mc_pause_thresh_q0q3;
749 u64 mc_pause_thresh_q4q7;
750
751 u64 mc_red_thresh_q[8];
752
753 u8 unused19[0x200 - 0x168];
754 u64 mc_rldram_ref_per;
755 u8 unused20[0x220 - 0x208];
756 u64 mc_rldram_test_ctrl;
757#define MC_RLDRAM_TEST_MODE BIT(47)
758#define MC_RLDRAM_TEST_WRITE BIT(7)
759#define MC_RLDRAM_TEST_GO BIT(15)
760#define MC_RLDRAM_TEST_DONE BIT(23)
761#define MC_RLDRAM_TEST_PASS BIT(31)
762
763 u8 unused21[0x240 - 0x228];
764 u64 mc_rldram_test_add;
765 u8 unused22[0x260 - 0x248];
766 u64 mc_rldram_test_d0;
767 u8 unused23[0x280 - 0x268];
768 u64 mc_rldram_test_d1;
769 u8 unused24[0x300 - 0x288];
770 u64 mc_rldram_test_d2;
raghavendra.koushik@neterion.com541ae682005-08-03 12:36:55 -0700771
772 u8 unused24_1[0x360 - 0x308];
773 u64 mc_rldram_ctrl;
774#define MC_RLDRAM_ENABLE_ODT BIT(7)
775
776 u8 unused24_2[0x640 - 0x368];
777 u64 mc_rldram_ref_per_herc;
778#define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16)
779
780 u8 unused24_3[0x660 - 0x648];
781 u64 mc_rldram_mrs_herc;
782
783 u8 unused25[0x700 - 0x668];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784 u64 mc_debug_ctrl;
785
786 u8 unused26[0x3000 - 0x2f08];
787
788/* XGXG */
789 /* XGXS control registers */
790
791 u64 xgxs_int_status;
792#define XGXS_INT_STATUS_TXGXS BIT(0)
793#define XGXS_INT_STATUS_RXGXS BIT(1)
794 u64 xgxs_int_mask;
795#define XGXS_INT_MASK_TXGXS BIT(0)
796#define XGXS_INT_MASK_RXGXS BIT(1)
797
798 u64 xgxs_txgxs_err_reg;
799#define TXGXS_ECC_DB_ERR BIT(15)
800 u64 xgxs_txgxs_err_mask;
801 u64 xgxs_txgxs_err_alarm;
802
803 u64 xgxs_rxgxs_err_reg;
804 u64 xgxs_rxgxs_err_mask;
805 u64 xgxs_rxgxs_err_alarm;
806
807 u8 unused27[0x100 - 0x40];
808
809 u64 xgxs_cfg;
810 u64 xgxs_status;
811
812 u64 xgxs_cfg_key;
813 u64 xgxs_efifo_cfg; /* CHANGED */
814 u64 rxgxs_ber_0; /* CHANGED */
815 u64 rxgxs_ber_1; /* CHANGED */
816
ravinandan.arakali@neterion.comad4ebed2005-10-17 18:26:20 -0700817 u64 spi_control;
818#define SPI_CONTROL_KEY(key) vBIT(key,0,4)
819#define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3)
820#define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8)
821#define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24)
822#define SPI_CONTROL_SEL1 BIT(4)
823#define SPI_CONTROL_REQ BIT(7)
824#define SPI_CONTROL_NACK BIT(5)
825#define SPI_CONTROL_DONE BIT(6)
826 u64 spi_data;
827#define SPI_DATA_WRITE(data,len) vBIT(data,0,len)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828} XENA_dev_config_t;
829
830#define XENA_REG_SPACE sizeof(XENA_dev_config_t)
831#define XENA_EEPROM_SPACE (0x01 << 11)
832
833#endif /* _REGS_H */