blob: 634bf1d3a311d13360c32c269fedbe81e146d3fd [file] [log] [blame]
Russell King59ac59f2010-02-11 21:56:07 +00001/*
2 * linux/arch/arm/mach-vexpress/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/errno.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/jiffies.h>
16#include <linux/smp.h>
17#include <linux/io.h>
18
19#include <asm/cacheflush.h>
Russell King59ac59f2010-02-11 21:56:07 +000020#include <asm/smp_scu.h>
21#include <asm/unified.h>
22
23#include <mach/ct-ca9x4.h>
24#include <mach/motherboard.h>
25#define V2M_PA_CS7 0x10000000
26
27#include "core.h"
28
29extern void vexpress_secondary_startup(void);
30
31/*
32 * control for which core is the next to come out of the secondary
33 * boot "holding pen"
34 */
35volatile int __cpuinitdata pen_release = -1;
36
Russell King3705ff62010-12-18 10:53:12 +000037/*
38 * Write pen_release in a way that is guaranteed to be visible to all
39 * observers, irrespective of whether they're taking part in coherency
40 * or not. This is necessary for the hotplug code to work reliably.
41 */
Russell Kingec150382011-01-22 17:22:34 +000042static void __cpuinit write_pen_release(int val)
Russell King3705ff62010-12-18 10:53:12 +000043{
44 pen_release = val;
45 smp_wmb();
46 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
47 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
48}
49
Russell King59ac59f2010-02-11 21:56:07 +000050static void __iomem *scu_base_addr(void)
51{
52 return MMIO_P2V(A9_MPCORE_SCU);
53}
54
55static DEFINE_SPINLOCK(boot_lock);
56
57void __cpuinit platform_secondary_init(unsigned int cpu)
58{
Russell King59ac59f2010-02-11 21:56:07 +000059 /*
60 * if any interrupts are already enabled for the primary
61 * core (e.g. timer irq), then they will not have been enabled
62 * for us: do so
63 */
Russell King38489532010-12-04 16:01:03 +000064 gic_secondary_init(0);
Russell King59ac59f2010-02-11 21:56:07 +000065
66 /*
67 * let the primary processor know we're out of the
68 * pen, then head off into the C entry point
69 */
Russell King3705ff62010-12-18 10:53:12 +000070 write_pen_release(-1);
Russell King59ac59f2010-02-11 21:56:07 +000071
72 /*
73 * Synchronise with the boot thread.
74 */
75 spin_lock(&boot_lock);
76 spin_unlock(&boot_lock);
77}
78
79int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
80{
81 unsigned long timeout;
82
83 /*
84 * Set synchronisation state between this boot processor
85 * and the secondary one
86 */
87 spin_lock(&boot_lock);
88
89 /*
90 * This is really belt and braces; we hold unintended secondary
91 * CPUs in the holding pen until we're ready for them. However,
92 * since we haven't sent them a soft interrupt, they shouldn't
93 * be there.
94 */
Russell King3705ff62010-12-18 10:53:12 +000095 write_pen_release(cpu);
Russell King59ac59f2010-02-11 21:56:07 +000096
97 /*
98 * Send the secondary CPU a soft interrupt, thereby causing
99 * the boot monitor to read the system wide flags register,
100 * and branch to the address found there.
101 */
Russell Kingad3b6992010-11-15 09:42:08 +0000102 smp_cross_call(cpumask_of(cpu), 1);
Russell King59ac59f2010-02-11 21:56:07 +0000103
104 timeout = jiffies + (1 * HZ);
105 while (time_before(jiffies, timeout)) {
106 smp_rmb();
107 if (pen_release == -1)
108 break;
109
110 udelay(10);
111 }
112
113 /*
114 * now the secondary core is starting up let it run its
115 * calibrations, then wait for it to finish
116 */
117 spin_unlock(&boot_lock);
118
119 return pen_release != -1 ? -ENOSYS : 0;
120}
121
122/*
123 * Initialise the CPU possible map early - this describes the CPUs
124 * which may be present or become present in the system.
125 */
126void __init smp_init_cpus(void)
127{
128 void __iomem *scu_base = scu_base_addr();
129 unsigned int i, ncores;
130
131 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
132
133 /* sanity check */
Russell King59ac59f2010-02-11 21:56:07 +0000134 if (ncores > NR_CPUS) {
135 printk(KERN_WARNING
136 "vexpress: no. of cores (%d) greater than configured "
137 "maximum of %d - clipping\n",
138 ncores, NR_CPUS);
139 ncores = NR_CPUS;
140 }
141
142 for (i = 0; i < ncores; i++)
143 set_cpu_possible(i, true);
144}
145
Russell King05c74a62010-12-03 11:09:48 +0000146void __init platform_smp_prepare_cpus(unsigned int max_cpus)
Russell King59ac59f2010-02-11 21:56:07 +0000147{
Russell King59ac59f2010-02-11 21:56:07 +0000148 int i;
149
Russell King59ac59f2010-02-11 21:56:07 +0000150 /*
151 * Initialise the present map, which describes the set of CPUs
152 * actually populated at the present time.
153 */
154 for (i = 0; i < max_cpus; i++)
155 set_cpu_present(i, true);
156
Russell King05c74a62010-12-03 11:09:48 +0000157 scu_enable(scu_base_addr());
158
Russell King59ac59f2010-02-11 21:56:07 +0000159 /*
Russell King05c74a62010-12-03 11:09:48 +0000160 * Write the address of secondary startup into the
161 * system-wide flags register. The boot monitor waits
162 * until it receives a soft interrupt, and then the
163 * secondary CPU branches to this address.
Russell King59ac59f2010-02-11 21:56:07 +0000164 */
Russell King05c74a62010-12-03 11:09:48 +0000165 writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
166 writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
167 MMIO_P2V(V2M_SYS_FLAGSSET));
Russell King59ac59f2010-02-11 21:56:07 +0000168}