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gerrit-public.fairphone.software / kernel / msm-4.9 / ec3bebc6ec64aac23500e6b8ef5c0aaaeda735cf / . / arch / arm / plat-omap / include / plat / omap-serial.h
blob: 348c9ead6edb1b6cffa9ea94d03f766496eba4c9 [file] [log] [blame]
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef __OMAP_SERIAL_H__
18#define __OMAP_SERIAL_H__
19
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]23#include <plat/mux.h>
24
Benoit Cousson374b8cf2010-12-09 14:24:17 +0000[diff] [blame]25#define DRIVER_NAME "omap_uart"
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]26
27/*
28 * Use tty device name as ttyO, [O -> OMAP]
29 * in bootargs we specify as console=ttyO0 if uart1
30 * is used as console uart.
31 */
32#define OMAP_SERIAL_NAME "ttyO"
33
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]34#define OMAP_MODE13X_SPEED 230400
35
Govindraj.R32212892011-11-07 18:58:55 +0530[diff] [blame]36#define OMAP_UART_SCR_TX_EMPTY 0x08
37
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]38/* WER = 0x7F
39 * Enable module level wakeup in WER reg
40 */
41#define OMAP_UART_WER_MOD_WKUP 0X7F
42
43/* Enable XON/XOFF flow control on output */
44#define OMAP_UART_SW_TX 0x04
45
46/* Enable XON/XOFF flow control on input */
47#define OMAP_UART_SW_RX 0x04
48
49#define OMAP_UART_SYSC_RESET 0X07
50#define OMAP_UART_TCR_TRIG 0X0F
51#define OMAP_UART_SW_CLR 0XF0
52#define OMAP_UART_FIFO_CLR 0X06
53
54#define OMAP_UART_DMA_CH_FREE -1
55
56#define RX_TIMEOUT (3 * HZ)
57#define OMAP_MAX_HSUART_PORTS 4
58
59#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
60
61struct omap_uart_port_info {
62 bool dma_enabled; /* To specify DMA Mode */
63 unsigned int uartclk; /* UART clock rate */
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]64 upf_t flags; /* UPF_* flags */
Govindraj.Rec3bebc2011-10-11 19:11:27 +0530[diff] [blame^]65
66 int (*get_context_loss_count)(struct device *);
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]67};
68
69struct uart_omap_dma {
70 u8 uart_dma_tx;
71 u8 uart_dma_rx;
72 int rx_dma_channel;
73 int tx_dma_channel;
74 dma_addr_t rx_buf_dma_phys;
75 dma_addr_t tx_buf_dma_phys;
76 unsigned int uart_base;
77 /*
78 * Buffer for rx dma.It is not required for tx because the buffer
79 * comes from port structure.
80 */
81 unsigned char *rx_buf;
82 unsigned int prev_rx_dma_pos;
83 int tx_buf_size;
84 int tx_dma_used;
85 int rx_dma_used;
86 spinlock_t tx_lock;
87 spinlock_t rx_lock;
88 /* timer to poll activity on rx dma */
89 struct timer_list rx_timer;
90 int rx_buf_size;
91 int rx_timeout;
92};
93
94struct uart_omap_port {
95 struct uart_port port;
96 struct uart_omap_dma uart_dma;
97 struct platform_device *pdev;
98
99 unsigned char ier;
100 unsigned char lcr;
101 unsigned char mcr;
102 unsigned char fcr;
103 unsigned char efr;
Govindraj.Rc538d202011-11-07 18:57:03 +0530[diff] [blame]104 unsigned char dll;
105 unsigned char dlh;
106 unsigned char mdr1;
107 unsigned char scr;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]108
109 int use_dma;
110 /*
111 * Some bits in registers are cleared on a read, so they must
112 * be saved whenever the register is read but the bits will not
113 * be immediately processed.
114 */
115 unsigned int lsr_break_flag;
116 unsigned char msr_saved_flags;
117 char name[20];
118 unsigned long port_activity;
Govindraj.Rec3bebc2011-10-11 19:11:27 +0530[diff] [blame^]119 u32 context_loss_cnt;
Govindraj.Rb6126332010-09-27 20:20:49 +0530[diff] [blame]120};
121
122#endif /* __OMAP_SERIAL_H__ */