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Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +08001/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 model = "Atmel AT91SAM9263 family SoC";
13 compatible = "atmel,at91sam9263";
14 interrupt-parent = <&aic>;
15
16 aliases {
17 serial0 = &dbgu;
18 serial1 = &usart0;
19 serial2 = &usart1;
20 serial3 = &usart2;
21 gpio0 = &pioA;
22 gpio1 = &pioB;
23 gpio2 = &pioC;
24 gpio3 = &pioD;
25 gpio4 = &pioE;
26 tcb0 = &tcb0;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020027 i2c0 = &i2c0;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080028 };
29 cpus {
30 cpu@0 {
31 compatible = "arm,arm926ejs";
32 };
33 };
34
35 memory {
36 reg = <0x20000000 0x08000000>;
37 };
38
39 ahb {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 apb {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges;
50
51 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020052 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080053 compatible = "atmel,at91rm9200-aic";
54 interrupt-controller;
55 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080056 atmel,external-irqs = <30 31>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080057 };
58
59 pmc: pmc@fffffc00 {
60 compatible = "atmel,at91rm9200-pmc";
61 reg = <0xfffffc00 0x100>;
62 };
63
64 ramc: ramc@ffffe200 {
65 compatible = "atmel,at91sam9260-sdramc";
66 reg = <0xffffe200 0x200
67 0xffffe800 0x200>;
68 };
69
70 pit: timer@fffffd30 {
71 compatible = "atmel,at91sam9260-pit";
72 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020073 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080074 };
75
76 tcb0: timer@fff7c000 {
77 compatible = "atmel,at91rm9200-tcb";
78 reg = <0xfff7c000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020079 interrupts = <19 4 0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080080 };
81
82 rstc@fffffd00 {
83 compatible = "atmel,at91sam9260-rstc";
84 reg = <0xfffffd00 0x10>;
85 };
86
87 shdwc@fffffd10 {
88 compatible = "atmel,at91sam9260-shdwc";
89 reg = <0xfffffd10 0x10>;
90 };
91
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +080092 pinctrl@fffff200 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
96 ranges = <0xfffff200 0xfffff200 0xa00>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080097
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +080098 atmel,mux-mask = <
99 /* A B */
100 0xfffffffb 0xffffe07f /* pioA */
101 0x0007ffff 0x39072fff /* pioB */
102 0xffffffff 0x3ffffff8 /* pioC */
103 0xfffffbff 0xffffffff /* pioD */
104 0xffe00fff 0xfbfcff00 /* pioE */
105 >;
106
107 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800108 dbgu {
109 pinctrl_dbgu: dbgu-0 {
110 atmel,pins =
111 <2 30 0x1 0x0 /* PC30 periph A */
112 2 31 0x1 0x1>; /* PC31 periph with pullup */
113 };
114 };
115
116 uart0 {
117 pinctrl_uart0: uart0-0 {
118 atmel,pins =
119 <0 26 0x1 0x1 /* PA26 periph A with pullup */
120 0 27 0x1 0x0>; /* PA27 periph A */
121 };
122
123 pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
124 atmel,pins =
125 <0 28 0x1 0x0 /* PA28 periph A */
126 0 29 0x1 0x0>; /* PA29 periph A */
127 };
128 };
129
130 uart1 {
131 pinctrl_uart1: uart1-0 {
132 atmel,pins =
133 <3 0 0x1 0x1 /* PD0 periph A with pullup */
134 3 1 0x1 0x0>; /* PD1 periph A */
135 };
136
137 pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
138 atmel,pins =
139 <3 7 0x2 0x0 /* PD7 periph B */
140 3 8 0x2 0x0>; /* PD8 periph B */
141 };
142 };
143
144 uart2 {
145 pinctrl_uart2: uart2-0 {
146 atmel,pins =
147 <3 2 0x1 0x1 /* PD2 periph A with pullup */
148 3 3 0x1 0x0>; /* PD3 periph A */
149 };
150
151 pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
152 atmel,pins =
153 <3 5 0x2 0x0 /* PD5 periph B */
154 4 6 0x2 0x0>; /* PD6 periph B */
155 };
156 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800157
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800158 pioA: gpio@fffff200 {
159 compatible = "atmel,at91rm9200-gpio";
160 reg = <0xfffff200 0x200>;
161 interrupts = <2 4 1>;
162 #gpio-cells = <2>;
163 gpio-controller;
164 interrupt-controller;
165 #interrupt-cells = <2>;
166 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800167
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800168 pioB: gpio@fffff400 {
169 compatible = "atmel,at91rm9200-gpio";
170 reg = <0xfffff400 0x200>;
171 interrupts = <3 4 1>;
172 #gpio-cells = <2>;
173 gpio-controller;
174 interrupt-controller;
175 #interrupt-cells = <2>;
176 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800177
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800178 pioC: gpio@fffff600 {
179 compatible = "atmel,at91rm9200-gpio";
180 reg = <0xfffff600 0x200>;
181 interrupts = <4 4 1>;
182 #gpio-cells = <2>;
183 gpio-controller;
184 interrupt-controller;
185 #interrupt-cells = <2>;
186 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800187
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800188 pioD: gpio@fffff800 {
189 compatible = "atmel,at91rm9200-gpio";
190 reg = <0xfffff800 0x200>;
191 interrupts = <4 4 1>;
192 #gpio-cells = <2>;
193 gpio-controller;
194 interrupt-controller;
195 #interrupt-cells = <2>;
196 };
197
198 pioE: gpio@fffffa00 {
199 compatible = "atmel,at91rm9200-gpio";
200 reg = <0xfffffa00 0x200>;
201 interrupts = <4 4 1>;
202 #gpio-cells = <2>;
203 gpio-controller;
204 interrupt-controller;
205 #interrupt-cells = <2>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800206 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800207 };
208
209 dbgu: serial@ffffee00 {
210 compatible = "atmel,at91sam9260-usart";
211 reg = <0xffffee00 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200212 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800215 status = "disabled";
216 };
217
218 usart0: serial@fff8c000 {
219 compatible = "atmel,at91sam9260-usart";
220 reg = <0xfff8c000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200221 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800222 atmel,use-dma-rx;
223 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_uart0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800226 status = "disabled";
227 };
228
229 usart1: serial@fff90000 {
230 compatible = "atmel,at91sam9260-usart";
231 reg = <0xfff90000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200232 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800233 atmel,use-dma-rx;
234 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800237 status = "disabled";
238 };
239
240 usart2: serial@fff94000 {
241 compatible = "atmel,at91sam9260-usart";
242 reg = <0xfff94000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200243 interrupts = <9 4 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800244 atmel,use-dma-rx;
245 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800248 status = "disabled";
249 };
250
251 macb0: ethernet@fffbc000 {
252 compatible = "cdns,at32ap7000-macb", "cdns,macb";
253 reg = <0xfffbc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200254 interrupts = <21 4 3>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800255 status = "disabled";
256 };
257
258 usb1: gadget@fff78000 {
259 compatible = "atmel,at91rm9200-udc";
260 reg = <0xfff78000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200261 interrupts = <24 4 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800262 status = "disabled";
263 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200264
265 i2c0: i2c@fff88000 {
266 compatible = "atmel,at91sam9263-i2c";
267 reg = <0xfff88000 0x100>;
268 interrupts = <13 4 6>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800273 };
274
275 nand0: nand@40000000 {
276 compatible = "atmel,at91rm9200-nand";
277 #address-cells = <1>;
278 #size-cells = <1>;
279 reg = <0x40000000 0x10000000
280 0xffffe000 0x200
281 >;
282 atmel,nand-addr-offset = <21>;
283 atmel,nand-cmd-offset = <22>;
284 gpios = <&pioA 22 0
285 &pioD 15 0
286 0
287 >;
288 status = "disabled";
289 };
290
291 usb0: ohci@00a00000 {
292 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
293 reg = <0x00a00000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200294 interrupts = <29 4 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800295 status = "disabled";
296 };
297 };
298
299 i2c@0 {
300 compatible = "i2c-gpio";
301 gpios = <&pioB 4 0 /* sda */
302 &pioB 5 0 /* scl */
303 >;
304 i2c-gpio,sda-open-drain;
305 i2c-gpio,scl-open-drain;
306 i2c-gpio,delay-us = <2>; /* ~100 kHz */
307 #address-cells = <1>;
308 #size-cells = <0>;
309 status = "disabled";
310 };
311};