| Hariram Purushothaman | dc4402e | 2017-03-28 20:41:43 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _CAM_HW_CDM170_REG_H_ |
| 14 | #define _CAM_HW_CDM170_REG_H_ |
| 15 | |
| 16 | #define CAM_CDM_REG_OFFSET_FIRST 0x0 |
| 17 | #define CAM_CDM_REG_OFFSET_LAST 0x200 |
| 18 | #define CAM_CDM_REGS_COUNT 0x30 |
| 19 | #define CAM_CDM_HWFIFO_SIZE 0x40 |
| 20 | |
| 21 | #define CAM_CDM_OFFSET_HW_VERSION 0x0 |
| 22 | #define CAM_CDM_OFFSET_TITAN_VERSION 0x4 |
| 23 | #define CAM_CDM_OFFSET_RST_CMD 0x10 |
| 24 | #define CAM_CDM_OFFSET_CGC_CFG 0x14 |
| 25 | #define CAM_CDM_OFFSET_CORE_CFG 0x18 |
| 26 | #define CAM_CDM_OFFSET_CORE_EN 0x1c |
| 27 | #define CAM_CDM_OFFSET_FE_CFG 0x20 |
| 28 | #define CAM_CDM_OFFSET_IRQ_MASK 0x30 |
| 29 | #define CAM_CDM_OFFSET_IRQ_CLEAR 0x34 |
| 30 | #define CAM_CDM_OFFSET_IRQ_CLEAR_CMD 0x38 |
| 31 | #define CAM_CDM_OFFSET_IRQ_SET 0x3c |
| 32 | #define CAM_CDM_OFFSET_IRQ_SET_CMD 0x40 |
| 33 | |
| 34 | #define CAM_CDM_OFFSET_IRQ_STATUS 0x44 |
| 35 | #define CAM_CDM_IRQ_STATUS_INFO_RST_DONE_MASK 0x1 |
| 36 | #define CAM_CDM_IRQ_STATUS_INFO_INLINE_IRQ_MASK 0x2 |
| 37 | #define CAM_CDM_IRQ_STATUS_INFO_BL_DONE_MASK 0x4 |
| 38 | #define CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000 |
| 39 | #define CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000 |
| 40 | #define CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000 |
| 41 | |
| 42 | #define CAM_CDM_OFFSET_BL_FIFO_BASE_REG 0x50 |
| 43 | #define CAM_CDM_OFFSET_BL_FIFO_LEN_REG 0x54 |
| 44 | #define CAM_CDM_OFFSET_BL_FIFO_STORE_REG 0x58 |
| 45 | #define CAM_CDM_OFFSET_BL_FIFO_CFG 0x5c |
| 46 | #define CAM_CDM_OFFSET_BL_FIFO_RB 0x60 |
| 47 | #define CAM_CDM_OFFSET_BL_FIFO_BASE_RB 0x64 |
| 48 | #define CAM_CDM_OFFSET_BL_FIFO_LEN_RB 0x68 |
| 49 | #define CAM_CDM_OFFSET_BL_FIFO_PENDING_REQ_RB 0x6c |
| 50 | #define CAM_CDM_OFFSET_IRQ_USR_DATA 0x80 |
| 51 | #define CAM_CDM_OFFSET_WAIT_STATUS 0x84 |
| 52 | #define CAM_CDM_OFFSET_SCRATCH_0_REG 0x90 |
| 53 | #define CAM_CDM_OFFSET_SCRATCH_1_REG 0x94 |
| 54 | #define CAM_CDM_OFFSET_SCRATCH_2_REG 0x98 |
| 55 | #define CAM_CDM_OFFSET_SCRATCH_3_REG 0x9c |
| 56 | #define CAM_CDM_OFFSET_SCRATCH_4_REG 0xa0 |
| 57 | #define CAM_CDM_OFFSET_SCRATCH_5_REG 0xa4 |
| 58 | #define CAM_CDM_OFFSET_SCRATCH_6_REG 0xa8 |
| 59 | #define CAM_CDM_OFFSET_SCRATCH_7_REG 0xac |
| 60 | #define CAM_CDM_OFFSET_LAST_AHB_ADDR 0xd0 |
| 61 | #define CAM_CDM_OFFSET_LAST_AHB_DATA 0xd4 |
| 62 | #define CAM_CDM_OFFSET_CORE_DBUG 0xd8 |
| 63 | #define CAM_CDM_OFFSET_LAST_AHB_ERR_ADDR 0xe0 |
| 64 | #define CAM_CDM_OFFSET_LAST_AHB_ERR_DATA 0xe4 |
| 65 | #define CAM_CDM_OFFSET_CURRENT_BL_BASE 0xe8 |
| 66 | #define CAM_CDM_OFFSET_CURRENT_BL_LEN 0xec |
| 67 | #define CAM_CDM_OFFSET_CURRENT_USED_AHB_BASE 0xf0 |
| 68 | #define CAM_CDM_OFFSET_DEBUG_STATUS 0xf4 |
| 69 | #define CAM_CDM_OFFSET_BUS_MISR_CFG_0 0x100 |
| 70 | #define CAM_CDM_OFFSET_BUS_MISR_CFG_1 0x104 |
| 71 | #define CAM_CDM_OFFSET_BUS_MISR_RD_VAL 0x108 |
| 72 | #define CAM_CDM_OFFSET_PERF_MON_CTRL 0x110 |
| 73 | #define CAM_CDM_OFFSET_PERF_MON_0 0x114 |
| 74 | #define CAM_CDM_OFFSET_PERF_MON_1 0x118 |
| 75 | #define CAM_CDM_OFFSET_PERF_MON_2 0x11c |
| 76 | #define CAM_CDM_OFFSET_SPARE 0x200 |
| 77 | |
| 78 | /* |
| 79 | * Always make sure below register offsets are aligned with |
| 80 | * enum cam_cdm_regs offsets |
| 81 | */ |
| 82 | struct cam_cdm_reg_offset cam170_cpas_cdm_register_offsets[] = { |
| 83 | { CAM_CDM_OFFSET_HW_VERSION, CAM_REG_ATTR_READ }, |
| 84 | { CAM_CDM_OFFSET_TITAN_VERSION, CAM_REG_ATTR_READ }, |
| 85 | { CAM_CDM_OFFSET_RST_CMD, CAM_REG_ATTR_WRITE }, |
| 86 | { CAM_CDM_OFFSET_CGC_CFG, CAM_REG_ATTR_READ_WRITE }, |
| 87 | { CAM_CDM_OFFSET_CORE_CFG, CAM_REG_ATTR_READ_WRITE }, |
| 88 | { CAM_CDM_OFFSET_CORE_EN, CAM_REG_ATTR_READ_WRITE }, |
| 89 | { CAM_CDM_OFFSET_FE_CFG, CAM_REG_ATTR_READ_WRITE }, |
| 90 | { CAM_CDM_OFFSET_IRQ_MASK, CAM_REG_ATTR_READ_WRITE }, |
| 91 | { CAM_CDM_OFFSET_IRQ_CLEAR, CAM_REG_ATTR_READ_WRITE }, |
| 92 | { CAM_CDM_OFFSET_IRQ_CLEAR_CMD, CAM_REG_ATTR_WRITE }, |
| 93 | { CAM_CDM_OFFSET_IRQ_SET, CAM_REG_ATTR_READ_WRITE }, |
| 94 | { CAM_CDM_OFFSET_IRQ_SET_CMD, CAM_REG_ATTR_WRITE }, |
| 95 | { CAM_CDM_OFFSET_IRQ_STATUS, CAM_REG_ATTR_READ }, |
| 96 | { CAM_CDM_OFFSET_IRQ_USR_DATA, CAM_REG_ATTR_READ_WRITE }, |
| 97 | { CAM_CDM_OFFSET_BL_FIFO_BASE_REG, CAM_REG_ATTR_READ_WRITE }, |
| 98 | { CAM_CDM_OFFSET_BL_FIFO_LEN_REG, CAM_REG_ATTR_READ_WRITE }, |
| 99 | { CAM_CDM_OFFSET_BL_FIFO_STORE_REG, CAM_REG_ATTR_WRITE }, |
| 100 | { CAM_CDM_OFFSET_BL_FIFO_CFG, CAM_REG_ATTR_READ_WRITE }, |
| 101 | { CAM_CDM_OFFSET_BL_FIFO_RB, CAM_REG_ATTR_READ_WRITE }, |
| 102 | { CAM_CDM_OFFSET_BL_FIFO_BASE_RB, CAM_REG_ATTR_READ }, |
| 103 | { CAM_CDM_OFFSET_BL_FIFO_LEN_RB, CAM_REG_ATTR_READ }, |
| 104 | { CAM_CDM_OFFSET_BL_FIFO_PENDING_REQ_RB, CAM_REG_ATTR_READ }, |
| 105 | { CAM_CDM_OFFSET_WAIT_STATUS, CAM_REG_ATTR_READ }, |
| 106 | { CAM_CDM_OFFSET_SCRATCH_0_REG, CAM_REG_ATTR_READ_WRITE }, |
| 107 | { CAM_CDM_OFFSET_SCRATCH_1_REG, CAM_REG_ATTR_READ_WRITE }, |
| 108 | { CAM_CDM_OFFSET_SCRATCH_2_REG, CAM_REG_ATTR_READ_WRITE }, |
| 109 | { CAM_CDM_OFFSET_SCRATCH_3_REG, CAM_REG_ATTR_READ_WRITE }, |
| 110 | { CAM_CDM_OFFSET_SCRATCH_4_REG, CAM_REG_ATTR_READ_WRITE }, |
| 111 | { CAM_CDM_OFFSET_SCRATCH_5_REG, CAM_REG_ATTR_READ_WRITE }, |
| 112 | { CAM_CDM_OFFSET_SCRATCH_6_REG, CAM_REG_ATTR_READ_WRITE }, |
| 113 | { CAM_CDM_OFFSET_SCRATCH_7_REG, CAM_REG_ATTR_READ_WRITE }, |
| 114 | { CAM_CDM_OFFSET_LAST_AHB_ADDR, CAM_REG_ATTR_READ }, |
| 115 | { CAM_CDM_OFFSET_LAST_AHB_DATA, CAM_REG_ATTR_READ }, |
| 116 | { CAM_CDM_OFFSET_CORE_DBUG, CAM_REG_ATTR_READ_WRITE }, |
| 117 | { CAM_CDM_OFFSET_LAST_AHB_ERR_ADDR, CAM_REG_ATTR_READ }, |
| 118 | { CAM_CDM_OFFSET_LAST_AHB_ERR_DATA, CAM_REG_ATTR_READ }, |
| 119 | { CAM_CDM_OFFSET_CURRENT_BL_BASE, CAM_REG_ATTR_READ }, |
| 120 | { CAM_CDM_OFFSET_CURRENT_BL_LEN, CAM_REG_ATTR_READ }, |
| 121 | { CAM_CDM_OFFSET_CURRENT_USED_AHB_BASE, CAM_REG_ATTR_READ }, |
| 122 | { CAM_CDM_OFFSET_DEBUG_STATUS, CAM_REG_ATTR_READ }, |
| 123 | { CAM_CDM_OFFSET_BUS_MISR_CFG_0, CAM_REG_ATTR_READ_WRITE }, |
| 124 | { CAM_CDM_OFFSET_BUS_MISR_CFG_1, CAM_REG_ATTR_READ_WRITE }, |
| 125 | { CAM_CDM_OFFSET_BUS_MISR_RD_VAL, CAM_REG_ATTR_READ }, |
| 126 | { CAM_CDM_OFFSET_PERF_MON_CTRL, CAM_REG_ATTR_READ_WRITE }, |
| 127 | { CAM_CDM_OFFSET_PERF_MON_0, CAM_REG_ATTR_READ }, |
| 128 | { CAM_CDM_OFFSET_PERF_MON_1, CAM_REG_ATTR_READ }, |
| 129 | { CAM_CDM_OFFSET_PERF_MON_2, CAM_REG_ATTR_READ }, |
| 130 | { CAM_CDM_OFFSET_SPARE, CAM_REG_ATTR_READ_WRITE } |
| 131 | }; |
| 132 | |
| 133 | struct cam_cdm_reg_offset_table cam170_cpas_cdm_offset_table = { |
| 134 | .first_offset = 0x0, |
| 135 | .last_offset = 0x200, |
| 136 | .reg_count = 0x30, |
| 137 | .offsets = cam170_cpas_cdm_register_offsets, |
| 138 | .offset_max_size = (sizeof(cam170_cpas_cdm_register_offsets)/ |
| 139 | sizeof(struct cam_cdm_reg_offset)), |
| 140 | }; |
| 141 | |
| 142 | #endif /* _CAM_HW_CDM170_REG_H_ */ |