Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Steven J. Hill | 49bffbd | 2013-03-25 15:05:40 -0500 | [diff] [blame] | 2 | * This file is subject to the terms and conditions of the GNU General Public |
| 3 | * License. See the file "COPYING" in the main directory of this archive |
| 4 | * for more details. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * PROM library initialisation code. |
Steven J. Hill | 49bffbd | 2013-03-25 15:05:40 -0500 | [diff] [blame] | 7 | * |
| 8 | * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc. |
| 9 | * All rights reserved. |
| 10 | * Authors: Carsten Langgaard <carstenl@mips.com> |
| 11 | * Maciej W. Rozycki <macro@mips.com> |
| 12 | * Steven J. Hill <sjhill@mips.com> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/string.h> |
| 16 | #include <linux/kernel.h> |
| 17 | |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 18 | #include <asm/cacheflush.h> |
Ralf Baechle | 852fe31 | 2011-05-28 15:27:59 +0100 | [diff] [blame] | 19 | #include <asm/smp-ops.h> |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 20 | #include <asm/traps.h> |
Steven J. Hill | b431f09 | 2013-03-25 14:47:05 -0500 | [diff] [blame] | 21 | #include <asm/fw/fw.h> |
Tim Anderson | 47b178b | 2009-06-17 16:25:18 -0700 | [diff] [blame] | 22 | #include <asm/gcmpregs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <asm/mips-boards/generic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <asm/mips-boards/malta.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | |
Dmitri Vorobiev | d0cdfe2 | 2009-03-23 00:12:27 +0200 | [diff] [blame] | 26 | static int mips_revision_corid; |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 27 | int mips_revision_sconid; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
| 29 | /* Bonito64 system controller register base. */ |
| 30 | unsigned long _pcictrl_bonito; |
| 31 | unsigned long _pcictrl_bonito_pcicfg; |
| 32 | |
| 33 | /* GT64120 system controller register base */ |
| 34 | unsigned long _pcictrl_gt64120; |
| 35 | |
| 36 | /* MIPS System controller register base */ |
| 37 | unsigned long _pcictrl_msc; |
| 38 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
| 40 | static void __init console_config(void) |
| 41 | { |
| 42 | char console_string[40]; |
| 43 | int baud = 0; |
| 44 | char parity = '\0', bits = '\0', flow = '\0'; |
| 45 | char *s; |
| 46 | |
Steven J. Hill | b431f09 | 2013-03-25 14:47:05 -0500 | [diff] [blame] | 47 | if ((strstr(fw_getcmdline(), "console=")) == NULL) { |
| 48 | s = fw_getenv("modetty0"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | if (s) { |
| 50 | while (*s >= '0' && *s <= '9') |
| 51 | baud = baud*10 + *s++ - '0'; |
Steven J. Hill | 49bffbd | 2013-03-25 15:05:40 -0500 | [diff] [blame] | 52 | if (*s == ',') |
| 53 | s++; |
| 54 | if (*s) |
| 55 | parity = *s++; |
| 56 | if (*s == ',') |
| 57 | s++; |
| 58 | if (*s) |
| 59 | bits = *s++; |
| 60 | if (*s == ',') |
| 61 | s++; |
| 62 | if (*s == 'h') |
| 63 | flow = 'r'; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | } |
| 65 | if (baud == 0) |
| 66 | baud = 38400; |
| 67 | if (parity != 'n' && parity != 'o' && parity != 'e') |
| 68 | parity = 'n'; |
| 69 | if (bits != '7' && bits != '8') |
| 70 | bits = '8'; |
| 71 | if (flow == '\0') |
| 72 | flow = 'r'; |
Steven J. Hill | 49bffbd | 2013-03-25 15:05:40 -0500 | [diff] [blame] | 73 | sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, |
| 74 | parity, bits, flow); |
Steven J. Hill | b431f09 | 2013-03-25 14:47:05 -0500 | [diff] [blame] | 75 | strcat(fw_getcmdline(), console_string); |
Ralf Baechle | 36a8853 | 2007-03-01 11:56:43 +0000 | [diff] [blame] | 76 | pr_info("Config serial console:%s\n", console_string); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 77 | } |
| 78 | } |
| 79 | #endif |
| 80 | |
Dmitri Vorobiev | cd2675f | 2008-04-01 02:03:20 +0400 | [diff] [blame] | 81 | static void __init mips_nmi_setup(void) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 82 | { |
| 83 | void *base; |
| 84 | extern char except_vec_nmi; |
| 85 | |
| 86 | base = cpu_has_veic ? |
| 87 | (void *)(CAC_BASE + 0xa80) : |
| 88 | (void *)(CAC_BASE + 0x380); |
| 89 | memcpy(base, &except_vec_nmi, 0x80); |
| 90 | flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); |
| 91 | } |
| 92 | |
Dmitri Vorobiev | 33d69d2 | 2008-04-01 02:03:21 +0400 | [diff] [blame] | 93 | static void __init mips_ejtag_setup(void) |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 94 | { |
| 95 | void *base; |
| 96 | extern char except_vec_ejtag_debug; |
| 97 | |
| 98 | base = cpu_has_veic ? |
| 99 | (void *)(CAC_BASE + 0xa00) : |
| 100 | (void *)(CAC_BASE + 0x300); |
| 101 | memcpy(base, &except_vec_ejtag_debug, 0x80); |
| 102 | flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); |
| 103 | } |
| 104 | |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 105 | extern struct plat_smp_ops msmtc_smp_ops; |
| 106 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | void __init prom_init(void) |
| 108 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | mips_display_message("LINUX"); |
| 110 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 111 | /* |
| 112 | * early setup of _pcictrl_bonito so that we can determine |
| 113 | * the system controller on a CORE_EMUL board |
| 114 | */ |
| 115 | _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); |
| 116 | |
| 117 | mips_revision_corid = MIPS_REVISION_CORID; |
| 118 | |
| 119 | if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 120 | if (BONITO_PCIDID == 0x0001df53 || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | BONITO_PCIDID == 0x0003df53) |
| 122 | mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; |
| 123 | else |
| 124 | mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; |
| 125 | } |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 126 | |
| 127 | mips_revision_sconid = MIPS_REVISION_SCONID; |
| 128 | if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { |
| 129 | switch (mips_revision_corid) { |
| 130 | case MIPS_REVISION_CORID_QED_RM5261: |
| 131 | case MIPS_REVISION_CORID_CORE_LV: |
| 132 | case MIPS_REVISION_CORID_CORE_FPGA: |
| 133 | case MIPS_REVISION_CORID_CORE_FPGAR2: |
| 134 | mips_revision_sconid = MIPS_REVISION_SCON_GT64120; |
| 135 | break; |
| 136 | case MIPS_REVISION_CORID_CORE_EMUL_BON: |
| 137 | case MIPS_REVISION_CORID_BONITO64: |
| 138 | case MIPS_REVISION_CORID_CORE_20K: |
| 139 | mips_revision_sconid = MIPS_REVISION_SCON_BONITO; |
| 140 | break; |
| 141 | case MIPS_REVISION_CORID_CORE_MSC: |
| 142 | case MIPS_REVISION_CORID_CORE_FPGA2: |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 143 | case MIPS_REVISION_CORID_CORE_24K: |
Chris Dearman | 3084024 | 2007-09-21 14:50:08 +0100 | [diff] [blame] | 144 | /* |
| 145 | * SOCit/ROCit support is essentially identical |
| 146 | * but make an attempt to distinguish them |
| 147 | */ |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 148 | mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; |
| 149 | break; |
Chris Dearman | 3084024 | 2007-09-21 14:50:08 +0100 | [diff] [blame] | 150 | case MIPS_REVISION_CORID_CORE_FPGA3: |
| 151 | case MIPS_REVISION_CORID_CORE_FPGA4: |
| 152 | case MIPS_REVISION_CORID_CORE_FPGA5: |
| 153 | case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 154 | default: |
Chris Dearman | 3084024 | 2007-09-21 14:50:08 +0100 | [diff] [blame] | 155 | /* See above */ |
| 156 | mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; |
| 157 | break; |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 158 | } |
| 159 | } |
| 160 | |
| 161 | switch (mips_revision_sconid) { |
Ralf Baechle | f76b7ea | 2007-03-04 17:26:56 +0000 | [diff] [blame] | 162 | u32 start, map, mask, data; |
| 163 | |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 164 | case MIPS_REVISION_SCON_GT64120: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 165 | /* |
| 166 | * Setup the North bridge to do Master byte-lane swapping |
| 167 | * when running in bigendian. |
| 168 | */ |
| 169 | _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); |
| 170 | |
| 171 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 172 | GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | |
| 173 | GT_PCI0_CMD_SBYTESWAP_BIT); |
| 174 | #else |
| 175 | GT_WRITE(GT_PCI0_CMD_OFS, 0); |
| 176 | #endif |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 177 | /* Fix up PCI I/O mapping if necessary (for Atlas). */ |
| 178 | start = GT_READ(GT_PCI0IOLD_OFS); |
| 179 | map = GT_READ(GT_PCI0IOREMAP_OFS); |
| 180 | if ((start & map) != 0) { |
| 181 | map &= ~start; |
| 182 | GT_WRITE(GT_PCI0IOREMAP_OFS, map); |
| 183 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | set_io_port_base(MALTA_GT_PORT_BASE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 186 | break; |
| 187 | |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 188 | case MIPS_REVISION_SCON_BONITO: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 189 | _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); |
| 190 | |
| 191 | /* |
| 192 | * Disable Bonito IOBC. |
| 193 | */ |
| 194 | BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & |
| 195 | ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | |
| 196 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); |
| 197 | |
| 198 | /* |
| 199 | * Setup the North bridge to do Master byte-lane swapping |
| 200 | * when running in bigendian. |
| 201 | */ |
| 202 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 203 | BONITO_BONGENCFG = BONITO_BONGENCFG & |
| 204 | ~(BONITO_BONGENCFG_MSTRBYTESWAP | |
| 205 | BONITO_BONGENCFG_BYTESWAP); |
| 206 | #else |
| 207 | BONITO_BONGENCFG = BONITO_BONGENCFG | |
| 208 | BONITO_BONGENCFG_MSTRBYTESWAP | |
| 209 | BONITO_BONGENCFG_BYTESWAP; |
| 210 | #endif |
| 211 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | set_io_port_base(MALTA_BONITO_PORT_BASE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | break; |
| 214 | |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 215 | case MIPS_REVISION_SCON_SOCIT: |
| 216 | case MIPS_REVISION_SCON_ROCIT: |
Ralf Baechle | 42a3b4f | 2005-09-03 15:56:17 -0700 | [diff] [blame] | 217 | _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); |
Steven J. Hill | 49bffbd | 2013-03-25 15:05:40 -0500 | [diff] [blame] | 218 | mips_pci_controller: |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 219 | mb(); |
| 220 | MSC_READ(MSC01_PCI_CFG, data); |
| 221 | MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); |
| 222 | wmb(); |
| 223 | |
| 224 | /* Fix up lane swapping. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 225 | #ifdef CONFIG_CPU_LITTLE_ENDIAN |
| 226 | MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); |
| 227 | #else |
| 228 | MSC_WRITE(MSC01_PCI_SWAP, |
| 229 | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | |
| 230 | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | |
| 231 | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); |
| 232 | #endif |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 233 | /* Fix up target memory mapping. */ |
| 234 | MSC_READ(MSC01_PCI_BAR0, mask); |
| 235 | MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | |
Maciej W. Rozycki | aa0980b8 | 2005-02-01 20:18:59 +0000 | [diff] [blame] | 237 | /* Don't handle target retries indefinitely. */ |
| 238 | if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == |
| 239 | MSC01_PCI_CFG_MAXRTRY_MSK) |
| 240 | data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << |
| 241 | MSC01_PCI_CFG_MAXRTRY_SHF)) | |
| 242 | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << |
| 243 | MSC01_PCI_CFG_MAXRTRY_SHF); |
| 244 | |
| 245 | wmb(); |
| 246 | MSC_WRITE(MSC01_PCI_CFG, data); |
| 247 | mb(); |
| 248 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 249 | set_io_port_base(MALTA_MSC_PORT_BASE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | break; |
| 251 | |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 252 | case MIPS_REVISION_SCON_SOCITSC: |
| 253 | case MIPS_REVISION_SCON_SOCITSCP: |
| 254 | _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); |
| 255 | goto mips_pci_controller; |
| 256 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 257 | default: |
Chris Dearman | b72c052 | 2007-04-27 15:58:41 +0100 | [diff] [blame] | 258 | /* Unknown system controller */ |
| 259 | mips_display_message("SC Error"); |
Steven J. Hill | 49bffbd | 2013-03-25 15:05:40 -0500 | [diff] [blame] | 260 | while (1); /* We die here... */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | } |
Ralf Baechle | e01402b | 2005-07-14 15:57:16 +0000 | [diff] [blame] | 262 | board_nmi_handler_setup = mips_nmi_setup; |
| 263 | board_ejtag_handler_setup = mips_ejtag_setup; |
| 264 | |
Steven J. Hill | b431f09 | 2013-03-25 14:47:05 -0500 | [diff] [blame] | 265 | fw_init_cmdline(); |
| 266 | fw_meminit(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 267 | #ifdef CONFIG_SERIAL_8250_CONSOLE |
| 268 | console_config(); |
| 269 | #endif |
Ralf Baechle | af3a1f6 | 2011-03-29 11:43:19 +0200 | [diff] [blame] | 270 | /* Early detection of CMP support */ |
| 271 | if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) |
Ralf Baechle | 852fe31 | 2011-05-28 15:27:59 +0100 | [diff] [blame] | 272 | if (!register_cmp_smp_ops()) |
| 273 | return; |
| 274 | |
| 275 | if (!register_vsmp_smp_ops()) |
| 276 | return; |
| 277 | |
Ralf Baechle | 87353d8 | 2007-11-19 12:23:51 +0000 | [diff] [blame] | 278 | #ifdef CONFIG_MIPS_MT_SMTC |
| 279 | register_smp_ops(&msmtc_smp_ops); |
| 280 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | } |