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gerrit-public.fairphone.software / kernel / msm-4.9 / ed6c1476bf7f16d5f203ce2893ed04284c3aebd3 / . / arch / arm / mach-omap2 / cm2_44xx.h
blob: 7521abf3d8305dfc99b4e02e62bf8f319c8fa323 [file] [log] [blame]
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]1/*
2 * OMAP44xx CM2 instance offset macros
3 *
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22 * or "OMAP4430".
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
26#define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
27
28/* CM2 base address */
29#define OMAP4430_CM2_BASE 0x4a008000
30
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]31#define OMAP44XX_CM2_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]33
34/* CM2 instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]35#define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
36#define OMAP4430_CM2_CKGEN_INST 0x0100
37#define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
38#define OMAP4430_CM2_CORE_INST 0x0700
39#define OMAP4430_CM2_IVAHD_INST 0x0f00
40#define OMAP4430_CM2_CAM_INST 0x1000
41#define OMAP4430_CM2_DSS_INST 0x1100
42#define OMAP4430_CM2_GFX_INST 0x1200
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]43#define OMAP4430_CM2_L3INIT_INST 0x1300
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]44#define OMAP4430_CM2_L4PER_INST 0x1400
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]45#define OMAP4430_CM2_CEFUSE_INST 0x1600
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]46#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_INST 0x1f00
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]48
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]49/* CM2 clockdomain register offsets (from instance start) */
50#define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000
51#define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000
52#define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100
53#define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200
54#define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300
55#define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400
56#define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500
57#define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600
58#define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700
59#define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000
60#define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000
61#define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000
62#define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000
63#define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000
64#define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000
65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
67
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]68/* CM2 */
69
70/* CM2.OCP_SOCKET_CM2 register offsets */
71#define OMAP4_REVISION_CM2_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]72#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]73#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]74#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]75
76/* CM2.CKGEN_CM2 register offsets */
77#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]78#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]79#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]80#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]81#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]82#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]83#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]84#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]85#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]86#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]87#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]88#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]89#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]90#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]91#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]92#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]93#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]94#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]95#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]96#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]97#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]98#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]99#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]100#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]101#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]102#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]103#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]104#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]105#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]106#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]107#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]108#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]109#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]110#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]111#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]112#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]113#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]114#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]115#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]116#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]117#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]118#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]119#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]120#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]121#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]122#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]123#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
124#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]125#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]126#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]127#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]128#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]129#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]130#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]131#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]132#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]133#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]134#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]139#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]140#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]141#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]142#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]143#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]144#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]145#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]146#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]147#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]148#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]149#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]150#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]151#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]152#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]153#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
154#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]155
156/* CM2.ALWAYS_ON_CM2 register offsets */
157#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]158#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]159#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]160#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]161#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]162#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]163#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]164#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]165#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]166#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]167#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]168#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]169
170/* CM2.CORE_CM2 register offsets */
171#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]172#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]173#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]174#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]175#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]176#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]177#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]178#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]179#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]180#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]181#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]182#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]183#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]184#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]185#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]186#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]187#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]188#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]189#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]190#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]191#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]192#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]193#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]194#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]195#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]196#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]197#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]198#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]199#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]200#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]201#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]202#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]203#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]204#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]205#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]206#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]207#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]208#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]209#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]210#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]211#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]212#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]213#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]214#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]215#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]216#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]217#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]218#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]219#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]220#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]221#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]222#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]223#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]224#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]225#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]226#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]227#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]228#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]229#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
230#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]231#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]232#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]233#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]234#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]235#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]236#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]237#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]238#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]239#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]240#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]241#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]242#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]243#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]244#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]245#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]246#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]247#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]248#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]249#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]250#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]251#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]252#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]253
254/* CM2.IVAHD_CM2 register offsets */
255#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]256#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]257#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]258#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]259#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]260#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]261#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]262#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]263#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]264#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]265
266/* CM2.CAM_CM2 register offsets */
267#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]268#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]269#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]270#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]271#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]272#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]273#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]274#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]275#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]276#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]277
278/* CM2.DSS_CM2 register offsets */
279#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]280#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]281#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]282#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]283#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]284#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]285#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]286#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]287#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]288#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]289
290/* CM2.GFX_CM2 register offsets */
291#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]292#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]293#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]294#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]295#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]296#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]297#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]298#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]299
300/* CM2.L3INIT_CM2 register offsets */
301#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]302#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]303#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]304#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]305#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]306#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]307#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]308#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]309#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]310#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]311#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]312#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]313#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]314#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]315#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]316#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]317#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]318#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]319#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]320#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]321#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]322#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]323#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]324#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]325#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]326#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]327#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]328#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]329#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]330#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]331#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]332#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]333#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]334#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]335#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]336#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]337#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]338#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]339#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]340#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]341
342/* CM2.L4PER_CM2 register offsets */
343#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]344#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]345#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]346#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]347#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]348#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]349#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]350#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]351#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]352#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]353#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]354#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]355#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]356#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]357#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]358#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]359#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]360#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]361#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]362#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]363#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]364#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]365#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]366#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]367#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]368#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]369#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]370#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]371#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]372#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]373#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]374#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]375#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]376#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]377#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]378#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]379#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]380#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]381#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]382#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]383#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]384#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]385#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]386#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]387#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]388#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]389#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]390#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]391#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]392#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]393#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]394#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]395#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]396#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]397#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]398#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]399#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]400#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]401#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]402#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]403#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]404#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]405#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]406#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]407#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]408#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]409#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]410#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]411#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]412#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]413#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]414#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]415#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]416#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]417#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]418#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]419#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]420#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]421#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]422#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]423#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]424#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]425#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]426#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]427#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]428#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]429#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]430#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]431#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]432#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]433#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]434#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]435#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]436#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]437#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]438#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]439#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]440#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]441#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]442#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]443#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]444#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]445
446/* CM2.CEFUSE_CM2 register offsets */
447#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]448#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]451
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]452#endif