Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 2 | |MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP |
| 3 | |M68000 Hi-Performance Microprocessor Division |
| 4 | |M68060 Software Package |
| 5 | |Production Release P1.00 -- October 10, 1994 |
| 6 | | |
Jan Engelhardt | 96de0e2 | 2007-10-19 23:21:04 +0200 | [diff] [blame] | 7 | |M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | | |
| 9 | |THE SOFTWARE is provided on an "AS IS" basis and without warranty. |
| 10 | |To the maximum extent permitted by applicable law, |
| 11 | |MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, |
| 12 | |INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE |
| 13 | |and any warranty against infringement with regard to the SOFTWARE |
| 14 | |(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. |
| 15 | | |
| 16 | |To the maximum extent permitted by applicable law, |
| 17 | |IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER |
| 18 | |(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, |
| 19 | |BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) |
| 20 | |ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. |
| 21 | |Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. |
| 22 | | |
| 23 | |You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE |
| 24 | |so long as this entire notice is retained without alteration in any modified and/or |
| 25 | |redistributed versions, and that such modified versions are clearly identified as such. |
| 26 | |No licenses are granted by implication, estoppel or otherwise under any patents |
| 27 | |or trademarks of Motorola, Inc. |
| 28 | |~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 29 | | fskeleton.s |
| 30 | | |
| 31 | | This file contains: |
| 32 | | (1) example "Call-out"s |
| 33 | | (2) example package entry code |
| 34 | | (3) example "Call-out" table |
| 35 | | |
| 36 | |
| 37 | #include <linux/linkage.h> |
| 38 | |
| 39 | |################################ |
| 40 | | (1) EXAMPLE CALL-OUTS # |
| 41 | | # |
| 42 | | _060_fpsp_done() # |
| 43 | | _060_real_ovfl() # |
| 44 | | _060_real_unfl() # |
| 45 | | _060_real_operr() # |
| 46 | | _060_real_snan() # |
| 47 | | _060_real_dz() # |
| 48 | | _060_real_inex() # |
| 49 | | _060_real_bsun() # |
| 50 | | _060_real_fline() # |
| 51 | | _060_real_fpu_disabled() # |
| 52 | | _060_real_trap() # |
| 53 | |################################ |
| 54 | |
| 55 | | |
| 56 | | _060_fpsp_done(): |
| 57 | | |
| 58 | | This is the main exit point for the 68060 Floating-Point |
| 59 | | Software Package. For a normal exit, all 060FPSP routines call this |
| 60 | | routine. The operating system can do system dependent clean-up or |
| 61 | | simply execute an "rte" as with the sample code below. |
| 62 | | |
| 63 | .global _060_fpsp_done |
| 64 | _060_fpsp_done: |
| 65 | bral _060_isp_done | do the same as isp_done |
| 66 | |
| 67 | | |
| 68 | | _060_real_ovfl(): |
| 69 | | |
| 70 | | This is the exit point for the 060FPSP when an enabled overflow exception |
| 71 | | is present. The routine below should point to the operating system handler |
| 72 | | for enabled overflow conditions. The exception stack frame is an overflow |
| 73 | | stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. |
| 74 | | |
| 75 | | The sample routine below simply clears the exception status bit and |
| 76 | | does an "rte". |
| 77 | | |
| 78 | .global _060_real_ovfl |
| 79 | _060_real_ovfl: |
| 80 | fsave -(%sp) |
| 81 | move.w #0x6000,0x2(%sp) |
| 82 | frestore (%sp)+ |
| 83 | bral trap | jump to trap handler |
| 84 | |
| 85 | |
| 86 | | |
| 87 | | _060_real_unfl(): |
| 88 | | |
| 89 | | This is the exit point for the 060FPSP when an enabled underflow exception |
| 90 | | is present. The routine below should point to the operating system handler |
| 91 | | for enabled underflow conditions. The exception stack frame is an underflow |
| 92 | | stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. |
| 93 | | |
| 94 | | The sample routine below simply clears the exception status bit and |
| 95 | | does an "rte". |
| 96 | | |
| 97 | .global _060_real_unfl |
| 98 | _060_real_unfl: |
| 99 | fsave -(%sp) |
| 100 | move.w #0x6000,0x2(%sp) |
| 101 | frestore (%sp)+ |
| 102 | bral trap | jump to trap handler |
| 103 | |
| 104 | | |
| 105 | | _060_real_operr(): |
| 106 | | |
| 107 | | This is the exit point for the 060FPSP when an enabled operand error exception |
| 108 | | is present. The routine below should point to the operating system handler |
| 109 | | for enabled operand error exceptions. The exception stack frame is an operand error |
| 110 | | stack frame. The FP state frame holds the source operand of the faulting |
| 111 | | instruction. |
| 112 | | |
| 113 | | The sample routine below simply clears the exception status bit and |
| 114 | | does an "rte". |
| 115 | | |
| 116 | .global _060_real_operr |
| 117 | _060_real_operr: |
| 118 | fsave -(%sp) |
| 119 | move.w #0x6000,0x2(%sp) |
| 120 | frestore (%sp)+ |
| 121 | bral trap | jump to trap handler |
| 122 | |
| 123 | | |
| 124 | | _060_real_snan(): |
| 125 | | |
| 126 | | This is the exit point for the 060FPSP when an enabled signalling NaN exception |
| 127 | | is present. The routine below should point to the operating system handler |
| 128 | | for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN |
| 129 | | stack frame. The FP state frame holds the source operand of the faulting |
| 130 | | instruction. |
| 131 | | |
| 132 | | The sample routine below simply clears the exception status bit and |
| 133 | | does an "rte". |
| 134 | | |
| 135 | .global _060_real_snan |
| 136 | _060_real_snan: |
| 137 | fsave -(%sp) |
| 138 | move.w #0x6000,0x2(%sp) |
| 139 | frestore (%sp)+ |
| 140 | bral trap | jump to trap handler |
| 141 | |
| 142 | | |
| 143 | | _060_real_dz(): |
| 144 | | |
| 145 | | This is the exit point for the 060FPSP when an enabled divide-by-zero exception |
| 146 | | is present. The routine below should point to the operating system handler |
| 147 | | for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero |
| 148 | | stack frame. The FP state frame holds the source operand of the faulting |
| 149 | | instruction. |
| 150 | | |
| 151 | | The sample routine below simply clears the exception status bit and |
| 152 | | does an "rte". |
| 153 | | |
| 154 | .global _060_real_dz |
| 155 | _060_real_dz: |
| 156 | fsave -(%sp) |
| 157 | move.w #0x6000,0x2(%sp) |
| 158 | frestore (%sp)+ |
| 159 | bral trap | jump to trap handler |
| 160 | |
| 161 | | |
| 162 | | _060_real_inex(): |
| 163 | | |
| 164 | | This is the exit point for the 060FPSP when an enabled inexact exception |
| 165 | | is present. The routine below should point to the operating system handler |
| 166 | | for enabled inexact exceptions. The exception stack frame is an inexact |
| 167 | | stack frame. The FP state frame holds the source operand of the faulting |
| 168 | | instruction. |
| 169 | | |
| 170 | | The sample routine below simply clears the exception status bit and |
| 171 | | does an "rte". |
| 172 | | |
| 173 | .global _060_real_inex |
| 174 | _060_real_inex: |
| 175 | fsave -(%sp) |
| 176 | move.w #0x6000,0x2(%sp) |
| 177 | frestore (%sp)+ |
| 178 | bral trap | jump to trap handler |
| 179 | |
| 180 | | |
| 181 | | _060_real_bsun(): |
| 182 | | |
| 183 | | This is the exit point for the 060FPSP when an enabled bsun exception |
| 184 | | is present. The routine below should point to the operating system handler |
| 185 | | for enabled bsun exceptions. The exception stack frame is a bsun |
| 186 | | stack frame. |
| 187 | | |
| 188 | | The sample routine below clears the exception status bit, clears the NaN |
| 189 | | bit in the FPSR, and does an "rte". The instruction that caused the |
| 190 | | bsun will now be re-executed but with the NaN FPSR bit cleared. |
| 191 | | |
| 192 | .global _060_real_bsun |
| 193 | _060_real_bsun: |
| 194 | | fsave -(%sp) |
| 195 | |
| 196 | fmove.l %fpsr,-(%sp) |
| 197 | andi.b #0xfe,(%sp) |
| 198 | fmove.l (%sp)+,%fpsr |
| 199 | |
| 200 | bral trap | jump to trap handler |
| 201 | |
| 202 | | |
| 203 | | _060_real_fline(): |
| 204 | | |
| 205 | | This is the exit point for the 060FPSP when an F-Line Illegal exception is |
| 206 | | encountered. Three different types of exceptions can enter the F-Line exception |
| 207 | | vector number 11: FP Unimplemented Instructions, FP implemented instructions when |
| 208 | | the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module |
| 209 | | _fpsp_fline() distinguishes between the three and acts appropriately. F-Line |
| 210 | | Illegals branch here. |
| 211 | | |
| 212 | .global _060_real_fline |
| 213 | _060_real_fline: |
| 214 | bral trap | jump to trap handler |
| 215 | |
| 216 | | |
| 217 | | _060_real_fpu_disabled(): |
| 218 | | |
| 219 | | This is the exit point for the 060FPSP when an FPU disabled exception is |
| 220 | | encountered. Three different types of exceptions can enter the F-Line exception |
| 221 | | vector number 11: FP Unimplemented Instructions, FP implemented instructions when |
| 222 | | the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module |
| 223 | | _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled |
| 224 | | exceptions branch here. |
| 225 | | |
| 226 | | The sample code below enables the FPU, sets the PC field in the exception stack |
| 227 | | frame to the PC of the instruction causing the exception, and does an "rte". |
| 228 | | The execution of the instruction then proceeds with an enabled floating-point |
| 229 | | unit. |
| 230 | | |
| 231 | .global _060_real_fpu_disabled |
| 232 | _060_real_fpu_disabled: |
| 233 | move.l %d0,-(%sp) | enabled the fpu |
| 234 | .long 0x4E7A0808 |movec pcr,%d0 |
| 235 | bclr #0x1,%d0 |
| 236 | .long 0x4E7B0808 |movec %d0,pcr |
| 237 | move.l (%sp)+,%d0 |
| 238 | |
| 239 | move.l 0xc(%sp),0x2(%sp) | set "Current PC" |
| 240 | rte |
| 241 | |
| 242 | | |
| 243 | | _060_real_trap(): |
| 244 | | |
| 245 | | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction |
| 246 | | discovers that the trap condition is true and it should branch to the operating |
| 247 | | system handler for the trap exception vector number 7. |
| 248 | | |
| 249 | | The sample code below simply executes an "rte". |
| 250 | | |
| 251 | .global _060_real_trap |
| 252 | _060_real_trap: |
| 253 | bral trap | jump to trap handler |
| 254 | |
| 255 | |############################################################################ |
| 256 | |
| 257 | |################################# |
| 258 | | (2) EXAMPLE PACKAGE ENTRY CODE # |
| 259 | |################################# |
| 260 | |
| 261 | .global _060_fpsp_snan |
| 262 | _060_fpsp_snan: |
| 263 | bra.l _FP_CALL_TOP+0x80+0x00 |
| 264 | |
| 265 | .global _060_fpsp_operr |
| 266 | _060_fpsp_operr: |
| 267 | bra.l _FP_CALL_TOP+0x80+0x08 |
| 268 | |
| 269 | .global _060_fpsp_ovfl |
| 270 | _060_fpsp_ovfl: |
| 271 | bra.l _FP_CALL_TOP+0x80+0x10 |
| 272 | |
| 273 | .global _060_fpsp_unfl |
| 274 | _060_fpsp_unfl: |
| 275 | bra.l _FP_CALL_TOP+0x80+0x18 |
| 276 | |
| 277 | .global _060_fpsp_dz |
| 278 | _060_fpsp_dz: |
| 279 | bra.l _FP_CALL_TOP+0x80+0x20 |
| 280 | |
| 281 | .global _060_fpsp_inex |
| 282 | _060_fpsp_inex: |
| 283 | bra.l _FP_CALL_TOP+0x80+0x28 |
| 284 | |
| 285 | .global _060_fpsp_fline |
| 286 | _060_fpsp_fline: |
| 287 | bra.l _FP_CALL_TOP+0x80+0x30 |
| 288 | |
| 289 | .global _060_fpsp_unsupp |
| 290 | _060_fpsp_unsupp: |
| 291 | bra.l _FP_CALL_TOP+0x80+0x38 |
| 292 | |
| 293 | .global _060_fpsp_effadd |
| 294 | _060_fpsp_effadd: |
| 295 | bra.l _FP_CALL_TOP+0x80+0x40 |
| 296 | |
| 297 | |############################################################################ |
| 298 | |
| 299 | |############################### |
| 300 | | (3) EXAMPLE CALL-OUT SECTION # |
| 301 | |############################### |
| 302 | |
| 303 | | The size of this section MUST be 128 bytes!!! |
| 304 | |
| 305 | _FP_CALL_TOP: |
| 306 | .long _060_real_bsun - _FP_CALL_TOP |
| 307 | .long _060_real_snan - _FP_CALL_TOP |
| 308 | .long _060_real_operr - _FP_CALL_TOP |
| 309 | .long _060_real_ovfl - _FP_CALL_TOP |
| 310 | .long _060_real_unfl - _FP_CALL_TOP |
| 311 | .long _060_real_dz - _FP_CALL_TOP |
| 312 | .long _060_real_inex - _FP_CALL_TOP |
| 313 | .long _060_real_fline - _FP_CALL_TOP |
| 314 | .long _060_real_fpu_disabled - _FP_CALL_TOP |
| 315 | .long _060_real_trap - _FP_CALL_TOP |
| 316 | .long _060_real_trace - _FP_CALL_TOP |
| 317 | .long _060_real_access - _FP_CALL_TOP |
| 318 | .long _060_fpsp_done - _FP_CALL_TOP |
| 319 | |
| 320 | .long 0x00000000, 0x00000000, 0x00000000 |
| 321 | |
| 322 | .long _060_imem_read - _FP_CALL_TOP |
| 323 | .long _060_dmem_read - _FP_CALL_TOP |
| 324 | .long _060_dmem_write - _FP_CALL_TOP |
| 325 | .long _060_imem_read_word - _FP_CALL_TOP |
| 326 | .long _060_imem_read_long - _FP_CALL_TOP |
| 327 | .long _060_dmem_read_byte - _FP_CALL_TOP |
| 328 | .long _060_dmem_read_word - _FP_CALL_TOP |
| 329 | .long _060_dmem_read_long - _FP_CALL_TOP |
| 330 | .long _060_dmem_write_byte - _FP_CALL_TOP |
| 331 | .long _060_dmem_write_word - _FP_CALL_TOP |
| 332 | .long _060_dmem_write_long - _FP_CALL_TOP |
| 333 | |
| 334 | .long 0x00000000 |
| 335 | |
| 336 | .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 |
| 337 | |
| 338 | |############################################################################ |
| 339 | |
| 340 | | 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!! |
| 341 | |
| 342 | #include "fpsp.sa" |