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Choi, Davida55c0a0e2009-09-25 14:42:12 +00001/**
2 * drivers/net/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19/**
20 * Supports:
21 * KS8851 16bit MLL chip from Micrel Inc.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/netdevice.h>
27#include <linux/etherdevice.h>
28#include <linux/ethtool.h>
29#include <linux/cache.h>
30#include <linux/crc32.h>
31#include <linux/mii.h>
32#include <linux/platform_device.h>
33#include <linux/delay.h>
34
35#define DRV_NAME "ks8851_mll"
36
37static u8 KS_DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
38#define MAX_RECV_FRAMES 32
39#define MAX_BUF_SIZE 2048
40#define TX_BUF_SIZE 2000
41#define RX_BUF_SIZE 2000
42
43#define KS_CCR 0x08
44#define CCR_EEPROM (1 << 9)
45#define CCR_SPI (1 << 8)
46#define CCR_8BIT (1 << 7)
47#define CCR_16BIT (1 << 6)
48#define CCR_32BIT (1 << 5)
49#define CCR_SHARED (1 << 4)
50#define CCR_32PIN (1 << 0)
51
52/* MAC address registers */
53#define KS_MARL 0x10
54#define KS_MARM 0x12
55#define KS_MARH 0x14
56
57#define KS_OBCR 0x20
58#define OBCR_ODS_16MA (1 << 6)
59
60#define KS_EEPCR 0x22
61#define EEPCR_EESA (1 << 4)
62#define EEPCR_EESB (1 << 3)
63#define EEPCR_EEDO (1 << 2)
64#define EEPCR_EESCK (1 << 1)
65#define EEPCR_EECS (1 << 0)
66
67#define KS_MBIR 0x24
68#define MBIR_TXMBF (1 << 12)
69#define MBIR_TXMBFA (1 << 11)
70#define MBIR_RXMBF (1 << 4)
71#define MBIR_RXMBFA (1 << 3)
72
73#define KS_GRR 0x26
74#define GRR_QMU (1 << 1)
75#define GRR_GSR (1 << 0)
76
77#define KS_WFCR 0x2A
78#define WFCR_MPRXE (1 << 7)
79#define WFCR_WF3E (1 << 3)
80#define WFCR_WF2E (1 << 2)
81#define WFCR_WF1E (1 << 1)
82#define WFCR_WF0E (1 << 0)
83
84#define KS_WF0CRC0 0x30
85#define KS_WF0CRC1 0x32
86#define KS_WF0BM0 0x34
87#define KS_WF0BM1 0x36
88#define KS_WF0BM2 0x38
89#define KS_WF0BM3 0x3A
90
91#define KS_WF1CRC0 0x40
92#define KS_WF1CRC1 0x42
93#define KS_WF1BM0 0x44
94#define KS_WF1BM1 0x46
95#define KS_WF1BM2 0x48
96#define KS_WF1BM3 0x4A
97
98#define KS_WF2CRC0 0x50
99#define KS_WF2CRC1 0x52
100#define KS_WF2BM0 0x54
101#define KS_WF2BM1 0x56
102#define KS_WF2BM2 0x58
103#define KS_WF2BM3 0x5A
104
105#define KS_WF3CRC0 0x60
106#define KS_WF3CRC1 0x62
107#define KS_WF3BM0 0x64
108#define KS_WF3BM1 0x66
109#define KS_WF3BM2 0x68
110#define KS_WF3BM3 0x6A
111
112#define KS_TXCR 0x70
113#define TXCR_TCGICMP (1 << 8)
114#define TXCR_TCGUDP (1 << 7)
115#define TXCR_TCGTCP (1 << 6)
116#define TXCR_TCGIP (1 << 5)
117#define TXCR_FTXQ (1 << 4)
118#define TXCR_TXFCE (1 << 3)
119#define TXCR_TXPE (1 << 2)
120#define TXCR_TXCRC (1 << 1)
121#define TXCR_TXE (1 << 0)
122
123#define KS_TXSR 0x72
124#define TXSR_TXLC (1 << 13)
125#define TXSR_TXMC (1 << 12)
126#define TXSR_TXFID_MASK (0x3f << 0)
127#define TXSR_TXFID_SHIFT (0)
128#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
129
130
131#define KS_RXCR1 0x74
132#define RXCR1_FRXQ (1 << 15)
133#define RXCR1_RXUDPFCC (1 << 14)
134#define RXCR1_RXTCPFCC (1 << 13)
135#define RXCR1_RXIPFCC (1 << 12)
136#define RXCR1_RXPAFMA (1 << 11)
137#define RXCR1_RXFCE (1 << 10)
138#define RXCR1_RXEFE (1 << 9)
139#define RXCR1_RXMAFMA (1 << 8)
140#define RXCR1_RXBE (1 << 7)
141#define RXCR1_RXME (1 << 6)
142#define RXCR1_RXUE (1 << 5)
143#define RXCR1_RXAE (1 << 4)
144#define RXCR1_RXINVF (1 << 1)
145#define RXCR1_RXE (1 << 0)
146#define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
147 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
148
149#define KS_RXCR2 0x76
150#define RXCR2_SRDBL_MASK (0x7 << 5)
151#define RXCR2_SRDBL_SHIFT (5)
152#define RXCR2_SRDBL_4B (0x0 << 5)
153#define RXCR2_SRDBL_8B (0x1 << 5)
154#define RXCR2_SRDBL_16B (0x2 << 5)
155#define RXCR2_SRDBL_32B (0x3 << 5)
156/* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
157#define RXCR2_IUFFP (1 << 4)
158#define RXCR2_RXIUFCEZ (1 << 3)
159#define RXCR2_UDPLFE (1 << 2)
160#define RXCR2_RXICMPFCC (1 << 1)
161#define RXCR2_RXSAF (1 << 0)
162
163#define KS_TXMIR 0x78
164
165#define KS_RXFHSR 0x7C
166#define RXFSHR_RXFV (1 << 15)
167#define RXFSHR_RXICMPFCS (1 << 13)
168#define RXFSHR_RXIPFCS (1 << 12)
169#define RXFSHR_RXTCPFCS (1 << 11)
170#define RXFSHR_RXUDPFCS (1 << 10)
171#define RXFSHR_RXBF (1 << 7)
172#define RXFSHR_RXMF (1 << 6)
173#define RXFSHR_RXUF (1 << 5)
174#define RXFSHR_RXMR (1 << 4)
175#define RXFSHR_RXFT (1 << 3)
176#define RXFSHR_RXFTL (1 << 2)
177#define RXFSHR_RXRF (1 << 1)
178#define RXFSHR_RXCE (1 << 0)
179#define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
180 RXFSHR_RXFTL | RXFSHR_RXMR |\
181 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
182 RXFSHR_RXTCPFCS)
183#define KS_RXFHBCR 0x7E
184#define RXFHBCR_CNT_MASK 0x0FFF
185
186#define KS_TXQCR 0x80
187#define TXQCR_AETFE (1 << 2)
188#define TXQCR_TXQMAM (1 << 1)
189#define TXQCR_METFE (1 << 0)
190
191#define KS_RXQCR 0x82
192#define RXQCR_RXDTTS (1 << 12)
193#define RXQCR_RXDBCTS (1 << 11)
194#define RXQCR_RXFCTS (1 << 10)
195#define RXQCR_RXIPHTOE (1 << 9)
196#define RXQCR_RXDTTE (1 << 7)
197#define RXQCR_RXDBCTE (1 << 6)
198#define RXQCR_RXFCTE (1 << 5)
199#define RXQCR_ADRFE (1 << 4)
200#define RXQCR_SDA (1 << 3)
201#define RXQCR_RRXEF (1 << 0)
202#define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
203
204#define KS_TXFDPR 0x84
205#define TXFDPR_TXFPAI (1 << 14)
206#define TXFDPR_TXFP_MASK (0x7ff << 0)
207#define TXFDPR_TXFP_SHIFT (0)
208
209#define KS_RXFDPR 0x86
210#define RXFDPR_RXFPAI (1 << 14)
211
212#define KS_RXDTTR 0x8C
213#define KS_RXDBCTR 0x8E
214
215#define KS_IER 0x90
216#define KS_ISR 0x92
217#define IRQ_LCI (1 << 15)
218#define IRQ_TXI (1 << 14)
219#define IRQ_RXI (1 << 13)
220#define IRQ_RXOI (1 << 11)
221#define IRQ_TXPSI (1 << 9)
222#define IRQ_RXPSI (1 << 8)
223#define IRQ_TXSAI (1 << 6)
224#define IRQ_RXWFDI (1 << 5)
225#define IRQ_RXMPDI (1 << 4)
226#define IRQ_LDI (1 << 3)
227#define IRQ_EDI (1 << 2)
228#define IRQ_SPIBEI (1 << 1)
229#define IRQ_DEDI (1 << 0)
230
231#define KS_RXFCTR 0x9C
232#define RXFCTR_THRESHOLD_MASK 0x00FF
233
234#define KS_RXFC 0x9D
235#define RXFCTR_RXFC_MASK (0xff << 8)
236#define RXFCTR_RXFC_SHIFT (8)
237#define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
238#define RXFCTR_RXFCT_MASK (0xff << 0)
239#define RXFCTR_RXFCT_SHIFT (0)
240
241#define KS_TXNTFSR 0x9E
242
243#define KS_MAHTR0 0xA0
244#define KS_MAHTR1 0xA2
245#define KS_MAHTR2 0xA4
246#define KS_MAHTR3 0xA6
247
248#define KS_FCLWR 0xB0
249#define KS_FCHWR 0xB2
250#define KS_FCOWR 0xB4
251
252#define KS_CIDER 0xC0
253#define CIDER_ID 0x8870
254#define CIDER_REV_MASK (0x7 << 1)
255#define CIDER_REV_SHIFT (1)
256#define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
257
258#define KS_CGCR 0xC6
259#define KS_IACR 0xC8
260#define IACR_RDEN (1 << 12)
261#define IACR_TSEL_MASK (0x3 << 10)
262#define IACR_TSEL_SHIFT (10)
263#define IACR_TSEL_MIB (0x3 << 10)
264#define IACR_ADDR_MASK (0x1f << 0)
265#define IACR_ADDR_SHIFT (0)
266
267#define KS_IADLR 0xD0
268#define KS_IAHDR 0xD2
269
270#define KS_PMECR 0xD4
271#define PMECR_PME_DELAY (1 << 14)
272#define PMECR_PME_POL (1 << 12)
273#define PMECR_WOL_WAKEUP (1 << 11)
274#define PMECR_WOL_MAGICPKT (1 << 10)
275#define PMECR_WOL_LINKUP (1 << 9)
276#define PMECR_WOL_ENERGY (1 << 8)
277#define PMECR_AUTO_WAKE_EN (1 << 7)
278#define PMECR_WAKEUP_NORMAL (1 << 6)
279#define PMECR_WKEVT_MASK (0xf << 2)
280#define PMECR_WKEVT_SHIFT (2)
281#define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
282#define PMECR_WKEVT_ENERGY (0x1 << 2)
283#define PMECR_WKEVT_LINK (0x2 << 2)
284#define PMECR_WKEVT_MAGICPKT (0x4 << 2)
285#define PMECR_WKEVT_FRAME (0x8 << 2)
286#define PMECR_PM_MASK (0x3 << 0)
287#define PMECR_PM_SHIFT (0)
288#define PMECR_PM_NORMAL (0x0 << 0)
289#define PMECR_PM_ENERGY (0x1 << 0)
290#define PMECR_PM_SOFTDOWN (0x2 << 0)
291#define PMECR_PM_POWERSAVE (0x3 << 0)
292
293/* Standard MII PHY data */
294#define KS_P1MBCR 0xE4
295#define P1MBCR_FORCE_FDX (1 << 8)
296
297#define KS_P1MBSR 0xE6
298#define P1MBSR_AN_COMPLETE (1 << 5)
299#define P1MBSR_AN_CAPABLE (1 << 3)
300#define P1MBSR_LINK_UP (1 << 2)
301
302#define KS_PHY1ILR 0xE8
303#define KS_PHY1IHR 0xEA
304#define KS_P1ANAR 0xEC
305#define KS_P1ANLPR 0xEE
306
307#define KS_P1SCLMD 0xF4
308#define P1SCLMD_LEDOFF (1 << 15)
309#define P1SCLMD_TXIDS (1 << 14)
310#define P1SCLMD_RESTARTAN (1 << 13)
311#define P1SCLMD_DISAUTOMDIX (1 << 10)
312#define P1SCLMD_FORCEMDIX (1 << 9)
313#define P1SCLMD_AUTONEGEN (1 << 7)
314#define P1SCLMD_FORCE100 (1 << 6)
315#define P1SCLMD_FORCEFDX (1 << 5)
316#define P1SCLMD_ADV_FLOW (1 << 4)
317#define P1SCLMD_ADV_100BT_FDX (1 << 3)
318#define P1SCLMD_ADV_100BT_HDX (1 << 2)
319#define P1SCLMD_ADV_10BT_FDX (1 << 1)
320#define P1SCLMD_ADV_10BT_HDX (1 << 0)
321
322#define KS_P1CR 0xF6
323#define P1CR_HP_MDIX (1 << 15)
324#define P1CR_REV_POL (1 << 13)
325#define P1CR_OP_100M (1 << 10)
326#define P1CR_OP_FDX (1 << 9)
327#define P1CR_OP_MDI (1 << 7)
328#define P1CR_AN_DONE (1 << 6)
329#define P1CR_LINK_GOOD (1 << 5)
330#define P1CR_PNTR_FLOW (1 << 4)
331#define P1CR_PNTR_100BT_FDX (1 << 3)
332#define P1CR_PNTR_100BT_HDX (1 << 2)
333#define P1CR_PNTR_10BT_FDX (1 << 1)
334#define P1CR_PNTR_10BT_HDX (1 << 0)
335
336/* TX Frame control */
337
338#define TXFR_TXIC (1 << 15)
339#define TXFR_TXFID_MASK (0x3f << 0)
340#define TXFR_TXFID_SHIFT (0)
341
342#define KS_P1SR 0xF8
343#define P1SR_HP_MDIX (1 << 15)
344#define P1SR_REV_POL (1 << 13)
345#define P1SR_OP_100M (1 << 10)
346#define P1SR_OP_FDX (1 << 9)
347#define P1SR_OP_MDI (1 << 7)
348#define P1SR_AN_DONE (1 << 6)
349#define P1SR_LINK_GOOD (1 << 5)
350#define P1SR_PNTR_FLOW (1 << 4)
351#define P1SR_PNTR_100BT_FDX (1 << 3)
352#define P1SR_PNTR_100BT_HDX (1 << 2)
353#define P1SR_PNTR_10BT_FDX (1 << 1)
354#define P1SR_PNTR_10BT_HDX (1 << 0)
355
356#define ENUM_BUS_NONE 0
357#define ENUM_BUS_8BIT 1
358#define ENUM_BUS_16BIT 2
359#define ENUM_BUS_32BIT 3
360
361#define MAX_MCAST_LST 32
362#define HW_MCAST_SIZE 8
363#define MAC_ADDR_LEN 6
364
365/**
366 * union ks_tx_hdr - tx header data
367 * @txb: The header as bytes
368 * @txw: The header as 16bit, little-endian words
369 *
370 * A dual representation of the tx header data to allow
371 * access to individual bytes, and to allow 16bit accesses
372 * with 16bit alignment.
373 */
374union ks_tx_hdr {
375 u8 txb[4];
376 __le16 txw[2];
377};
378
379/**
380 * struct ks_net - KS8851 driver private data
381 * @net_device : The network device we're bound to
382 * @hw_addr : start address of data register.
383 * @hw_addr_cmd : start address of command register.
384 * @txh : temporaly buffer to save status/length.
385 * @lock : Lock to ensure that the device is not accessed when busy.
386 * @pdev : Pointer to platform device.
387 * @mii : The MII state information for the mii calls.
388 * @frame_head_info : frame header information for multi-pkt rx.
389 * @statelock : Lock on this structure for tx list.
390 * @msg_enable : The message flags controlling driver output (see ethtool).
391 * @frame_cnt : number of frames received.
392 * @bus_width : i/o bus width.
393 * @irq : irq number assigned to this device.
394 * @rc_rxqcr : Cached copy of KS_RXQCR.
395 * @rc_txcr : Cached copy of KS_TXCR.
396 * @rc_ier : Cached copy of KS_IER.
397 * @sharedbus : Multipex(addr and data bus) mode indicator.
398 * @cmd_reg_cache : command register cached.
399 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
400 * @promiscuous : promiscuous mode indicator.
401 * @all_mcast : mutlicast indicator.
402 * @mcast_lst_size : size of multicast list.
403 * @mcast_lst : multicast list.
404 * @mcast_bits : multicast enabed.
405 * @mac_addr : MAC address assigned to this device.
406 * @fid : frame id.
407 * @extra_byte : number of extra byte prepended rx pkt.
408 * @enabled : indicator this device works.
409 *
410 * The @lock ensures that the chip is protected when certain operations are
411 * in progress. When the read or write packet transfer is in progress, most
412 * of the chip registers are not accessible until the transfer is finished and
413 * the DMA has been de-asserted.
414 *
415 * The @statelock is used to protect information in the structure which may
416 * need to be accessed via several sources, such as the network driver layer
417 * or one of the work queues.
418 *
419 */
420
421/* Receive multiplex framer header info */
422struct type_frame_head {
423 u16 sts; /* Frame status */
424 u16 len; /* Byte count */
425};
426
427struct ks_net {
428 struct net_device *netdev;
429 void __iomem *hw_addr;
430 void __iomem *hw_addr_cmd;
431 union ks_tx_hdr txh ____cacheline_aligned;
432 struct mutex lock; /* spinlock to be interrupt safe */
433 struct platform_device *pdev;
434 struct mii_if_info mii;
435 struct type_frame_head *frame_head_info;
436 spinlock_t statelock;
437 u32 msg_enable;
438 u32 frame_cnt;
439 int bus_width;
440 int irq;
441
442 u16 rc_rxqcr;
443 u16 rc_txcr;
444 u16 rc_ier;
445 u16 sharedbus;
446 u16 cmd_reg_cache;
447 u16 cmd_reg_cache_int;
448 u16 promiscuous;
449 u16 all_mcast;
450 u16 mcast_lst_size;
451 u8 mcast_lst[MAX_MCAST_LST][MAC_ADDR_LEN];
452 u8 mcast_bits[HW_MCAST_SIZE];
453 u8 mac_addr[6];
454 u8 fid;
455 u8 extra_byte;
456 u8 enabled;
457};
458
459static int msg_enable;
460
461#define ks_info(_ks, _msg...) dev_info(&(_ks)->pdev->dev, _msg)
462#define ks_warn(_ks, _msg...) dev_warn(&(_ks)->pdev->dev, _msg)
463#define ks_dbg(_ks, _msg...) dev_dbg(&(_ks)->pdev->dev, _msg)
464#define ks_err(_ks, _msg...) dev_err(&(_ks)->pdev->dev, _msg)
465
466#define BE3 0x8000 /* Byte Enable 3 */
467#define BE2 0x4000 /* Byte Enable 2 */
468#define BE1 0x2000 /* Byte Enable 1 */
469#define BE0 0x1000 /* Byte Enable 0 */
470
471/**
472 * register read/write calls.
473 *
474 * All these calls issue transactions to access the chip's registers. They
475 * all require that the necessary lock is held to prevent accesses when the
476 * chip is busy transfering packet data (RX/TX FIFO accesses).
477 */
478
479/**
480 * ks_rdreg8 - read 8 bit register from device
481 * @ks : The chip information
482 * @offset: The register address
483 *
484 * Read a 8bit register from the chip, returning the result
485 */
486static u8 ks_rdreg8(struct ks_net *ks, int offset)
487{
488 u16 data;
489 u8 shift_bit = offset & 0x03;
490 u8 shift_data = (offset & 1) << 3;
491 ks->cmd_reg_cache = (u16) offset | (u16)(BE0 << shift_bit);
492 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
493 data = ioread16(ks->hw_addr);
494 return (u8)(data >> shift_data);
495}
496
497/**
498 * ks_rdreg16 - read 16 bit register from device
499 * @ks : The chip information
500 * @offset: The register address
501 *
502 * Read a 16bit register from the chip, returning the result
503 */
504
505static u16 ks_rdreg16(struct ks_net *ks, int offset)
506{
507 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
508 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
509 return ioread16(ks->hw_addr);
510}
511
512/**
513 * ks_wrreg8 - write 8bit register value to chip
514 * @ks: The chip information
515 * @offset: The register address
516 * @value: The value to write
517 *
518 */
519static void ks_wrreg8(struct ks_net *ks, int offset, u8 value)
520{
521 u8 shift_bit = (offset & 0x03);
522 u16 value_write = (u16)(value << ((offset & 1) << 3));
523 ks->cmd_reg_cache = (u16)offset | (BE0 << shift_bit);
524 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
525 iowrite16(value_write, ks->hw_addr);
526}
527
528/**
529 * ks_wrreg16 - write 16bit register value to chip
530 * @ks: The chip information
531 * @offset: The register address
532 * @value: The value to write
533 *
534 */
535
536static void ks_wrreg16(struct ks_net *ks, int offset, u16 value)
537{
538 ks->cmd_reg_cache = (u16)offset | ((BE1 | BE0) << (offset & 0x02));
539 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
540 iowrite16(value, ks->hw_addr);
541}
542
543/**
544 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
545 * @ks: The chip state
546 * @wptr: buffer address to save data
547 * @len: length in byte to read
548 *
549 */
550static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len)
551{
552 len >>= 1;
553 while (len--)
554 *wptr++ = (u16)ioread16(ks->hw_addr);
555}
556
557/**
558 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
559 * @ks: The chip information
560 * @wptr: buffer address
561 * @len: length in byte to write
562 *
563 */
564static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len)
565{
566 len >>= 1;
567 while (len--)
568 iowrite16(*wptr++, ks->hw_addr);
569}
570
David J. Choi4a91ca42009-11-19 15:34:30 +0000571static void ks_disable_int(struct ks_net *ks)
572{
573 ks_wrreg16(ks, KS_IER, 0x0000);
574} /* ks_disable_int */
575
576static void ks_enable_int(struct ks_net *ks)
577{
578 ks_wrreg16(ks, KS_IER, ks->rc_ier);
579} /* ks_enable_int */
580
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000581/**
582 * ks_tx_fifo_space - return the available hardware buffer size.
583 * @ks: The chip information
584 *
585 */
586static inline u16 ks_tx_fifo_space(struct ks_net *ks)
587{
588 return ks_rdreg16(ks, KS_TXMIR) & 0x1fff;
589}
590
591/**
592 * ks_save_cmd_reg - save the command register from the cache.
593 * @ks: The chip information
594 *
595 */
596static inline void ks_save_cmd_reg(struct ks_net *ks)
597{
598 /*ks8851 MLL has a bug to read back the command register.
599 * So rely on software to save the content of command register.
600 */
601 ks->cmd_reg_cache_int = ks->cmd_reg_cache;
602}
603
604/**
605 * ks_restore_cmd_reg - restore the command register from the cache and
606 * write to hardware register.
607 * @ks: The chip information
608 *
609 */
610static inline void ks_restore_cmd_reg(struct ks_net *ks)
611{
612 ks->cmd_reg_cache = ks->cmd_reg_cache_int;
613 iowrite16(ks->cmd_reg_cache, ks->hw_addr_cmd);
614}
615
616/**
617 * ks_set_powermode - set power mode of the device
618 * @ks: The chip information
619 * @pwrmode: The power mode value to write to KS_PMECR.
620 *
621 * Change the power mode of the chip.
622 */
623static void ks_set_powermode(struct ks_net *ks, unsigned pwrmode)
624{
625 unsigned pmecr;
626
627 if (netif_msg_hw(ks))
628 ks_dbg(ks, "setting power mode %d\n", pwrmode);
629
630 ks_rdreg16(ks, KS_GRR);
631 pmecr = ks_rdreg16(ks, KS_PMECR);
632 pmecr &= ~PMECR_PM_MASK;
633 pmecr |= pwrmode;
634
635 ks_wrreg16(ks, KS_PMECR, pmecr);
636}
637
638/**
639 * ks_read_config - read chip configuration of bus width.
640 * @ks: The chip information
641 *
642 */
643static void ks_read_config(struct ks_net *ks)
644{
645 u16 reg_data = 0;
646
647 /* Regardless of bus width, 8 bit read should always work.*/
648 reg_data = ks_rdreg8(ks, KS_CCR) & 0x00FF;
649 reg_data |= ks_rdreg8(ks, KS_CCR+1) << 8;
650
651 /* addr/data bus are multiplexed */
652 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED;
653
654 /* There are garbage data when reading data from QMU,
655 depending on bus-width.
656 */
657
658 if (reg_data & CCR_8BIT) {
659 ks->bus_width = ENUM_BUS_8BIT;
660 ks->extra_byte = 1;
661 } else if (reg_data & CCR_16BIT) {
662 ks->bus_width = ENUM_BUS_16BIT;
663 ks->extra_byte = 2;
664 } else {
665 ks->bus_width = ENUM_BUS_32BIT;
666 ks->extra_byte = 4;
667 }
668}
669
670/**
671 * ks_soft_reset - issue one of the soft reset to the device
672 * @ks: The device state.
673 * @op: The bit(s) to set in the GRR
674 *
675 * Issue the relevant soft-reset command to the device's GRR register
676 * specified by @op.
677 *
678 * Note, the delays are in there as a caution to ensure that the reset
679 * has time to take effect and then complete. Since the datasheet does
680 * not currently specify the exact sequence, we have chosen something
681 * that seems to work with our device.
682 */
683static void ks_soft_reset(struct ks_net *ks, unsigned op)
684{
685 /* Disable interrupt first */
686 ks_wrreg16(ks, KS_IER, 0x0000);
687 ks_wrreg16(ks, KS_GRR, op);
688 mdelay(10); /* wait a short time to effect reset */
689 ks_wrreg16(ks, KS_GRR, 0);
690 mdelay(1); /* wait for condition to clear */
691}
692
693
David J. Choi4a91ca42009-11-19 15:34:30 +0000694void ks_enable_qmu(struct ks_net *ks)
695{
696 u16 w;
697
698 w = ks_rdreg16(ks, KS_TXCR);
699 /* Enables QMU Transmit (TXCR). */
700 ks_wrreg16(ks, KS_TXCR, w | TXCR_TXE);
701
702 /*
703 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
704 * Enable
705 */
706
707 w = ks_rdreg16(ks, KS_RXQCR);
708 ks_wrreg16(ks, KS_RXQCR, w | RXQCR_RXFCTE);
709
710 /* Enables QMU Receive (RXCR1). */
711 w = ks_rdreg16(ks, KS_RXCR1);
712 ks_wrreg16(ks, KS_RXCR1, w | RXCR1_RXE);
713 ks->enabled = true;
714} /* ks_enable_qmu */
715
716static void ks_disable_qmu(struct ks_net *ks)
717{
718 u16 w;
719
720 w = ks_rdreg16(ks, KS_TXCR);
721
722 /* Disables QMU Transmit (TXCR). */
723 w &= ~TXCR_TXE;
724 ks_wrreg16(ks, KS_TXCR, w);
725
726 /* Disables QMU Receive (RXCR1). */
727 w = ks_rdreg16(ks, KS_RXCR1);
728 w &= ~RXCR1_RXE ;
729 ks_wrreg16(ks, KS_RXCR1, w);
730
731 ks->enabled = false;
732
733} /* ks_disable_qmu */
734
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000735/**
736 * ks_read_qmu - read 1 pkt data from the QMU.
737 * @ks: The chip information
738 * @buf: buffer address to save 1 pkt
739 * @len: Pkt length
740 * Here is the sequence to read 1 pkt:
741 * 1. set sudo DMA mode
742 * 2. read prepend data
743 * 3. read pkt data
744 * 4. reset sudo DMA Mode
745 */
746static inline void ks_read_qmu(struct ks_net *ks, u16 *buf, u32 len)
747{
748 u32 r = ks->extra_byte & 0x1 ;
749 u32 w = ks->extra_byte - r;
750
751 /* 1. set sudo DMA mode */
752 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
753 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
754
755 /* 2. read prepend data */
756 /**
757 * read 4 + extra bytes and discard them.
758 * extra bytes for dummy, 2 for status, 2 for len
759 */
760
761 /* use likely(r) for 8 bit access for performance */
762 if (unlikely(r))
763 ioread8(ks->hw_addr);
764 ks_inblk(ks, buf, w + 2 + 2);
765
766 /* 3. read pkt data */
767 ks_inblk(ks, buf, ALIGN(len, 4));
768
769 /* 4. reset sudo DMA Mode */
770 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
771}
772
773/**
774 * ks_rcv - read multiple pkts data from the QMU.
775 * @ks: The chip information
776 * @netdev: The network device being opened.
777 *
778 * Read all of header information before reading pkt content.
779 * It is not allowed only port of pkts in QMU after issuing
780 * interrupt ack.
781 */
782static void ks_rcv(struct ks_net *ks, struct net_device *netdev)
783{
784 u32 i;
785 struct type_frame_head *frame_hdr = ks->frame_head_info;
786 struct sk_buff *skb;
787
788 ks->frame_cnt = ks_rdreg16(ks, KS_RXFCTR) >> 8;
789
790 /* read all header information */
791 for (i = 0; i < ks->frame_cnt; i++) {
792 /* Checking Received packet status */
793 frame_hdr->sts = ks_rdreg16(ks, KS_RXFHSR);
794 /* Get packet len from hardware */
795 frame_hdr->len = ks_rdreg16(ks, KS_RXFHBCR);
796 frame_hdr++;
797 }
798
799 frame_hdr = ks->frame_head_info;
800 while (ks->frame_cnt--) {
801 skb = dev_alloc_skb(frame_hdr->len + 16);
802 if (likely(skb && (frame_hdr->sts & RXFSHR_RXFV) &&
803 (frame_hdr->len < RX_BUF_SIZE) && frame_hdr->len)) {
804 skb_reserve(skb, 2);
805 /* read data block including CRC 4 bytes */
David J. Choi4a91ca42009-11-19 15:34:30 +0000806 ks_read_qmu(ks, (u16 *)skb->data, frame_hdr->len);
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000807 skb_put(skb, frame_hdr->len);
808 skb->dev = netdev;
809 skb->protocol = eth_type_trans(skb, netdev);
810 netif_rx(skb);
811 } else {
812 printk(KERN_ERR "%s: err:skb alloc\n", __func__);
813 ks_wrreg16(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_RRXEF));
814 if (skb)
815 dev_kfree_skb_irq(skb);
816 }
817 frame_hdr++;
818 }
819}
820
821/**
822 * ks_update_link_status - link status update.
823 * @netdev: The network device being opened.
824 * @ks: The chip information
825 *
826 */
827
828static void ks_update_link_status(struct net_device *netdev, struct ks_net *ks)
829{
830 /* check the status of the link */
831 u32 link_up_status;
832 if (ks_rdreg16(ks, KS_P1SR) & P1SR_LINK_GOOD) {
833 netif_carrier_on(netdev);
834 link_up_status = true;
835 } else {
836 netif_carrier_off(netdev);
837 link_up_status = false;
838 }
839 if (netif_msg_link(ks))
840 ks_dbg(ks, "%s: %s\n",
841 __func__, link_up_status ? "UP" : "DOWN");
842}
843
844/**
845 * ks_irq - device interrupt handler
846 * @irq: Interrupt number passed from the IRQ hnalder.
847 * @pw: The private word passed to register_irq(), our struct ks_net.
848 *
849 * This is the handler invoked to find out what happened
850 *
851 * Read the interrupt status, work out what needs to be done and then clear
852 * any of the interrupts that are not needed.
853 */
854
855static irqreturn_t ks_irq(int irq, void *pw)
856{
857 struct ks_net *ks = pw;
858 struct net_device *netdev = ks->netdev;
859 u16 status;
860
861 /*this should be the first in IRQ handler */
862 ks_save_cmd_reg(ks);
863
864 status = ks_rdreg16(ks, KS_ISR);
865 if (unlikely(!status)) {
866 ks_restore_cmd_reg(ks);
867 return IRQ_NONE;
868 }
869
870 ks_wrreg16(ks, KS_ISR, status);
871
872 if (likely(status & IRQ_RXI))
873 ks_rcv(ks, netdev);
874
875 if (unlikely(status & IRQ_LCI))
876 ks_update_link_status(netdev, ks);
877
878 if (unlikely(status & IRQ_TXI))
879 netif_wake_queue(netdev);
880
881 if (unlikely(status & IRQ_LDI)) {
882
883 u16 pmecr = ks_rdreg16(ks, KS_PMECR);
884 pmecr &= ~PMECR_WKEVT_MASK;
885 ks_wrreg16(ks, KS_PMECR, pmecr | PMECR_WKEVT_LINK);
886 }
887
888 /* this should be the last in IRQ handler*/
889 ks_restore_cmd_reg(ks);
890 return IRQ_HANDLED;
891}
892
893
894/**
895 * ks_net_open - open network device
896 * @netdev: The network device being opened.
897 *
898 * Called when the network device is marked active, such as a user executing
899 * 'ifconfig up' on the device.
900 */
901static int ks_net_open(struct net_device *netdev)
902{
903 struct ks_net *ks = netdev_priv(netdev);
904 int err;
905
906#define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW)
907 /* lock the card, even if we may not actually do anything
908 * else at the moment.
909 */
910
911 if (netif_msg_ifup(ks))
912 ks_dbg(ks, "%s - entry\n", __func__);
913
914 /* reset the HW */
David J. Choi4a91ca42009-11-19 15:34:30 +0000915 err = request_irq(ks->irq, ks_irq, KS_INT_FLAGS, DRV_NAME, netdev);
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000916
917 if (err) {
918 printk(KERN_ERR "Failed to request IRQ: %d: %d\n",
919 ks->irq, err);
920 return err;
921 }
922
David J. Choi4a91ca42009-11-19 15:34:30 +0000923 /* wake up powermode to normal mode */
924 ks_set_powermode(ks, PMECR_PM_NORMAL);
925 mdelay(1); /* wait for normal mode to take effect */
926
927 ks_wrreg16(ks, KS_ISR, 0xffff);
928 ks_enable_int(ks);
929 ks_enable_qmu(ks);
930 netif_start_queue(ks->netdev);
931
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000932 if (netif_msg_ifup(ks))
933 ks_dbg(ks, "network device %s up\n", netdev->name);
934
935 return 0;
936}
937
938/**
939 * ks_net_stop - close network device
940 * @netdev: The device being closed.
941 *
942 * Called to close down a network device which has been active. Cancell any
943 * work, shutdown the RX and TX process and then place the chip into a low
944 * power state whilst it is not being used.
945 */
946static int ks_net_stop(struct net_device *netdev)
947{
948 struct ks_net *ks = netdev_priv(netdev);
949
950 if (netif_msg_ifdown(ks))
951 ks_info(ks, "%s: shutting down\n", netdev->name);
952
953 netif_stop_queue(netdev);
954
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000955 mutex_lock(&ks->lock);
956
957 /* turn off the IRQs and ack any outstanding */
958 ks_wrreg16(ks, KS_IER, 0x0000);
959 ks_wrreg16(ks, KS_ISR, 0xffff);
960
David J. Choi4a91ca42009-11-19 15:34:30 +0000961 /* shutdown RX/TX QMU */
962 ks_disable_qmu(ks);
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000963
964 /* set powermode to soft power down to save power */
965 ks_set_powermode(ks, PMECR_PM_SOFTDOWN);
966 free_irq(ks->irq, netdev);
967 mutex_unlock(&ks->lock);
968 return 0;
969}
970
971
972/**
973 * ks_write_qmu - write 1 pkt data to the QMU.
974 * @ks: The chip information
975 * @pdata: buffer address to save 1 pkt
976 * @len: Pkt length in byte
977 * Here is the sequence to write 1 pkt:
978 * 1. set sudo DMA mode
979 * 2. write status/length
980 * 3. write pkt data
981 * 4. reset sudo DMA Mode
982 * 5. reset sudo DMA mode
983 * 6. Wait until pkt is out
984 */
985static void ks_write_qmu(struct ks_net *ks, u8 *pdata, u16 len)
986{
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000987 /* start header at txb[0] to align txw entries */
David J. Choi4a91ca42009-11-19 15:34:30 +0000988 ks->txh.txw[0] = 0;
Choi, Davida55c0a0e2009-09-25 14:42:12 +0000989 ks->txh.txw[1] = cpu_to_le16(len);
990
991 /* 1. set sudo-DMA mode */
992 ks_wrreg8(ks, KS_RXQCR, (ks->rc_rxqcr | RXQCR_SDA) & 0xff);
993 /* 2. write status/lenth info */
994 ks_outblk(ks, ks->txh.txw, 4);
995 /* 3. write pkt data */
996 ks_outblk(ks, (u16 *)pdata, ALIGN(len, 4));
997 /* 4. reset sudo-DMA mode */
998 ks_wrreg8(ks, KS_RXQCR, ks->rc_rxqcr);
999 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
1000 ks_wrreg16(ks, KS_TXQCR, TXQCR_METFE);
1001 /* 6. wait until TXQCR_METFE is auto-cleared */
1002 while (ks_rdreg16(ks, KS_TXQCR) & TXQCR_METFE)
1003 ;
1004}
1005
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001006/**
1007 * ks_start_xmit - transmit packet
1008 * @skb : The buffer to transmit
1009 * @netdev : The device used to transmit the packet.
1010 *
1011 * Called by the network layer to transmit the @skb.
1012 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1013 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1014 */
1015static int ks_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1016{
1017 int retv = NETDEV_TX_OK;
1018 struct ks_net *ks = netdev_priv(netdev);
1019
1020 disable_irq(netdev->irq);
1021 ks_disable_int(ks);
1022 spin_lock(&ks->statelock);
1023
1024 /* Extra space are required:
1025 * 4 byte for alignment, 4 for status/length, 4 for CRC
1026 */
1027
1028 if (likely(ks_tx_fifo_space(ks) >= skb->len + 12)) {
1029 ks_write_qmu(ks, skb->data, skb->len);
1030 dev_kfree_skb(skb);
1031 } else
1032 retv = NETDEV_TX_BUSY;
1033 spin_unlock(&ks->statelock);
1034 ks_enable_int(ks);
1035 enable_irq(netdev->irq);
1036 return retv;
1037}
1038
1039/**
1040 * ks_start_rx - ready to serve pkts
1041 * @ks : The chip information
1042 *
1043 */
1044static void ks_start_rx(struct ks_net *ks)
1045{
1046 u16 cntl;
1047
1048 /* Enables QMU Receive (RXCR1). */
1049 cntl = ks_rdreg16(ks, KS_RXCR1);
1050 cntl |= RXCR1_RXE ;
1051 ks_wrreg16(ks, KS_RXCR1, cntl);
1052} /* ks_start_rx */
1053
1054/**
1055 * ks_stop_rx - stop to serve pkts
1056 * @ks : The chip information
1057 *
1058 */
1059static void ks_stop_rx(struct ks_net *ks)
1060{
1061 u16 cntl;
1062
1063 /* Disables QMU Receive (RXCR1). */
1064 cntl = ks_rdreg16(ks, KS_RXCR1);
1065 cntl &= ~RXCR1_RXE ;
1066 ks_wrreg16(ks, KS_RXCR1, cntl);
1067
1068} /* ks_stop_rx */
1069
1070static unsigned long const ethernet_polynomial = 0x04c11db7U;
1071
1072static unsigned long ether_gen_crc(int length, u8 *data)
1073{
1074 long crc = -1;
1075 while (--length >= 0) {
1076 u8 current_octet = *data++;
1077 int bit;
1078
1079 for (bit = 0; bit < 8; bit++, current_octet >>= 1) {
1080 crc = (crc << 1) ^
1081 ((crc < 0) ^ (current_octet & 1) ?
1082 ethernet_polynomial : 0);
1083 }
1084 }
1085 return (unsigned long)crc;
1086} /* ether_gen_crc */
1087
1088/**
1089* ks_set_grpaddr - set multicast information
1090* @ks : The chip information
1091*/
1092
1093static void ks_set_grpaddr(struct ks_net *ks)
1094{
1095 u8 i;
1096 u32 index, position, value;
1097
1098 memset(ks->mcast_bits, 0, sizeof(u8) * HW_MCAST_SIZE);
1099
1100 for (i = 0; i < ks->mcast_lst_size; i++) {
1101 position = (ether_gen_crc(6, ks->mcast_lst[i]) >> 26) & 0x3f;
1102 index = position >> 3;
1103 value = 1 << (position & 7);
1104 ks->mcast_bits[index] |= (u8)value;
1105 }
1106
1107 for (i = 0; i < HW_MCAST_SIZE; i++) {
1108 if (i & 1) {
1109 ks_wrreg16(ks, (u16)((KS_MAHTR0 + i) & ~1),
1110 (ks->mcast_bits[i] << 8) |
1111 ks->mcast_bits[i - 1]);
1112 }
1113 }
1114} /* ks_set_grpaddr */
1115
1116/*
1117* ks_clear_mcast - clear multicast information
1118*
1119* @ks : The chip information
1120* This routine removes all mcast addresses set in the hardware.
1121*/
1122
1123static void ks_clear_mcast(struct ks_net *ks)
1124{
1125 u16 i, mcast_size;
1126 for (i = 0; i < HW_MCAST_SIZE; i++)
1127 ks->mcast_bits[i] = 0;
1128
1129 mcast_size = HW_MCAST_SIZE >> 2;
1130 for (i = 0; i < mcast_size; i++)
1131 ks_wrreg16(ks, KS_MAHTR0 + (2*i), 0);
1132}
1133
1134static void ks_set_promis(struct ks_net *ks, u16 promiscuous_mode)
1135{
1136 u16 cntl;
1137 ks->promiscuous = promiscuous_mode;
1138 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1139 cntl = ks_rdreg16(ks, KS_RXCR1);
1140
1141 cntl &= ~RXCR1_FILTER_MASK;
1142 if (promiscuous_mode)
1143 /* Enable Promiscuous mode */
1144 cntl |= RXCR1_RXAE | RXCR1_RXINVF;
1145 else
1146 /* Disable Promiscuous mode (default normal mode) */
1147 cntl |= RXCR1_RXPAFMA;
1148
1149 ks_wrreg16(ks, KS_RXCR1, cntl);
1150
1151 if (ks->enabled)
1152 ks_start_rx(ks);
1153
1154} /* ks_set_promis */
1155
1156static void ks_set_mcast(struct ks_net *ks, u16 mcast)
1157{
1158 u16 cntl;
1159
1160 ks->all_mcast = mcast;
1161 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1162 cntl = ks_rdreg16(ks, KS_RXCR1);
1163 cntl &= ~RXCR1_FILTER_MASK;
1164 if (mcast)
1165 /* Enable "Perfect with Multicast address passed mode" */
1166 cntl |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1167 else
1168 /**
1169 * Disable "Perfect with Multicast address passed
1170 * mode" (normal mode).
1171 */
1172 cntl |= RXCR1_RXPAFMA;
1173
1174 ks_wrreg16(ks, KS_RXCR1, cntl);
1175
1176 if (ks->enabled)
1177 ks_start_rx(ks);
1178} /* ks_set_mcast */
1179
1180static void ks_set_rx_mode(struct net_device *netdev)
1181{
1182 struct ks_net *ks = netdev_priv(netdev);
1183 struct dev_mc_list *ptr;
1184
1185 /* Turn on/off promiscuous mode. */
1186 if ((netdev->flags & IFF_PROMISC) == IFF_PROMISC)
1187 ks_set_promis(ks,
1188 (u16)((netdev->flags & IFF_PROMISC) == IFF_PROMISC));
1189 /* Turn on/off all mcast mode. */
1190 else if ((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI)
1191 ks_set_mcast(ks,
1192 (u16)((netdev->flags & IFF_ALLMULTI) == IFF_ALLMULTI));
1193 else
1194 ks_set_promis(ks, false);
1195
1196 if ((netdev->flags & IFF_MULTICAST) && netdev->mc_count) {
1197 if (netdev->mc_count <= MAX_MCAST_LST) {
1198 int i = 0;
1199 for (ptr = netdev->mc_list; ptr; ptr = ptr->next) {
1200 if (!(*ptr->dmi_addr & 1))
1201 continue;
1202 if (i >= MAX_MCAST_LST)
1203 break;
1204 memcpy(ks->mcast_lst[i++], ptr->dmi_addr,
1205 MAC_ADDR_LEN);
1206 }
1207 ks->mcast_lst_size = (u8)i;
1208 ks_set_grpaddr(ks);
1209 } else {
1210 /**
1211 * List too big to support so
1212 * turn on all mcast mode.
1213 */
1214 ks->mcast_lst_size = MAX_MCAST_LST;
1215 ks_set_mcast(ks, true);
1216 }
1217 } else {
1218 ks->mcast_lst_size = 0;
1219 ks_clear_mcast(ks);
1220 }
1221} /* ks_set_rx_mode */
1222
1223static void ks_set_mac(struct ks_net *ks, u8 *data)
1224{
1225 u16 *pw = (u16 *)data;
1226 u16 w, u;
1227
1228 ks_stop_rx(ks); /* Stop receiving for reconfiguration */
1229
1230 u = *pw++;
1231 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1232 ks_wrreg16(ks, KS_MARH, w);
1233
1234 u = *pw++;
1235 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1236 ks_wrreg16(ks, KS_MARM, w);
1237
1238 u = *pw;
1239 w = ((u & 0xFF) << 8) | ((u >> 8) & 0xFF);
1240 ks_wrreg16(ks, KS_MARL, w);
1241
1242 memcpy(ks->mac_addr, data, 6);
1243
1244 if (ks->enabled)
1245 ks_start_rx(ks);
1246}
1247
1248static int ks_set_mac_address(struct net_device *netdev, void *paddr)
1249{
1250 struct ks_net *ks = netdev_priv(netdev);
1251 struct sockaddr *addr = paddr;
1252 u8 *da;
1253
1254 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1255
1256 da = (u8 *)netdev->dev_addr;
1257
1258 ks_set_mac(ks, da);
1259 return 0;
1260}
1261
1262static int ks_net_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
1263{
1264 struct ks_net *ks = netdev_priv(netdev);
1265
1266 if (!netif_running(netdev))
1267 return -EINVAL;
1268
1269 return generic_mii_ioctl(&ks->mii, if_mii(req), cmd, NULL);
1270}
1271
1272static const struct net_device_ops ks_netdev_ops = {
1273 .ndo_open = ks_net_open,
1274 .ndo_stop = ks_net_stop,
1275 .ndo_do_ioctl = ks_net_ioctl,
1276 .ndo_start_xmit = ks_start_xmit,
1277 .ndo_set_mac_address = ks_set_mac_address,
1278 .ndo_set_rx_mode = ks_set_rx_mode,
1279 .ndo_change_mtu = eth_change_mtu,
1280 .ndo_validate_addr = eth_validate_addr,
1281};
1282
1283/* ethtool support */
1284
1285static void ks_get_drvinfo(struct net_device *netdev,
1286 struct ethtool_drvinfo *di)
1287{
1288 strlcpy(di->driver, DRV_NAME, sizeof(di->driver));
1289 strlcpy(di->version, "1.00", sizeof(di->version));
1290 strlcpy(di->bus_info, dev_name(netdev->dev.parent),
1291 sizeof(di->bus_info));
1292}
1293
1294static u32 ks_get_msglevel(struct net_device *netdev)
1295{
1296 struct ks_net *ks = netdev_priv(netdev);
1297 return ks->msg_enable;
1298}
1299
1300static void ks_set_msglevel(struct net_device *netdev, u32 to)
1301{
1302 struct ks_net *ks = netdev_priv(netdev);
1303 ks->msg_enable = to;
1304}
1305
1306static int ks_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1307{
1308 struct ks_net *ks = netdev_priv(netdev);
1309 return mii_ethtool_gset(&ks->mii, cmd);
1310}
1311
1312static int ks_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1313{
1314 struct ks_net *ks = netdev_priv(netdev);
1315 return mii_ethtool_sset(&ks->mii, cmd);
1316}
1317
1318static u32 ks_get_link(struct net_device *netdev)
1319{
1320 struct ks_net *ks = netdev_priv(netdev);
1321 return mii_link_ok(&ks->mii);
1322}
1323
1324static int ks_nway_reset(struct net_device *netdev)
1325{
1326 struct ks_net *ks = netdev_priv(netdev);
1327 return mii_nway_restart(&ks->mii);
1328}
1329
1330static const struct ethtool_ops ks_ethtool_ops = {
1331 .get_drvinfo = ks_get_drvinfo,
1332 .get_msglevel = ks_get_msglevel,
1333 .set_msglevel = ks_set_msglevel,
1334 .get_settings = ks_get_settings,
1335 .set_settings = ks_set_settings,
1336 .get_link = ks_get_link,
1337 .nway_reset = ks_nway_reset,
1338};
1339
1340/* MII interface controls */
1341
1342/**
1343 * ks_phy_reg - convert MII register into a KS8851 register
1344 * @reg: MII register number.
1345 *
1346 * Return the KS8851 register number for the corresponding MII PHY register
1347 * if possible. Return zero if the MII register has no direct mapping to the
1348 * KS8851 register set.
1349 */
1350static int ks_phy_reg(int reg)
1351{
1352 switch (reg) {
1353 case MII_BMCR:
1354 return KS_P1MBCR;
1355 case MII_BMSR:
1356 return KS_P1MBSR;
1357 case MII_PHYSID1:
1358 return KS_PHY1ILR;
1359 case MII_PHYSID2:
1360 return KS_PHY1IHR;
1361 case MII_ADVERTISE:
1362 return KS_P1ANAR;
1363 case MII_LPA:
1364 return KS_P1ANLPR;
1365 }
1366
1367 return 0x0;
1368}
1369
1370/**
1371 * ks_phy_read - MII interface PHY register read.
1372 * @netdev: The network device the PHY is on.
1373 * @phy_addr: Address of PHY (ignored as we only have one)
1374 * @reg: The register to read.
1375 *
1376 * This call reads data from the PHY register specified in @reg. Since the
1377 * device does not support all the MII registers, the non-existant values
1378 * are always returned as zero.
1379 *
1380 * We return zero for unsupported registers as the MII code does not check
1381 * the value returned for any error status, and simply returns it to the
1382 * caller. The mii-tool that the driver was tested with takes any -ve error
1383 * as real PHY capabilities, thus displaying incorrect data to the user.
1384 */
1385static int ks_phy_read(struct net_device *netdev, int phy_addr, int reg)
1386{
1387 struct ks_net *ks = netdev_priv(netdev);
1388 int ksreg;
1389 int result;
1390
1391 ksreg = ks_phy_reg(reg);
1392 if (!ksreg)
1393 return 0x0; /* no error return allowed, so use zero */
1394
1395 mutex_lock(&ks->lock);
1396 result = ks_rdreg16(ks, ksreg);
1397 mutex_unlock(&ks->lock);
1398
1399 return result;
1400}
1401
1402static void ks_phy_write(struct net_device *netdev,
1403 int phy, int reg, int value)
1404{
1405 struct ks_net *ks = netdev_priv(netdev);
1406 int ksreg;
1407
1408 ksreg = ks_phy_reg(reg);
1409 if (ksreg) {
1410 mutex_lock(&ks->lock);
1411 ks_wrreg16(ks, ksreg, value);
1412 mutex_unlock(&ks->lock);
1413 }
1414}
1415
1416/**
1417 * ks_read_selftest - read the selftest memory info.
1418 * @ks: The device state
1419 *
1420 * Read and check the TX/RX memory selftest information.
1421 */
1422static int ks_read_selftest(struct ks_net *ks)
1423{
1424 unsigned both_done = MBIR_TXMBF | MBIR_RXMBF;
1425 int ret = 0;
1426 unsigned rd;
1427
1428 rd = ks_rdreg16(ks, KS_MBIR);
1429
1430 if ((rd & both_done) != both_done) {
1431 ks_warn(ks, "Memory selftest not finished\n");
1432 return 0;
1433 }
1434
1435 if (rd & MBIR_TXMBFA) {
1436 ks_err(ks, "TX memory selftest fails\n");
1437 ret |= 1;
1438 }
1439
1440 if (rd & MBIR_RXMBFA) {
1441 ks_err(ks, "RX memory selftest fails\n");
1442 ret |= 2;
1443 }
1444
1445 ks_info(ks, "the selftest passes\n");
1446 return ret;
1447}
1448
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001449static void ks_setup(struct ks_net *ks)
1450{
1451 u16 w;
1452
1453 /**
1454 * Configure QMU Transmit
1455 */
1456
1457 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1458 ks_wrreg16(ks, KS_TXFDPR, TXFDPR_TXFPAI);
1459
1460 /* Setup Receive Frame Data Pointer Auto-Increment */
1461 ks_wrreg16(ks, KS_RXFDPR, RXFDPR_RXFPAI);
1462
1463 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1464 ks_wrreg16(ks, KS_RXFCTR, 1 & RXFCTR_THRESHOLD_MASK);
1465
1466 /* Setup RxQ Command Control (RXQCR) */
1467 ks->rc_rxqcr = RXQCR_CMD_CNTL;
1468 ks_wrreg16(ks, KS_RXQCR, ks->rc_rxqcr);
1469
1470 /**
1471 * set the force mode to half duplex, default is full duplex
1472 * because if the auto-negotiation fails, most switch uses
1473 * half-duplex.
1474 */
1475
1476 w = ks_rdreg16(ks, KS_P1MBCR);
1477 w &= ~P1MBCR_FORCE_FDX;
1478 ks_wrreg16(ks, KS_P1MBCR, w);
1479
1480 w = TXCR_TXFCE | TXCR_TXPE | TXCR_TXCRC | TXCR_TCGIP;
1481 ks_wrreg16(ks, KS_TXCR, w);
1482
David J. Choi4a91ca42009-11-19 15:34:30 +00001483 w = RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXUE | RXCR1_RXME | RXCR1_RXIPFCC;
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001484
1485 if (ks->promiscuous) /* bPromiscuous */
1486 w |= (RXCR1_RXAE | RXCR1_RXINVF);
1487 else if (ks->all_mcast) /* Multicast address passed mode */
1488 w |= (RXCR1_RXAE | RXCR1_RXMAFMA | RXCR1_RXPAFMA);
1489 else /* Normal mode */
1490 w |= RXCR1_RXPAFMA;
1491
1492 ks_wrreg16(ks, KS_RXCR1, w);
1493} /*ks_setup */
1494
1495
1496static void ks_setup_int(struct ks_net *ks)
1497{
1498 ks->rc_ier = 0x00;
1499 /* Clear the interrupts status of the hardware. */
1500 ks_wrreg16(ks, KS_ISR, 0xffff);
1501
1502 /* Enables the interrupts of the hardware. */
1503 ks->rc_ier = (IRQ_LCI | IRQ_TXI | IRQ_RXI);
1504} /* ks_setup_int */
1505
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001506static int ks_hw_init(struct ks_net *ks)
1507{
1508#define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1509 ks->promiscuous = 0;
1510 ks->all_mcast = 0;
1511 ks->mcast_lst_size = 0;
1512
1513 ks->frame_head_info = (struct type_frame_head *) \
1514 kmalloc(MHEADER_SIZE, GFP_KERNEL);
1515 if (!ks->frame_head_info) {
1516 printk(KERN_ERR "Error: Fail to allocate frame memory\n");
1517 return false;
1518 }
1519
1520 ks_set_mac(ks, KS_DEFAULT_MAC_ADDRESS);
1521 return true;
1522}
1523
1524
1525static int __devinit ks8851_probe(struct platform_device *pdev)
1526{
1527 int err = -ENOMEM;
1528 struct resource *io_d, *io_c;
1529 struct net_device *netdev;
1530 struct ks_net *ks;
1531 u16 id, data;
1532
1533 io_d = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1534 io_c = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1535
1536 if (!request_mem_region(io_d->start, resource_size(io_d), DRV_NAME))
1537 goto err_mem_region;
1538
1539 if (!request_mem_region(io_c->start, resource_size(io_c), DRV_NAME))
1540 goto err_mem_region1;
1541
1542 netdev = alloc_etherdev(sizeof(struct ks_net));
1543 if (!netdev)
1544 goto err_alloc_etherdev;
1545
1546 SET_NETDEV_DEV(netdev, &pdev->dev);
1547
1548 ks = netdev_priv(netdev);
1549 ks->netdev = netdev;
1550 ks->hw_addr = ioremap(io_d->start, resource_size(io_d));
1551
1552 if (!ks->hw_addr)
1553 goto err_ioremap;
1554
1555 ks->hw_addr_cmd = ioremap(io_c->start, resource_size(io_c));
1556 if (!ks->hw_addr_cmd)
1557 goto err_ioremap1;
1558
1559 ks->irq = platform_get_irq(pdev, 0);
1560
1561 if (ks->irq < 0) {
1562 err = ks->irq;
1563 goto err_get_irq;
1564 }
1565
1566 ks->pdev = pdev;
1567
1568 mutex_init(&ks->lock);
1569 spin_lock_init(&ks->statelock);
1570
1571 netdev->netdev_ops = &ks_netdev_ops;
1572 netdev->ethtool_ops = &ks_ethtool_ops;
1573
1574 /* setup mii state */
1575 ks->mii.dev = netdev;
1576 ks->mii.phy_id = 1,
1577 ks->mii.phy_id_mask = 1;
1578 ks->mii.reg_num_mask = 0xf;
1579 ks->mii.mdio_read = ks_phy_read;
1580 ks->mii.mdio_write = ks_phy_write;
1581
1582 ks_info(ks, "message enable is %d\n", msg_enable);
1583 /* set the default message enable */
1584 ks->msg_enable = netif_msg_init(msg_enable, (NETIF_MSG_DRV |
1585 NETIF_MSG_PROBE |
1586 NETIF_MSG_LINK));
1587 ks_read_config(ks);
1588
1589 /* simple check for a valid chip being connected to the bus */
1590 if ((ks_rdreg16(ks, KS_CIDER) & ~CIDER_REV_MASK) != CIDER_ID) {
1591 ks_err(ks, "failed to read device ID\n");
1592 err = -ENODEV;
1593 goto err_register;
1594 }
1595
1596 if (ks_read_selftest(ks)) {
1597 ks_err(ks, "failed to read device ID\n");
1598 err = -ENODEV;
1599 goto err_register;
1600 }
1601
1602 err = register_netdev(netdev);
1603 if (err)
1604 goto err_register;
1605
1606 platform_set_drvdata(pdev, netdev);
1607
1608 ks_soft_reset(ks, GRR_GSR);
1609 ks_hw_init(ks);
David J. Choi4a91ca42009-11-19 15:34:30 +00001610 ks_disable_qmu(ks);
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001611 ks_setup(ks);
1612 ks_setup_int(ks);
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001613 memcpy(netdev->dev_addr, ks->mac_addr, 6);
1614
1615 data = ks_rdreg16(ks, KS_OBCR);
1616 ks_wrreg16(ks, KS_OBCR, data | OBCR_ODS_16MA);
1617
1618 /**
1619 * If you want to use the default MAC addr,
1620 * comment out the 2 functions below.
1621 */
1622
1623 random_ether_addr(netdev->dev_addr);
1624 ks_set_mac(ks, netdev->dev_addr);
1625
1626 id = ks_rdreg16(ks, KS_CIDER);
1627
1628 printk(KERN_INFO DRV_NAME
1629 " Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1630 (id >> 8) & 0xff, (id >> 4) & 0xf, (id >> 1) & 0x7);
1631 return 0;
1632
1633err_register:
1634err_get_irq:
1635 iounmap(ks->hw_addr_cmd);
1636err_ioremap1:
1637 iounmap(ks->hw_addr);
1638err_ioremap:
1639 free_netdev(netdev);
1640err_alloc_etherdev:
1641 release_mem_region(io_c->start, resource_size(io_c));
1642err_mem_region1:
1643 release_mem_region(io_d->start, resource_size(io_d));
1644err_mem_region:
1645 return err;
1646}
1647
1648static int __devexit ks8851_remove(struct platform_device *pdev)
1649{
1650 struct net_device *netdev = platform_get_drvdata(pdev);
1651 struct ks_net *ks = netdev_priv(netdev);
1652 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1653
David J. Choi4a91ca42009-11-19 15:34:30 +00001654 kfree(ks->frame_head_info);
Choi, Davida55c0a0e2009-09-25 14:42:12 +00001655 unregister_netdev(netdev);
1656 iounmap(ks->hw_addr);
1657 free_netdev(netdev);
1658 release_mem_region(iomem->start, resource_size(iomem));
1659 platform_set_drvdata(pdev, NULL);
1660 return 0;
1661
1662}
1663
1664static struct platform_driver ks8851_platform_driver = {
1665 .driver = {
1666 .name = DRV_NAME,
1667 .owner = THIS_MODULE,
1668 },
1669 .probe = ks8851_probe,
1670 .remove = __devexit_p(ks8851_remove),
1671};
1672
1673static int __init ks8851_init(void)
1674{
1675 return platform_driver_register(&ks8851_platform_driver);
1676}
1677
1678static void __exit ks8851_exit(void)
1679{
1680 platform_driver_unregister(&ks8851_platform_driver);
1681}
1682
1683module_init(ks8851_init);
1684module_exit(ks8851_exit);
1685
1686MODULE_DESCRIPTION("KS8851 MLL Network driver");
1687MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1688MODULE_LICENSE("GPL");
1689module_param_named(message, msg_enable, int, 0);
1690MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
1691