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Albert Herranz7657c3a2009-12-17 15:27:20 -08001/*
2 * Freescale eSDHC controller driver.
3 *
Jerry Huangf060bc92012-02-14 14:05:37 +08004 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
Albert Herranz7657c3a2009-12-17 15:27:20 -08005 * Copyright (c) 2009 MontaVista Software, Inc.
6 *
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 */
15
Oded Gabbay66b50a02013-06-27 12:00:05 -040016#include <linux/err.h>
Albert Herranz7657c3a2009-12-17 15:27:20 -080017#include <linux/io.h>
Jerry Huangf060bc92012-02-14 14:05:37 +080018#include <linux/of.h>
Albert Herranz7657c3a2009-12-17 15:27:20 -080019#include <linux/delay.h>
Paul Gortmaker88b47672011-07-03 15:15:51 -040020#include <linux/module.h>
Albert Herranz7657c3a2009-12-17 15:27:20 -080021#include <linux/mmc/host.h>
Shawn Guo38576af2011-05-27 23:48:14 +080022#include "sdhci-pltfm.h"
Wolfram Sang80872e22010-10-15 12:21:03 +020023#include "sdhci-esdhc.h"
Albert Herranz7657c3a2009-12-17 15:27:20 -080024
Jerry Huang137ccd42012-03-08 11:25:02 +080025#define VENDOR_V_22 0x12
Haijun Zhanga4071fb2012-12-04 10:41:28 +080026#define VENDOR_V_23 0x13
yangbo luf4932cf2015-10-08 18:36:36 +080027
28struct sdhci_esdhc {
29 u8 vendor_ver;
30 u8 spec_ver;
31};
32
33/**
34 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
35 * to make it compatible with SD spec.
36 *
37 * @host: pointer to sdhci_host
38 * @spec_reg: SD spec register address
39 * @value: 32bit eSDHC register value on spec_reg address
40 *
41 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
42 * registers are 32 bits. There are differences in register size, register
43 * address, register function, bit position and function between eSDHC spec
44 * and SD spec.
45 *
46 * Return a fixed up register value
47 */
48static u32 esdhc_readl_fixup(struct sdhci_host *host,
49 int spec_reg, u32 value)
Jerry Huang137ccd42012-03-08 11:25:02 +080050{
yangbo luf4932cf2015-10-08 18:36:36 +080051 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang8605e7a2016-02-16 21:08:26 +080052 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
Jerry Huang137ccd42012-03-08 11:25:02 +080053 u32 ret;
54
Jerry Huang137ccd42012-03-08 11:25:02 +080055 /*
56 * The bit of ADMA flag in eSDHC is not compatible with standard
57 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
58 * supported by eSDHC.
59 * And for many FSL eSDHC controller, the reset value of field
yangbo luf4932cf2015-10-08 18:36:36 +080060 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA,
Jerry Huang137ccd42012-03-08 11:25:02 +080061 * only these vendor version is greater than 2.2/0x12 support ADMA.
Jerry Huang137ccd42012-03-08 11:25:02 +080062 */
yangbo luf4932cf2015-10-08 18:36:36 +080063 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) {
64 if (esdhc->vendor_ver > VENDOR_V_22) {
65 ret = value | SDHCI_CAN_DO_ADMA2;
66 return ret;
67 }
Jerry Huang137ccd42012-03-08 11:25:02 +080068 }
yangbo luf4932cf2015-10-08 18:36:36 +080069 ret = value;
Jerry Huang137ccd42012-03-08 11:25:02 +080070 return ret;
71}
72
yangbo luf4932cf2015-10-08 18:36:36 +080073static u16 esdhc_readw_fixup(struct sdhci_host *host,
74 int spec_reg, u32 value)
Albert Herranz7657c3a2009-12-17 15:27:20 -080075{
76 u16 ret;
yangbo luf4932cf2015-10-08 18:36:36 +080077 int shift = (spec_reg & 0x2) * 8;
Albert Herranz7657c3a2009-12-17 15:27:20 -080078
yangbo luf4932cf2015-10-08 18:36:36 +080079 if (spec_reg == SDHCI_HOST_VERSION)
80 ret = value & 0xffff;
Albert Herranz7657c3a2009-12-17 15:27:20 -080081 else
yangbo luf4932cf2015-10-08 18:36:36 +080082 ret = (value >> shift) & 0xffff;
Xu leie51cbc92011-09-09 20:05:46 +080083 return ret;
84}
85
yangbo luf4932cf2015-10-08 18:36:36 +080086static u8 esdhc_readb_fixup(struct sdhci_host *host,
87 int spec_reg, u32 value)
Xu leie51cbc92011-09-09 20:05:46 +080088{
yangbo luf4932cf2015-10-08 18:36:36 +080089 u8 ret;
90 u8 dma_bits;
91 int shift = (spec_reg & 0x3) * 8;
92
93 ret = (value >> shift) & 0xff;
Roy Zangba8c4dc2012-01-13 15:02:01 +080094
95 /*
96 * "DMA select" locates at offset 0x28 in SD specification, but on
97 * P5020 or P3041, it locates at 0x29.
98 */
yangbo luf4932cf2015-10-08 18:36:36 +080099 if (spec_reg == SDHCI_HOST_CONTROL) {
Roy Zangba8c4dc2012-01-13 15:02:01 +0800100 /* DMA select is 22,23 bits in Protocol Control Register */
yangbo luf4932cf2015-10-08 18:36:36 +0800101 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK;
Roy Zangba8c4dc2012-01-13 15:02:01 +0800102 /* fixup the result */
103 ret &= ~SDHCI_CTRL_DMA_MASK;
104 ret |= dma_bits;
105 }
yangbo luf4932cf2015-10-08 18:36:36 +0800106 return ret;
107}
108
109/**
110 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be
111 * written into eSDHC register.
112 *
113 * @host: pointer to sdhci_host
114 * @spec_reg: SD spec register address
115 * @value: 8/16/32bit SD spec register value that would be written
116 * @old_value: 32bit eSDHC register value on spec_reg address
117 *
118 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
119 * registers are 32 bits. There are differences in register size, register
120 * address, register function, bit position and function between eSDHC spec
121 * and SD spec.
122 *
123 * Return a fixed up register value
124 */
125static u32 esdhc_writel_fixup(struct sdhci_host *host,
126 int spec_reg, u32 value, u32 old_value)
127{
128 u32 ret;
129
130 /*
131 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
132 * when SYSCTL[RSTD] is set for some special operations.
133 * No any impact on other operation.
134 */
135 if (spec_reg == SDHCI_INT_ENABLE)
136 ret = value | SDHCI_INT_BLK_GAP;
137 else
138 ret = value;
Roy Zangba8c4dc2012-01-13 15:02:01 +0800139
Albert Herranz7657c3a2009-12-17 15:27:20 -0800140 return ret;
141}
142
yangbo luf4932cf2015-10-08 18:36:36 +0800143static u32 esdhc_writew_fixup(struct sdhci_host *host,
144 int spec_reg, u16 value, u32 old_value)
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800145{
yangbo luf4932cf2015-10-08 18:36:36 +0800146 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
147 int shift = (spec_reg & 0x2) * 8;
148 u32 ret;
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800149
yangbo luf4932cf2015-10-08 18:36:36 +0800150 switch (spec_reg) {
151 case SDHCI_TRANSFER_MODE:
152 /*
153 * Postpone this write, we must do it together with a
154 * command write that is down below. Return old value.
155 */
156 pltfm_host->xfer_mode_shadow = value;
157 return old_value;
158 case SDHCI_COMMAND:
159 ret = (value << 16) | pltfm_host->xfer_mode_shadow;
160 return ret;
161 }
162
163 ret = old_value & (~(0xffff << shift));
164 ret |= (value << shift);
165
166 if (spec_reg == SDHCI_BLOCK_SIZE) {
Albert Herranz7657c3a2009-12-17 15:27:20 -0800167 /*
168 * Two last DMA bits are reserved, and first one is used for
169 * non-standard blksz of 4096 bytes that we don't support
170 * yet. So clear the DMA boundary bits.
171 */
yangbo luf4932cf2015-10-08 18:36:36 +0800172 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0));
Albert Herranz7657c3a2009-12-17 15:27:20 -0800173 }
yangbo luf4932cf2015-10-08 18:36:36 +0800174 return ret;
Albert Herranz7657c3a2009-12-17 15:27:20 -0800175}
176
yangbo luf4932cf2015-10-08 18:36:36 +0800177static u32 esdhc_writeb_fixup(struct sdhci_host *host,
178 int spec_reg, u8 value, u32 old_value)
Albert Herranz7657c3a2009-12-17 15:27:20 -0800179{
yangbo luf4932cf2015-10-08 18:36:36 +0800180 u32 ret;
181 u32 dma_bits;
182 u8 tmp;
183 int shift = (spec_reg & 0x3) * 8;
184
Roy Zangba8c4dc2012-01-13 15:02:01 +0800185 /*
yangbo lu9e4703d2015-10-16 15:44:03 +0800186 * eSDHC doesn't have a standard power control register, so we do
187 * nothing here to avoid incorrect operation.
188 */
189 if (spec_reg == SDHCI_POWER_CONTROL)
190 return old_value;
191 /*
Roy Zangba8c4dc2012-01-13 15:02:01 +0800192 * "DMA select" location is offset 0x28 in SD specification, but on
193 * P5020 or P3041, it's located at 0x29.
194 */
yangbo luf4932cf2015-10-08 18:36:36 +0800195 if (spec_reg == SDHCI_HOST_CONTROL) {
Oded Gabbaydcaff042013-07-05 12:48:35 -0400196 /*
197 * If host control register is not standard, exit
198 * this function
199 */
200 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
yangbo luf4932cf2015-10-08 18:36:36 +0800201 return old_value;
Oded Gabbaydcaff042013-07-05 12:48:35 -0400202
Roy Zangba8c4dc2012-01-13 15:02:01 +0800203 /* DMA select is 22,23 bits in Protocol Control Register */
yangbo luf4932cf2015-10-08 18:36:36 +0800204 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5;
205 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits;
206 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) |
207 (old_value & SDHCI_CTRL_DMA_MASK);
208 ret = (ret & (~0xff)) | tmp;
209
210 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */
211 ret &= ~ESDHC_HOST_CONTROL_RES;
212 return ret;
Roy Zangba8c4dc2012-01-13 15:02:01 +0800213 }
214
yangbo luf4932cf2015-10-08 18:36:36 +0800215 ret = (old_value & (~(0xff << shift))) | (value << shift);
216 return ret;
217}
218
219static u32 esdhc_be_readl(struct sdhci_host *host, int reg)
220{
221 u32 ret;
222 u32 value;
223
224 value = ioread32be(host->ioaddr + reg);
225 ret = esdhc_readl_fixup(host, reg, value);
226
227 return ret;
228}
229
230static u32 esdhc_le_readl(struct sdhci_host *host, int reg)
231{
232 u32 ret;
233 u32 value;
234
235 value = ioread32(host->ioaddr + reg);
236 ret = esdhc_readl_fixup(host, reg, value);
237
238 return ret;
239}
240
241static u16 esdhc_be_readw(struct sdhci_host *host, int reg)
242{
243 u16 ret;
244 u32 value;
245 int base = reg & ~0x3;
246
247 value = ioread32be(host->ioaddr + base);
248 ret = esdhc_readw_fixup(host, reg, value);
249 return ret;
250}
251
252static u16 esdhc_le_readw(struct sdhci_host *host, int reg)
253{
254 u16 ret;
255 u32 value;
256 int base = reg & ~0x3;
257
258 value = ioread32(host->ioaddr + base);
259 ret = esdhc_readw_fixup(host, reg, value);
260 return ret;
261}
262
263static u8 esdhc_be_readb(struct sdhci_host *host, int reg)
264{
265 u8 ret;
266 u32 value;
267 int base = reg & ~0x3;
268
269 value = ioread32be(host->ioaddr + base);
270 ret = esdhc_readb_fixup(host, reg, value);
271 return ret;
272}
273
274static u8 esdhc_le_readb(struct sdhci_host *host, int reg)
275{
276 u8 ret;
277 u32 value;
278 int base = reg & ~0x3;
279
280 value = ioread32(host->ioaddr + base);
281 ret = esdhc_readb_fixup(host, reg, value);
282 return ret;
283}
284
285static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg)
286{
287 u32 value;
288
289 value = esdhc_writel_fixup(host, reg, val, 0);
290 iowrite32be(value, host->ioaddr + reg);
291}
292
293static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg)
294{
295 u32 value;
296
297 value = esdhc_writel_fixup(host, reg, val, 0);
298 iowrite32(value, host->ioaddr + reg);
299}
300
301static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg)
302{
303 int base = reg & ~0x3;
304 u32 value;
305 u32 ret;
306
307 value = ioread32be(host->ioaddr + base);
308 ret = esdhc_writew_fixup(host, reg, val, value);
309 if (reg != SDHCI_TRANSFER_MODE)
310 iowrite32be(ret, host->ioaddr + base);
311}
312
313static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg)
314{
315 int base = reg & ~0x3;
316 u32 value;
317 u32 ret;
318
319 value = ioread32(host->ioaddr + base);
320 ret = esdhc_writew_fixup(host, reg, val, value);
321 if (reg != SDHCI_TRANSFER_MODE)
322 iowrite32(ret, host->ioaddr + base);
323}
324
325static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg)
326{
327 int base = reg & ~0x3;
328 u32 value;
329 u32 ret;
330
331 value = ioread32be(host->ioaddr + base);
332 ret = esdhc_writeb_fixup(host, reg, val, value);
333 iowrite32be(ret, host->ioaddr + base);
334}
335
336static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg)
337{
338 int base = reg & ~0x3;
339 u32 value;
340 u32 ret;
341
342 value = ioread32(host->ioaddr + base);
343 ret = esdhc_writeb_fixup(host, reg, val, value);
344 iowrite32(ret, host->ioaddr + base);
Albert Herranz7657c3a2009-12-17 15:27:20 -0800345}
346
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800347/*
348 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
349 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
350 * and Block Gap Event(IRQSTAT[BGE]) are also set.
351 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
352 * and re-issue the entire read transaction from beginning.
353 */
yangbo luf4932cf2015-10-08 18:36:36 +0800354static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask)
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800355{
yangbo luf4932cf2015-10-08 18:36:36 +0800356 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang8605e7a2016-02-16 21:08:26 +0800357 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800358 bool applicable;
359 dma_addr_t dmastart;
360 dma_addr_t dmanow;
361
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800362 applicable = (intmask & SDHCI_INT_DATA_END) &&
yangbo luf4932cf2015-10-08 18:36:36 +0800363 (intmask & SDHCI_INT_BLK_GAP) &&
364 (esdhc->vendor_ver == VENDOR_V_23);
Haijun Zhanga4071fb2012-12-04 10:41:28 +0800365 if (!applicable)
366 return;
367
368 host->data->error = 0;
369 dmastart = sg_dma_address(host->data->sg);
370 dmanow = dmastart + host->data->bytes_xfered;
371 /*
372 * Force update to the next DMA block boundary.
373 */
374 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
375 SDHCI_DEFAULT_BOUNDARY_SIZE;
376 host->data->bytes_xfered = dmanow - dmastart;
377 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
378}
379
Wolfram Sang80872e22010-10-15 12:21:03 +0200380static int esdhc_of_enable_dma(struct sdhci_host *host)
Albert Herranz7657c3a2009-12-17 15:27:20 -0800381{
yangbo luf4932cf2015-10-08 18:36:36 +0800382 u32 value;
383
384 value = sdhci_readl(host, ESDHC_DMA_SYSCTL);
385 value |= ESDHC_DMA_SNOOP;
386 sdhci_writel(host, value, ESDHC_DMA_SYSCTL);
Albert Herranz7657c3a2009-12-17 15:27:20 -0800387 return 0;
388}
389
Wolfram Sang80872e22010-10-15 12:21:03 +0200390static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
Albert Herranz7657c3a2009-12-17 15:27:20 -0800391{
Shawn Guoe3071482011-07-20 17:13:36 -0400392 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Albert Herranz7657c3a2009-12-17 15:27:20 -0800393
Shawn Guoe3071482011-07-20 17:13:36 -0400394 return pltfm_host->clock;
Albert Herranz7657c3a2009-12-17 15:27:20 -0800395}
396
Wolfram Sang80872e22010-10-15 12:21:03 +0200397static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
Albert Herranz7657c3a2009-12-17 15:27:20 -0800398{
Shawn Guoe3071482011-07-20 17:13:36 -0400399 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Albert Herranz7657c3a2009-12-17 15:27:20 -0800400
Shawn Guoe3071482011-07-20 17:13:36 -0400401 return pltfm_host->clock / 256 / 16;
Albert Herranz7657c3a2009-12-17 15:27:20 -0800402}
403
Jerry Huangf060bc92012-02-14 14:05:37 +0800404static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
405{
yangbo luf4932cf2015-10-08 18:36:36 +0800406 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang8605e7a2016-02-16 21:08:26 +0800407 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
Joakim Tjernlundbd455022015-04-20 23:12:13 +0200408 int pre_div = 1;
Dong Aishengd31fc002013-09-13 19:11:32 +0800409 int div = 1;
410 u32 temp;
411
Russell King1650d0c2014-04-25 12:58:50 +0100412 host->mmc->actual_clock = 0;
413
Dong Aishengd31fc002013-09-13 19:11:32 +0800414 if (clock == 0)
Russell King373073e2014-04-25 12:58:45 +0100415 return;
Dong Aishengd31fc002013-09-13 19:11:32 +0800416
Yangbo Lu77bd2f62015-08-11 10:53:34 +0800417 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
yangbo luf4932cf2015-10-08 18:36:36 +0800418 if (esdhc->vendor_ver < VENDOR_V_23)
Yangbo Lu77bd2f62015-08-11 10:53:34 +0800419 pre_div = 2;
420
Jerry Huangf060bc92012-02-14 14:05:37 +0800421 /* Workaround to reduce the clock frequency for p1010 esdhc */
422 if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
423 if (clock > 20000000)
424 clock -= 5000000;
425 if (clock > 40000000)
426 clock -= 5000000;
427 }
428
Dong Aishengd31fc002013-09-13 19:11:32 +0800429 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
430 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
431 | ESDHC_CLOCK_MASK);
432 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
433
434 while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
435 pre_div *= 2;
436
437 while (host->max_clk / pre_div / div > clock && div < 16)
438 div++;
439
440 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
Dong Aishenge76b8552013-09-13 19:11:37 +0800441 clock, host->max_clk / pre_div / div);
Joakim Tjernlundbd455022015-04-20 23:12:13 +0200442 host->mmc->actual_clock = host->max_clk / pre_div / div;
Dong Aishengd31fc002013-09-13 19:11:32 +0800443 pre_div >>= 1;
444 div--;
445
446 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
447 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
448 | (div << ESDHC_DIVIDER_SHIFT)
449 | (pre_div << ESDHC_PREDIV_SHIFT));
450 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
451 mdelay(1);
Jerry Huangf060bc92012-02-14 14:05:37 +0800452}
453
Russell King2317f562014-04-25 12:57:07 +0100454static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
Oded Gabbay66b50a02013-06-27 12:00:05 -0400455{
456 u32 ctrl;
457
yangbo luf4932cf2015-10-08 18:36:36 +0800458 ctrl = sdhci_readl(host, ESDHC_PROCTL);
459 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK);
Oded Gabbay66b50a02013-06-27 12:00:05 -0400460 switch (width) {
461 case MMC_BUS_WIDTH_8:
yangbo luf4932cf2015-10-08 18:36:36 +0800462 ctrl |= ESDHC_CTRL_8BITBUS;
Oded Gabbay66b50a02013-06-27 12:00:05 -0400463 break;
464
465 case MMC_BUS_WIDTH_4:
yangbo luf4932cf2015-10-08 18:36:36 +0800466 ctrl |= ESDHC_CTRL_4BITBUS;
Oded Gabbay66b50a02013-06-27 12:00:05 -0400467 break;
468
469 default:
Oded Gabbay66b50a02013-06-27 12:00:05 -0400470 break;
471 }
472
yangbo luf4932cf2015-10-08 18:36:36 +0800473 sdhci_writel(host, ctrl, ESDHC_PROCTL);
Oded Gabbay66b50a02013-06-27 12:00:05 -0400474}
475
Alessio Igor Bogani304f0a92014-12-09 09:40:38 +0100476static void esdhc_reset(struct sdhci_host *host, u8 mask)
477{
478 sdhci_reset(host, mask);
479
480 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
481 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
482}
483
Russell King723f7922014-04-25 12:59:46 +0100484#ifdef CONFIG_PM
Russell King723f7922014-04-25 12:59:46 +0100485static u32 esdhc_proctl;
486static int esdhc_of_suspend(struct device *dev)
487{
488 struct sdhci_host *host = dev_get_drvdata(dev);
489
yangbo luf4932cf2015-10-08 18:36:36 +0800490 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL);
Russell King723f7922014-04-25 12:59:46 +0100491
492 return sdhci_suspend_host(host);
493}
494
Ulf Hansson06732b82014-05-23 10:36:44 +0200495static int esdhc_of_resume(struct device *dev)
Russell King723f7922014-04-25 12:59:46 +0100496{
497 struct sdhci_host *host = dev_get_drvdata(dev);
498 int ret = sdhci_resume_host(host);
499
500 if (ret == 0) {
501 /* Isn't this already done by sdhci_resume_host() ? --rmk */
502 esdhc_of_enable_dma(host);
yangbo luf4932cf2015-10-08 18:36:36 +0800503 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
Russell King723f7922014-04-25 12:59:46 +0100504 }
Russell King723f7922014-04-25 12:59:46 +0100505 return ret;
506}
507
508static const struct dev_pm_ops esdhc_pmops = {
Ulf Hansson06732b82014-05-23 10:36:44 +0200509 .suspend = esdhc_of_suspend,
510 .resume = esdhc_of_resume,
Russell King723f7922014-04-25 12:59:46 +0100511};
512#define ESDHC_PMOPS (&esdhc_pmops)
513#else
514#define ESDHC_PMOPS NULL
515#endif
516
yangbo luf4932cf2015-10-08 18:36:36 +0800517static const struct sdhci_ops sdhci_esdhc_be_ops = {
518 .read_l = esdhc_be_readl,
519 .read_w = esdhc_be_readw,
520 .read_b = esdhc_be_readb,
521 .write_l = esdhc_be_writel,
522 .write_w = esdhc_be_writew,
523 .write_b = esdhc_be_writeb,
524 .set_clock = esdhc_of_set_clock,
525 .enable_dma = esdhc_of_enable_dma,
526 .get_max_clock = esdhc_of_get_max_clock,
527 .get_min_clock = esdhc_of_get_min_clock,
528 .adma_workaround = esdhc_of_adma_workaround,
529 .set_bus_width = esdhc_pltfm_set_bus_width,
530 .reset = esdhc_reset,
531 .set_uhs_signaling = sdhci_set_uhs_signaling,
532};
533
534static const struct sdhci_ops sdhci_esdhc_le_ops = {
535 .read_l = esdhc_le_readl,
536 .read_w = esdhc_le_readw,
537 .read_b = esdhc_le_readb,
538 .write_l = esdhc_le_writel,
539 .write_w = esdhc_le_writew,
540 .write_b = esdhc_le_writeb,
541 .set_clock = esdhc_of_set_clock,
542 .enable_dma = esdhc_of_enable_dma,
543 .get_max_clock = esdhc_of_get_max_clock,
544 .get_min_clock = esdhc_of_get_min_clock,
545 .adma_workaround = esdhc_of_adma_workaround,
546 .set_bus_width = esdhc_pltfm_set_bus_width,
547 .reset = esdhc_reset,
548 .set_uhs_signaling = sdhci_set_uhs_signaling,
549};
550
551static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = {
Richard Zhue481e452011-03-21 13:22:13 +0800552 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
Jerry Huang137ccd42012-03-08 11:25:02 +0800553 | SDHCI_QUIRK_NO_CARD_NO_RESET
554 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
yangbo luf4932cf2015-10-08 18:36:36 +0800555 .ops = &sdhci_esdhc_be_ops,
Albert Herranz7657c3a2009-12-17 15:27:20 -0800556};
Shawn Guo38576af2011-05-27 23:48:14 +0800557
yangbo luf4932cf2015-10-08 18:36:36 +0800558static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
559 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
560 | SDHCI_QUIRK_NO_CARD_NO_RESET
561 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
562 .ops = &sdhci_esdhc_le_ops,
563};
564
565static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
566{
567 struct sdhci_pltfm_host *pltfm_host;
568 struct sdhci_esdhc *esdhc;
569 u16 host_ver;
570
571 pltfm_host = sdhci_priv(host);
Jisheng Zhang8605e7a2016-02-16 21:08:26 +0800572 esdhc = sdhci_pltfm_priv(pltfm_host);
yangbo luf4932cf2015-10-08 18:36:36 +0800573
574 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION);
575 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
576 SDHCI_VENDOR_VER_SHIFT;
577 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
yangbo luf4932cf2015-10-08 18:36:36 +0800578}
579
Bill Pembertonc3be1ef2012-11-19 13:23:06 -0500580static int sdhci_esdhc_probe(struct platform_device *pdev)
Shawn Guo38576af2011-05-27 23:48:14 +0800581{
Oded Gabbay66b50a02013-06-27 12:00:05 -0400582 struct sdhci_host *host;
Oded Gabbaydcaff042013-07-05 12:48:35 -0400583 struct device_node *np;
yangbo lu1ef5e492015-11-25 10:05:37 +0800584 struct sdhci_pltfm_host *pltfm_host;
585 struct sdhci_esdhc *esdhc;
Oded Gabbay66b50a02013-06-27 12:00:05 -0400586 int ret;
587
yangbo luf4932cf2015-10-08 18:36:36 +0800588 np = pdev->dev.of_node;
589
590 if (of_get_property(np, "little-endian", NULL))
Jisheng Zhang8605e7a2016-02-16 21:08:26 +0800591 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata,
592 sizeof(struct sdhci_esdhc));
yangbo luf4932cf2015-10-08 18:36:36 +0800593 else
Jisheng Zhang8605e7a2016-02-16 21:08:26 +0800594 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata,
595 sizeof(struct sdhci_esdhc));
yangbo luf4932cf2015-10-08 18:36:36 +0800596
Oded Gabbay66b50a02013-06-27 12:00:05 -0400597 if (IS_ERR(host))
598 return PTR_ERR(host);
599
yangbo luf4932cf2015-10-08 18:36:36 +0800600 esdhc_init(pdev, host);
601
Oded Gabbay66b50a02013-06-27 12:00:05 -0400602 sdhci_get_of_property(pdev);
603
yangbo lu1ef5e492015-11-25 10:05:37 +0800604 pltfm_host = sdhci_priv(host);
Jisheng Zhang8605e7a2016-02-16 21:08:26 +0800605 esdhc = sdhci_pltfm_priv(pltfm_host);
yangbo lu1ef5e492015-11-25 10:05:37 +0800606 if (esdhc->vendor_ver == VENDOR_V_22)
607 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
608
609 if (esdhc->vendor_ver > VENDOR_V_22)
610 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
611
Yangbo Lu74fd5e32015-06-01 13:47:12 +0800612 if (of_device_is_compatible(np, "fsl,p5040-esdhc") ||
613 of_device_is_compatible(np, "fsl,p5020-esdhc") ||
614 of_device_is_compatible(np, "fsl,p4080-esdhc") ||
615 of_device_is_compatible(np, "fsl,p1020-esdhc") ||
Yangbo Luaaa58d02015-09-16 14:36:10 +0800616 of_device_is_compatible(np, "fsl,t1040-esdhc") ||
617 of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
Yangbo Lu74fd5e32015-06-01 13:47:12 +0800618 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
619
yangbo lua22950c2015-10-08 18:36:57 +0800620 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
621 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
622
Oded Gabbaydcaff042013-07-05 12:48:35 -0400623 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
624 /*
625 * Freescale messed up with P2020 as it has a non-standard
626 * host control register
627 */
628 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
629 }
630
Oded Gabbay66b50a02013-06-27 12:00:05 -0400631 /* call to generic mmc_of_parse to support additional capabilities */
Ulf Hanssonf0991402014-12-18 10:41:41 +0100632 ret = mmc_of_parse(host->mmc);
633 if (ret)
634 goto err;
635
Haijun Zhang490104a2013-08-26 09:19:24 +0800636 mmc_of_parse_voltage(np, &host->ocr_mask);
Oded Gabbay66b50a02013-06-27 12:00:05 -0400637
638 ret = sdhci_add_host(host);
639 if (ret)
Ulf Hanssonf0991402014-12-18 10:41:41 +0100640 goto err;
Oded Gabbay66b50a02013-06-27 12:00:05 -0400641
Ulf Hanssonf0991402014-12-18 10:41:41 +0100642 return 0;
643 err:
644 sdhci_pltfm_free(pdev);
Oded Gabbay66b50a02013-06-27 12:00:05 -0400645 return ret;
Shawn Guo38576af2011-05-27 23:48:14 +0800646}
647
Shawn Guo38576af2011-05-27 23:48:14 +0800648static const struct of_device_id sdhci_esdhc_of_match[] = {
649 { .compatible = "fsl,mpc8379-esdhc" },
650 { .compatible = "fsl,mpc8536-esdhc" },
651 { .compatible = "fsl,esdhc" },
652 { }
653};
654MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
655
656static struct platform_driver sdhci_esdhc_driver = {
657 .driver = {
658 .name = "sdhci-esdhc",
Shawn Guo38576af2011-05-27 23:48:14 +0800659 .of_match_table = sdhci_esdhc_of_match,
Russell King723f7922014-04-25 12:59:46 +0100660 .pm = ESDHC_PMOPS,
Shawn Guo38576af2011-05-27 23:48:14 +0800661 },
662 .probe = sdhci_esdhc_probe,
Kevin Haocaebcae2015-02-27 15:47:31 +0800663 .remove = sdhci_pltfm_unregister,
Shawn Guo38576af2011-05-27 23:48:14 +0800664};
665
Axel Lind1f81a62011-11-26 12:55:43 +0800666module_platform_driver(sdhci_esdhc_driver);
Shawn Guo38576af2011-05-27 23:48:14 +0800667
668MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
669MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
670 "Anton Vorontsov <avorontsov@ru.mvista.com>");
671MODULE_LICENSE("GPL v2");