Lennert Buytenhek | abc848c | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Marvell MBUS common definitions. |
| 3 | * |
| 4 | * Copyright (C) 2008 Marvell Semiconductor |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __LINUX_MBUS_H |
| 12 | #define __LINUX_MBUS_H |
| 13 | |
Ezequiel Garcia | 79d9468 | 2013-07-26 10:17:47 -0300 | [diff] [blame] | 14 | struct resource; |
| 15 | |
Lennert Buytenhek | abc848c | 2008-03-27 14:51:39 -0400 | [diff] [blame] | 16 | struct mbus_dram_target_info |
| 17 | { |
| 18 | /* |
| 19 | * The 4-bit MBUS target ID of the DRAM controller. |
| 20 | */ |
| 21 | u8 mbus_dram_target_id; |
| 22 | |
| 23 | /* |
| 24 | * The base address, size, and MBUS attribute ID for each |
| 25 | * of the possible DRAM chip selects. Peripherals are |
| 26 | * required to support at least 4 decode windows. |
| 27 | */ |
| 28 | int num_cs; |
| 29 | struct mbus_dram_window { |
| 30 | u8 cs_index; |
| 31 | u8 mbus_attr; |
| 32 | u32 base; |
| 33 | u32 size; |
| 34 | } cs[4]; |
| 35 | }; |
| 36 | |
Thomas Petazzoni | fddddb5 | 2013-03-21 17:59:14 +0100 | [diff] [blame] | 37 | /* Flags for PCI/PCIe address decoding regions */ |
| 38 | #define MVEBU_MBUS_PCI_IO 0x1 |
| 39 | #define MVEBU_MBUS_PCI_MEM 0x2 |
| 40 | #define MVEBU_MBUS_PCI_WA 0x3 |
| 41 | |
| 42 | /* |
| 43 | * Magic value that explicits that we don't need a remapping-capable |
| 44 | * address decoding window. |
| 45 | */ |
| 46 | #define MVEBU_MBUS_NO_REMAP (0xffffffff) |
| 47 | |
Thomas Petazzoni | 95b80e0 | 2013-03-21 17:59:19 +0100 | [diff] [blame] | 48 | /* Maximum size of a mbus window name */ |
| 49 | #define MVEBU_MBUS_MAX_WINNAME_SZ 32 |
| 50 | |
Andrew Lunn | 63a9332 | 2011-12-07 21:48:07 +0100 | [diff] [blame] | 51 | /* |
| 52 | * The Marvell mbus is to be found only on SOCs from the Orion family |
| 53 | * at the moment. Provide a dummy stub for other architectures. |
| 54 | */ |
| 55 | #ifdef CONFIG_PLAT_ORION |
| 56 | extern const struct mbus_dram_target_info *mv_mbus_dram_info(void); |
| 57 | #else |
| 58 | static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void) |
| 59 | { |
| 60 | return NULL; |
| 61 | } |
| 62 | #endif |
Thomas Petazzoni | fddddb5 | 2013-03-21 17:59:14 +0100 | [diff] [blame] | 63 | |
Thomas Petazzoni | 4749c02 | 2014-11-21 17:00:04 +0100 | [diff] [blame] | 64 | int mvebu_mbus_save_cpu_target(u32 *store_addr); |
Ezequiel Garcia | 79d9468 | 2013-07-26 10:17:47 -0300 | [diff] [blame] | 65 | void mvebu_mbus_get_pcie_mem_aperture(struct resource *res); |
| 66 | void mvebu_mbus_get_pcie_io_aperture(struct resource *res); |
Thomas Petazzoni | 6a63b09 | 2013-07-26 10:17:39 -0300 | [diff] [blame] | 67 | int mvebu_mbus_add_window_remap_by_id(unsigned int target, |
| 68 | unsigned int attribute, |
| 69 | phys_addr_t base, size_t size, |
| 70 | phys_addr_t remap); |
Thomas Petazzoni | 6a63b09 | 2013-07-26 10:17:39 -0300 | [diff] [blame] | 71 | int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, |
| 72 | phys_addr_t base, size_t size); |
Thomas Petazzoni | fddddb5 | 2013-03-21 17:59:14 +0100 | [diff] [blame] | 73 | int mvebu_mbus_del_window(phys_addr_t base, size_t size); |
| 74 | int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base, |
| 75 | size_t mbus_size, phys_addr_t sdram_phys_base, |
| 76 | size_t sdram_size); |
Thomas Petazzoni | 5686a1e | 2014-04-14 15:47:01 +0200 | [diff] [blame] | 77 | int mvebu_mbus_dt_init(bool is_coherent); |
Thomas Petazzoni | fddddb5 | 2013-03-21 17:59:14 +0100 | [diff] [blame] | 78 | |
| 79 | #endif /* __LINUX_MBUS_H */ |