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Russell King97d654f2006-03-15 15:54:37 +00001/*
2 * linux/arch/arm/mach-sa1100/clock.c
3 */
4#include <linux/module.h>
5#include <linux/kernel.h>
Russell King5e1dbdb42008-11-08 20:48:27 +00006#include <linux/device.h>
Russell King97d654f2006-03-15 15:54:37 +00007#include <linux/list.h>
8#include <linux/errno.h>
9#include <linux/err.h>
10#include <linux/string.h>
11#include <linux/clk.h>
12#include <linux/spinlock.h>
Russell Kingd0a9d752007-04-22 10:08:58 +010013#include <linux/mutex.h>
Jett.Zhou4a8f8342011-11-30 14:32:36 +080014#include <linux/io.h>
15#include <linux/clkdev.h>
Russell King97d654f2006-03-15 15:54:37 +000016
Russell Kinga09e64f2008-08-05 16:14:15 +010017#include <mach/hardware.h>
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +010018#include <mach/generic.h>
Russell King97d654f2006-03-15 15:54:37 +000019
Jett.Zhou4a8f8342011-11-30 14:32:36 +080020struct clkops {
21 void (*enable)(struct clk *);
22 void (*disable)(struct clk *);
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +010023 unsigned long (*get_rate)(struct clk *);
Jett.Zhou4a8f8342011-11-30 14:32:36 +080024};
25
Russell King97d654f2006-03-15 15:54:37 +000026struct clk {
Jett.Zhou4a8f8342011-11-30 14:32:36 +080027 const struct clkops *ops;
Russell King97d654f2006-03-15 15:54:37 +000028 unsigned int enabled;
Russell King97d654f2006-03-15 15:54:37 +000029};
30
Jett.Zhou4a8f8342011-11-30 14:32:36 +080031#define DEFINE_CLK(_name, _ops) \
32struct clk clk_##_name = { \
33 .ops = _ops, \
34 }
35
36static DEFINE_SPINLOCK(clocks_lock);
37
38static void clk_gpio27_enable(struct clk *clk)
Russell King97d654f2006-03-15 15:54:37 +000039{
40 /*
41 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
42 * (SA-1110 Developer's Manual, section 9.1.2.1)
43 */
44 GAFR |= GPIO_32_768kHz;
45 GPDR |= GPIO_32_768kHz;
46 TUCR = TUCR_3_6864MHz;
47}
48
Jett.Zhou4a8f8342011-11-30 14:32:36 +080049static void clk_gpio27_disable(struct clk *clk)
Russell King97d654f2006-03-15 15:54:37 +000050{
51 TUCR = 0;
52 GPDR &= ~GPIO_32_768kHz;
53 GAFR &= ~GPIO_32_768kHz;
54}
55
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +010056static void clk_cpu_enable(struct clk *clk)
57{
58}
59
60static void clk_cpu_disable(struct clk *clk)
61{
62}
63
64static unsigned long clk_cpu_get_rate(struct clk *clk)
65{
66 return sa11x0_getspeed(0) * 1000;
67}
68
Russell King5e1dbdb42008-11-08 20:48:27 +000069int clk_enable(struct clk *clk)
70{
71 unsigned long flags;
72
Jett.Zhou4a8f8342011-11-30 14:32:36 +080073 if (clk) {
74 spin_lock_irqsave(&clocks_lock, flags);
75 if (clk->enabled++ == 0)
76 clk->ops->enable(clk);
77 spin_unlock_irqrestore(&clocks_lock, flags);
78 }
79
Russell King97d654f2006-03-15 15:54:37 +000080 return 0;
81}
Russell King5e1dbdb42008-11-08 20:48:27 +000082EXPORT_SYMBOL(clk_enable);
Russell King97d654f2006-03-15 15:54:37 +000083
Russell King5e1dbdb42008-11-08 20:48:27 +000084void clk_disable(struct clk *clk)
Russell King97d654f2006-03-15 15:54:37 +000085{
Russell King5e1dbdb42008-11-08 20:48:27 +000086 unsigned long flags;
Russell King97d654f2006-03-15 15:54:37 +000087
Jett.Zhou4a8f8342011-11-30 14:32:36 +080088 if (clk) {
89 WARN_ON(clk->enabled == 0);
90 spin_lock_irqsave(&clocks_lock, flags);
91 if (--clk->enabled == 0)
92 clk->ops->disable(clk);
93 spin_unlock_irqrestore(&clocks_lock, flags);
94 }
Russell King97d654f2006-03-15 15:54:37 +000095}
Russell King5e1dbdb42008-11-08 20:48:27 +000096EXPORT_SYMBOL(clk_disable);
97
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +010098unsigned long clk_get_rate(struct clk *clk)
99{
100 if (clk && clk->ops && clk->ops->get_rate)
101 return clk->ops->get_rate(clk);
102
103 return 0;
104}
105EXPORT_SYMBOL(clk_get_rate);
106
Jett.Zhou4a8f8342011-11-30 14:32:36 +0800107const struct clkops clk_gpio27_ops = {
108 .enable = clk_gpio27_enable,
109 .disable = clk_gpio27_disable,
110};
111
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +0100112const struct clkops clk_cpu_ops = {
113 .enable = clk_cpu_enable,
114 .disable = clk_cpu_disable,
115 .get_rate = clk_cpu_get_rate,
116};
117
Jett.Zhou4a8f8342011-11-30 14:32:36 +0800118static DEFINE_CLK(gpio27, &clk_gpio27_ops);
119
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +0100120static DEFINE_CLK(cpu, &clk_cpu_ops);
121
Dmitry Eremin-Solenikovee3a4022014-12-21 16:07:43 +0100122static unsigned long clk_36864_get_rate(struct clk *clk)
123{
124 return 3686400;
125}
126
127static struct clkops clk_36864_ops = {
128 .get_rate = clk_36864_get_rate,
129};
130
131static DEFINE_CLK(36864, &clk_36864_ops);
132
Jett.Zhou4a8f8342011-11-30 14:32:36 +0800133static struct clk_lookup sa11xx_clkregs[] = {
134 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
135 CLKDEV_INIT("sa1100-rtc", NULL, NULL),
Dmitry Eremin-Solenikov4faee122014-12-03 18:35:29 +0100136 CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu),
137 CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu),
Dmitry Eremin-Solenikov7faf6d12014-12-03 18:35:53 +0100138 /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */
139 CLKDEV_INIT("1800", NULL, &clk_cpu),
Dmitry Eremin-Solenikovee3a4022014-12-21 16:07:43 +0100140 CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864),
Jett.Zhou4a8f8342011-11-30 14:32:36 +0800141};
142
143static int __init sa11xx_clk_init(void)
Russell King5e1dbdb42008-11-08 20:48:27 +0000144{
Jett.Zhou4a8f8342011-11-30 14:32:36 +0800145 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
146 return 0;
Russell King5e1dbdb42008-11-08 20:48:27 +0000147}
Jett.Zhou4a8f8342011-11-30 14:32:36 +0800148core_initcall(sa11xx_clk_init);