Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Emilio López |
| 3 | * |
| 4 | * Emilio López <emilio@elopez.com.ar> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/clkdev.h> |
| 19 | #include <linux/clk/sunxi.h> |
| 20 | #include <linux/of.h> |
| 21 | #include <linux/of_address.h> |
| 22 | |
| 23 | #include "clk-factors.h" |
| 24 | |
| 25 | static DEFINE_SPINLOCK(clk_lock); |
| 26 | |
| 27 | /** |
| 28 | * sunxi_osc_clk_setup() - Setup function for gatable oscillator |
| 29 | */ |
| 30 | |
| 31 | #define SUNXI_OSC24M_GATE 0 |
| 32 | |
| 33 | static void __init sunxi_osc_clk_setup(struct device_node *node) |
| 34 | { |
| 35 | struct clk *clk; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 36 | struct clk_fixed_rate *fixed; |
| 37 | struct clk_gate *gate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 38 | const char *clk_name = node->name; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 39 | u32 rate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 40 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 41 | /* allocate fixed-rate and gate clock structs */ |
| 42 | fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); |
| 43 | if (!fixed) |
| 44 | return; |
| 45 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
| 46 | if (!gate) { |
| 47 | kfree(fixed); |
| 48 | return; |
| 49 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 50 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 51 | if (of_property_read_u32(node, "clock-frequency", &rate)) |
| 52 | return; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 53 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 54 | /* set up gate and fixed rate properties */ |
| 55 | gate->reg = of_iomap(node, 0); |
| 56 | gate->bit_idx = SUNXI_OSC24M_GATE; |
| 57 | gate->lock = &clk_lock; |
| 58 | fixed->fixed_rate = rate; |
| 59 | |
| 60 | clk = clk_register_composite(NULL, clk_name, |
| 61 | NULL, 0, |
| 62 | NULL, NULL, |
| 63 | &fixed->hw, &clk_fixed_rate_ops, |
| 64 | &gate->hw, &clk_gate_ops, |
| 65 | CLK_IS_ROOT); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 66 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame^] | 67 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 68 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 69 | clk_register_clkdev(clk, clk_name, NULL); |
| 70 | } |
| 71 | } |
| 72 | |
| 73 | |
| 74 | |
| 75 | /** |
| 76 | * sunxi_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
| 77 | * PLL1 rate is calculated as follows |
| 78 | * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
| 79 | * parent_rate is always 24Mhz |
| 80 | */ |
| 81 | |
| 82 | static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 83 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 84 | { |
| 85 | u8 div; |
| 86 | |
| 87 | /* Normalize value to a 6M multiple */ |
| 88 | div = *freq / 6000000; |
| 89 | *freq = 6000000 * div; |
| 90 | |
| 91 | /* we were called to round the frequency, we can now return */ |
| 92 | if (n == NULL) |
| 93 | return; |
| 94 | |
| 95 | /* m is always zero for pll1 */ |
| 96 | *m = 0; |
| 97 | |
| 98 | /* k is 1 only on these cases */ |
| 99 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 100 | *k = 1; |
| 101 | else |
| 102 | *k = 0; |
| 103 | |
| 104 | /* p will be 3 for divs under 10 */ |
| 105 | if (div < 10) |
| 106 | *p = 3; |
| 107 | |
| 108 | /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
| 109 | else if (div < 20 || (div < 32 && (div & 1))) |
| 110 | *p = 2; |
| 111 | |
| 112 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 113 | * of divs between 40-62 */ |
| 114 | else if (div < 40 || (div < 64 && (div & 2))) |
| 115 | *p = 1; |
| 116 | |
| 117 | /* any other entries have p = 0 */ |
| 118 | else |
| 119 | *p = 0; |
| 120 | |
| 121 | /* calculate a suitable n based on k and p */ |
| 122 | div <<= *p; |
| 123 | div /= (*k + 1); |
| 124 | *n = div / 4; |
| 125 | } |
| 126 | |
| 127 | |
| 128 | |
| 129 | /** |
| 130 | * sunxi_get_apb1_factors() - calculates m, p factors for APB1 |
| 131 | * APB1 rate is calculated as follows |
| 132 | * rate = (parent_rate >> p) / (m + 1); |
| 133 | */ |
| 134 | |
| 135 | static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate, |
| 136 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 137 | { |
| 138 | u8 calcm, calcp; |
| 139 | |
| 140 | if (parent_rate < *freq) |
| 141 | *freq = parent_rate; |
| 142 | |
| 143 | parent_rate = (parent_rate + (*freq - 1)) / *freq; |
| 144 | |
| 145 | /* Invalid rate! */ |
| 146 | if (parent_rate > 32) |
| 147 | return; |
| 148 | |
| 149 | if (parent_rate <= 4) |
| 150 | calcp = 0; |
| 151 | else if (parent_rate <= 8) |
| 152 | calcp = 1; |
| 153 | else if (parent_rate <= 16) |
| 154 | calcp = 2; |
| 155 | else |
| 156 | calcp = 3; |
| 157 | |
| 158 | calcm = (parent_rate >> calcp) - 1; |
| 159 | |
| 160 | *freq = (parent_rate >> calcp) / (calcm + 1); |
| 161 | |
| 162 | /* we were called to round the frequency, we can now return */ |
| 163 | if (n == NULL) |
| 164 | return; |
| 165 | |
| 166 | *m = calcm; |
| 167 | *p = calcp; |
| 168 | } |
| 169 | |
| 170 | |
| 171 | |
| 172 | /** |
| 173 | * sunxi_factors_clk_setup() - Setup function for factor clocks |
| 174 | */ |
| 175 | |
| 176 | struct factors_data { |
| 177 | struct clk_factors_config *table; |
| 178 | void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
| 179 | }; |
| 180 | |
| 181 | static struct clk_factors_config pll1_config = { |
| 182 | .nshift = 8, |
| 183 | .nwidth = 5, |
| 184 | .kshift = 4, |
| 185 | .kwidth = 2, |
| 186 | .mshift = 0, |
| 187 | .mwidth = 2, |
| 188 | .pshift = 16, |
| 189 | .pwidth = 2, |
| 190 | }; |
| 191 | |
| 192 | static struct clk_factors_config apb1_config = { |
| 193 | .mshift = 0, |
| 194 | .mwidth = 5, |
| 195 | .pshift = 16, |
| 196 | .pwidth = 2, |
| 197 | }; |
| 198 | |
| 199 | static const __initconst struct factors_data pll1_data = { |
| 200 | .table = &pll1_config, |
| 201 | .getter = sunxi_get_pll1_factors, |
| 202 | }; |
| 203 | |
| 204 | static const __initconst struct factors_data apb1_data = { |
| 205 | .table = &apb1_config, |
| 206 | .getter = sunxi_get_apb1_factors, |
| 207 | }; |
| 208 | |
| 209 | static void __init sunxi_factors_clk_setup(struct device_node *node, |
| 210 | struct factors_data *data) |
| 211 | { |
| 212 | struct clk *clk; |
| 213 | const char *clk_name = node->name; |
| 214 | const char *parent; |
| 215 | void *reg; |
| 216 | |
| 217 | reg = of_iomap(node, 0); |
| 218 | |
| 219 | parent = of_clk_get_parent_name(node, 0); |
| 220 | |
Emilio López | 5a4fe9b | 2013-03-27 18:20:42 -0300 | [diff] [blame] | 221 | clk = clk_register_factors(NULL, clk_name, parent, 0, reg, |
| 222 | data->table, data->getter, &clk_lock); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 223 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame^] | 224 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 225 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 226 | clk_register_clkdev(clk, clk_name, NULL); |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | |
| 231 | |
| 232 | /** |
| 233 | * sunxi_mux_clk_setup() - Setup function for muxes |
| 234 | */ |
| 235 | |
| 236 | #define SUNXI_MUX_GATE_WIDTH 2 |
| 237 | |
| 238 | struct mux_data { |
| 239 | u8 shift; |
| 240 | }; |
| 241 | |
Giacomo A. Catenazzi | 61fd58d | 2013-05-17 10:43:20 -0300 | [diff] [blame] | 242 | static const __initconst struct mux_data cpu_mux_data = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 243 | .shift = 16, |
| 244 | }; |
| 245 | |
| 246 | static const __initconst struct mux_data apb1_mux_data = { |
| 247 | .shift = 24, |
| 248 | }; |
| 249 | |
| 250 | static void __init sunxi_mux_clk_setup(struct device_node *node, |
| 251 | struct mux_data *data) |
| 252 | { |
| 253 | struct clk *clk; |
| 254 | const char *clk_name = node->name; |
Emilio López | 918d7f6 | 2013-03-27 18:20:43 -0300 | [diff] [blame] | 255 | const char *parents[5]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 256 | void *reg; |
| 257 | int i = 0; |
| 258 | |
| 259 | reg = of_iomap(node, 0); |
| 260 | |
| 261 | while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
| 262 | i++; |
| 263 | |
| 264 | clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg, |
| 265 | data->shift, SUNXI_MUX_GATE_WIDTH, |
| 266 | 0, &clk_lock); |
| 267 | |
| 268 | if (clk) { |
| 269 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 270 | clk_register_clkdev(clk, clk_name, NULL); |
| 271 | } |
| 272 | } |
| 273 | |
| 274 | |
| 275 | |
| 276 | /** |
| 277 | * sunxi_divider_clk_setup() - Setup function for simple divider clocks |
| 278 | */ |
| 279 | |
| 280 | #define SUNXI_DIVISOR_WIDTH 2 |
| 281 | |
| 282 | struct div_data { |
| 283 | u8 shift; |
| 284 | u8 pow; |
| 285 | }; |
| 286 | |
| 287 | static const __initconst struct div_data axi_data = { |
| 288 | .shift = 0, |
| 289 | .pow = 0, |
| 290 | }; |
| 291 | |
| 292 | static const __initconst struct div_data ahb_data = { |
| 293 | .shift = 4, |
| 294 | .pow = 1, |
| 295 | }; |
| 296 | |
| 297 | static const __initconst struct div_data apb0_data = { |
| 298 | .shift = 8, |
| 299 | .pow = 1, |
| 300 | }; |
| 301 | |
| 302 | static void __init sunxi_divider_clk_setup(struct device_node *node, |
| 303 | struct div_data *data) |
| 304 | { |
| 305 | struct clk *clk; |
| 306 | const char *clk_name = node->name; |
| 307 | const char *clk_parent; |
| 308 | void *reg; |
| 309 | |
| 310 | reg = of_iomap(node, 0); |
| 311 | |
| 312 | clk_parent = of_clk_get_parent_name(node, 0); |
| 313 | |
| 314 | clk = clk_register_divider(NULL, clk_name, clk_parent, 0, |
| 315 | reg, data->shift, SUNXI_DIVISOR_WIDTH, |
| 316 | data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
| 317 | &clk_lock); |
| 318 | if (clk) { |
| 319 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 320 | clk_register_clkdev(clk, clk_name, NULL); |
| 321 | } |
| 322 | } |
| 323 | |
| 324 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 325 | |
| 326 | /** |
| 327 | * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
| 328 | */ |
| 329 | |
| 330 | #define SUNXI_GATES_MAX_SIZE 64 |
| 331 | |
| 332 | struct gates_data { |
| 333 | DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
| 334 | }; |
| 335 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 336 | static const __initconst struct gates_data sun4i_axi_gates_data = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 337 | .mask = {1}, |
| 338 | }; |
| 339 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 340 | static const __initconst struct gates_data sun4i_ahb_gates_data = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 341 | .mask = {0x7F77FFF, 0x14FB3F}, |
| 342 | }; |
| 343 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 344 | static const __initconst struct gates_data sun5i_a13_ahb_gates_data = { |
| 345 | .mask = {0x107067e7, 0x185111}, |
| 346 | }; |
| 347 | |
| 348 | static const __initconst struct gates_data sun4i_apb0_gates_data = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 349 | .mask = {0x4EF}, |
| 350 | }; |
| 351 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 352 | static const __initconst struct gates_data sun5i_a13_apb0_gates_data = { |
| 353 | .mask = {0x61}, |
| 354 | }; |
| 355 | |
| 356 | static const __initconst struct gates_data sun4i_apb1_gates_data = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 357 | .mask = {0xFF00F7}, |
| 358 | }; |
| 359 | |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 360 | static const __initconst struct gates_data sun5i_a13_apb1_gates_data = { |
| 361 | .mask = {0xa0007}, |
| 362 | }; |
| 363 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 364 | static void __init sunxi_gates_clk_setup(struct device_node *node, |
| 365 | struct gates_data *data) |
| 366 | { |
| 367 | struct clk_onecell_data *clk_data; |
| 368 | const char *clk_parent; |
| 369 | const char *clk_name; |
| 370 | void *reg; |
| 371 | int qty; |
| 372 | int i = 0; |
| 373 | int j = 0; |
| 374 | int ignore; |
| 375 | |
| 376 | reg = of_iomap(node, 0); |
| 377 | |
| 378 | clk_parent = of_clk_get_parent_name(node, 0); |
| 379 | |
| 380 | /* Worst-case size approximation and memory allocation */ |
| 381 | qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); |
| 382 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 383 | if (!clk_data) |
| 384 | return; |
| 385 | clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); |
| 386 | if (!clk_data->clks) { |
| 387 | kfree(clk_data); |
| 388 | return; |
| 389 | } |
| 390 | |
| 391 | for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { |
| 392 | of_property_read_string_index(node, "clock-output-names", |
| 393 | j, &clk_name); |
| 394 | |
| 395 | /* No driver claims this clock, but it should remain gated */ |
| 396 | ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0; |
| 397 | |
| 398 | clk_data->clks[i] = clk_register_gate(NULL, clk_name, |
| 399 | clk_parent, ignore, |
| 400 | reg + 4 * (i/32), i % 32, |
| 401 | 0, &clk_lock); |
| 402 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 403 | |
| 404 | j++; |
| 405 | } |
| 406 | |
| 407 | /* Adjust to the real max */ |
| 408 | clk_data->clk_num = i; |
| 409 | |
| 410 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 411 | } |
| 412 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 413 | /* Matches for of_clk_init */ |
| 414 | static const __initconst struct of_device_id clk_match[] = { |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 415 | {.compatible = "allwinner,sun4i-osc-clk", .data = sunxi_osc_clk_setup,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 416 | {} |
| 417 | }; |
| 418 | |
| 419 | /* Matches for factors clocks */ |
| 420 | static const __initconst struct of_device_id clk_factors_match[] = { |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 421 | {.compatible = "allwinner,sun4i-pll1-clk", .data = &pll1_data,}, |
| 422 | {.compatible = "allwinner,sun4i-apb1-clk", .data = &apb1_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 423 | {} |
| 424 | }; |
| 425 | |
| 426 | /* Matches for divider clocks */ |
| 427 | static const __initconst struct of_device_id clk_div_match[] = { |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 428 | {.compatible = "allwinner,sun4i-axi-clk", .data = &axi_data,}, |
| 429 | {.compatible = "allwinner,sun4i-ahb-clk", .data = &ahb_data,}, |
| 430 | {.compatible = "allwinner,sun4i-apb0-clk", .data = &apb0_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 431 | {} |
| 432 | }; |
| 433 | |
| 434 | /* Matches for mux clocks */ |
| 435 | static const __initconst struct of_device_id clk_mux_match[] = { |
Giacomo A. Catenazzi | 61fd58d | 2013-05-17 10:43:20 -0300 | [diff] [blame] | 436 | {.compatible = "allwinner,sun4i-cpu-clk", .data = &cpu_mux_data,}, |
Emilio López | e327699 | 2013-03-26 23:39:17 -0300 | [diff] [blame] | 437 | {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &apb1_mux_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 438 | {} |
| 439 | }; |
| 440 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 441 | /* Matches for gate clocks */ |
| 442 | static const __initconst struct of_device_id clk_gates_match[] = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 443 | {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, |
| 444 | {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, |
| 445 | {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, |
| 446 | {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, |
| 447 | {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, |
| 448 | {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, |
| 449 | {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 450 | {} |
| 451 | }; |
| 452 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 453 | static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
| 454 | void *function) |
| 455 | { |
| 456 | struct device_node *np; |
| 457 | const struct div_data *data; |
| 458 | const struct of_device_id *match; |
| 459 | void (*setup_function)(struct device_node *, const void *) = function; |
| 460 | |
| 461 | for_each_matching_node(np, clk_match) { |
| 462 | match = of_match_node(clk_match, np); |
| 463 | data = match->data; |
| 464 | setup_function(np, data); |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | void __init sunxi_init_clocks(void) |
| 469 | { |
| 470 | /* Register all the simple sunxi clocks on DT */ |
| 471 | of_clk_init(clk_match); |
| 472 | |
| 473 | /* Register factor clocks */ |
| 474 | of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
| 475 | |
| 476 | /* Register divider clocks */ |
| 477 | of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
| 478 | |
| 479 | /* Register mux clocks */ |
| 480 | of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 481 | |
| 482 | /* Register gate clocks */ |
| 483 | of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 484 | } |