Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> |
| 3 | * Copyright (C) 2007-2009 PetaLogix |
| 4 | * Copyright (C) 2006 Atmark Techno, Inc. |
| 5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public |
| 7 | * License. See the file "COPYING" in the main directory of this archive |
| 8 | * for more details. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/init.h> |
| 12 | #include <linux/irq.h> |
| 13 | #include <asm/page.h> |
| 14 | #include <linux/io.h> |
| 15 | |
| 16 | #include <asm/prom.h> |
| 17 | #include <asm/irq.h> |
| 18 | |
| 19 | #ifdef CONFIG_SELFMOD_INTC |
| 20 | #include <asm/selfmod.h> |
| 21 | #define INTC_BASE BARRIER_BASE_ADDR |
| 22 | #else |
| 23 | static unsigned int intc_baseaddr; |
| 24 | #define INTC_BASE intc_baseaddr |
| 25 | #endif |
| 26 | |
| 27 | unsigned int nr_irq; |
| 28 | |
| 29 | /* No one else should require these constants, so define them locally here. */ |
| 30 | #define ISR 0x00 /* Interrupt Status Register */ |
| 31 | #define IPR 0x04 /* Interrupt Pending Register */ |
| 32 | #define IER 0x08 /* Interrupt Enable Register */ |
| 33 | #define IAR 0x0c /* Interrupt Acknowledge Register */ |
| 34 | #define SIE 0x10 /* Set Interrupt Enable bits */ |
| 35 | #define CIE 0x14 /* Clear Interrupt Enable bits */ |
| 36 | #define IVR 0x18 /* Interrupt Vector Register */ |
| 37 | #define MER 0x1c /* Master Enable Register */ |
| 38 | |
| 39 | #define MER_ME (1<<0) |
| 40 | #define MER_HIE (1<<1) |
| 41 | |
| 42 | static void intc_enable_or_unmask(unsigned int irq) |
| 43 | { |
| 44 | pr_debug("enable_or_unmask: %d\n", irq); |
| 45 | out_be32(INTC_BASE + SIE, 1 << irq); |
| 46 | } |
| 47 | |
| 48 | static void intc_disable_or_mask(unsigned int irq) |
| 49 | { |
| 50 | pr_debug("disable: %d\n", irq); |
| 51 | out_be32(INTC_BASE + CIE, 1 << irq); |
| 52 | } |
| 53 | |
| 54 | static void intc_ack(unsigned int irq) |
| 55 | { |
| 56 | pr_debug("ack: %d\n", irq); |
| 57 | out_be32(INTC_BASE + IAR, 1 << irq); |
| 58 | } |
| 59 | |
| 60 | static void intc_mask_ack(unsigned int irq) |
| 61 | { |
| 62 | unsigned long mask = 1 << irq; |
| 63 | pr_debug("disable_and_ack: %d\n", irq); |
| 64 | out_be32(INTC_BASE + CIE, mask); |
| 65 | out_be32(INTC_BASE + IAR, mask); |
| 66 | } |
| 67 | |
| 68 | static void intc_end(unsigned int irq) |
| 69 | { |
| 70 | unsigned long mask = 1 << irq; |
| 71 | pr_debug("end: %d\n", irq); |
| 72 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { |
| 73 | out_be32(INTC_BASE + SIE, mask); |
| 74 | /* ack level sensitive intr */ |
| 75 | if (irq_desc[irq].status & IRQ_LEVEL) |
| 76 | out_be32(INTC_BASE + IAR, mask); |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | static struct irq_chip intc_dev = { |
| 81 | .name = "Xilinx INTC", |
| 82 | .unmask = intc_enable_or_unmask, |
| 83 | .mask = intc_disable_or_mask, |
| 84 | .ack = intc_ack, |
| 85 | .mask_ack = intc_mask_ack, |
| 86 | .end = intc_end, |
| 87 | }; |
| 88 | |
| 89 | unsigned int get_irq(struct pt_regs *regs) |
| 90 | { |
| 91 | int irq; |
| 92 | |
| 93 | /* |
| 94 | * NOTE: This function is the one that needs to be improved in |
| 95 | * order to handle multiple interrupt controllers. It currently |
| 96 | * is hardcoded to check for interrupts only on the first INTC. |
| 97 | */ |
| 98 | irq = in_be32(INTC_BASE + IVR); |
| 99 | pr_debug("get_irq: %d\n", irq); |
| 100 | |
| 101 | return irq; |
| 102 | } |
| 103 | |
| 104 | void __init init_IRQ(void) |
| 105 | { |
| 106 | u32 i, j, intr_type; |
| 107 | struct device_node *intc = NULL; |
| 108 | #ifdef CONFIG_SELFMOD_INTC |
| 109 | unsigned int intc_baseaddr = 0; |
| 110 | static int arr_func[] = { |
| 111 | (int)&get_irq, |
| 112 | (int)&intc_enable_or_unmask, |
| 113 | (int)&intc_disable_or_mask, |
| 114 | (int)&intc_mask_ack, |
| 115 | (int)&intc_ack, |
| 116 | (int)&intc_end, |
| 117 | 0 |
| 118 | }; |
| 119 | #endif |
| 120 | static char *intc_list[] = { |
| 121 | "xlnx,xps-intc-1.00.a", |
| 122 | "xlnx,opb-intc-1.00.c", |
| 123 | "xlnx,opb-intc-1.00.b", |
| 124 | "xlnx,opb-intc-1.00.a", |
| 125 | NULL |
| 126 | }; |
| 127 | |
| 128 | for (j = 0; intc_list[j] != NULL; j++) { |
| 129 | intc = of_find_compatible_node(NULL, NULL, intc_list[j]); |
| 130 | if (intc) |
| 131 | break; |
| 132 | } |
| 133 | |
| 134 | intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL); |
| 135 | intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE); |
| 136 | nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL); |
| 137 | |
| 138 | intr_type = |
| 139 | *(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL); |
| 140 | if (intr_type >= (1 << nr_irq)) |
| 141 | printk(KERN_INFO " ERROR: Mishmash in king-of-intr param\n"); |
| 142 | |
| 143 | #ifdef CONFIG_SELFMOD_INTC |
| 144 | selfmod_function((int *) arr_func, intc_baseaddr); |
| 145 | #endif |
| 146 | printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n", |
| 147 | intc_list[j], intc_baseaddr, nr_irq, intr_type); |
| 148 | |
| 149 | /* |
| 150 | * Disable all external interrupts until they are |
| 151 | * explicity requested. |
| 152 | */ |
| 153 | out_be32(intc_baseaddr + IER, 0); |
| 154 | |
| 155 | /* Acknowledge any pending interrupts just in case. */ |
| 156 | out_be32(intc_baseaddr + IAR, 0xffffffff); |
| 157 | |
| 158 | /* Turn on the Master Enable. */ |
| 159 | out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); |
| 160 | |
| 161 | for (i = 0; i < nr_irq; ++i) { |
| 162 | if (intr_type & (0x00000001 << i)) { |
| 163 | set_irq_chip_and_handler_name(i, &intc_dev, |
| 164 | handle_edge_irq, intc_dev.name); |
| 165 | irq_desc[i].status &= ~IRQ_LEVEL; |
| 166 | } else { |
| 167 | set_irq_chip_and_handler_name(i, &intc_dev, |
| 168 | handle_level_irq, intc_dev.name); |
| 169 | irq_desc[i].status |= IRQ_LEVEL; |
| 170 | } |
| 171 | } |
| 172 | } |