Chao Xie | 1ec770d | 2014-10-31 10:13:51 +0800 | [diff] [blame] | 1 | /* |
| 2 | * mmp2 clock framework source file |
| 3 | * |
| 4 | * Copyright (C) 2012 Marvell |
| 5 | * Chao Xie <xiechao.mail@gmail.com> |
| 6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public |
| 8 | * License version 2. This program is licensed "as is" without any |
| 9 | * warranty of any kind, whether express or implied. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/spinlock.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/of_address.h> |
| 19 | |
| 20 | #include <dt-bindings/clock/marvell,mmp2.h> |
| 21 | |
| 22 | #include "clk.h" |
| 23 | #include "reset.h" |
| 24 | |
| 25 | #define APBC_RTC 0x0 |
| 26 | #define APBC_TWSI0 0x4 |
| 27 | #define APBC_TWSI1 0x8 |
| 28 | #define APBC_TWSI2 0xc |
| 29 | #define APBC_TWSI3 0x10 |
| 30 | #define APBC_TWSI4 0x7c |
| 31 | #define APBC_TWSI5 0x80 |
| 32 | #define APBC_KPC 0x18 |
| 33 | #define APBC_UART0 0x2c |
| 34 | #define APBC_UART1 0x30 |
| 35 | #define APBC_UART2 0x34 |
| 36 | #define APBC_UART3 0x88 |
| 37 | #define APBC_GPIO 0x38 |
| 38 | #define APBC_PWM0 0x3c |
| 39 | #define APBC_PWM1 0x40 |
| 40 | #define APBC_PWM2 0x44 |
| 41 | #define APBC_PWM3 0x48 |
| 42 | #define APBC_SSP0 0x50 |
| 43 | #define APBC_SSP1 0x54 |
| 44 | #define APBC_SSP2 0x58 |
| 45 | #define APBC_SSP3 0x5c |
| 46 | #define APMU_SDH0 0x54 |
| 47 | #define APMU_SDH1 0x58 |
| 48 | #define APMU_SDH2 0xe8 |
| 49 | #define APMU_SDH3 0xec |
| 50 | #define APMU_USB 0x5c |
| 51 | #define APMU_DISP0 0x4c |
| 52 | #define APMU_DISP1 0x110 |
| 53 | #define APMU_CCIC0 0x50 |
| 54 | #define APMU_CCIC1 0xf4 |
| 55 | #define MPMU_UART_PLL 0x14 |
| 56 | |
| 57 | struct mmp2_clk_unit { |
| 58 | struct mmp_clk_unit unit; |
| 59 | void __iomem *mpmu_base; |
| 60 | void __iomem *apmu_base; |
| 61 | void __iomem *apbc_base; |
| 62 | }; |
| 63 | |
| 64 | static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = { |
| 65 | {MMP2_CLK_CLK32, "clk32", NULL, CLK_IS_ROOT, 32768}, |
| 66 | {MMP2_CLK_VCTCXO, "vctcxo", NULL, CLK_IS_ROOT, 26000000}, |
| 67 | {MMP2_CLK_PLL1, "pll1", NULL, CLK_IS_ROOT, 800000000}, |
| 68 | {MMP2_CLK_PLL2, "pll2", NULL, CLK_IS_ROOT, 960000000}, |
| 69 | {MMP2_CLK_USB_PLL, "usb_pll", NULL, CLK_IS_ROOT, 480000000}, |
| 70 | }; |
| 71 | |
| 72 | static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = { |
| 73 | {MMP2_CLK_PLL1_2, "pll1_2", "pll1", 1, 2, 0}, |
| 74 | {MMP2_CLK_PLL1_4, "pll1_4", "pll1_2", 1, 2, 0}, |
| 75 | {MMP2_CLK_PLL1_8, "pll1_8", "pll1_4", 1, 2, 0}, |
| 76 | {MMP2_CLK_PLL1_16, "pll1_16", "pll1_8", 1, 2, 0}, |
| 77 | {MMP2_CLK_PLL1_20, "pll1_20", "pll1_4", 1, 5, 0}, |
| 78 | {MMP2_CLK_PLL1_3, "pll1_3", "pll1", 1, 3, 0}, |
| 79 | {MMP2_CLK_PLL1_6, "pll1_6", "pll1_3", 1, 2, 0}, |
| 80 | {MMP2_CLK_PLL1_12, "pll1_12", "pll1_6", 1, 2, 0}, |
| 81 | {MMP2_CLK_PLL2_2, "pll2_2", "pll2", 1, 2, 0}, |
| 82 | {MMP2_CLK_PLL2_4, "pll2_4", "pll2_2", 1, 2, 0}, |
| 83 | {MMP2_CLK_PLL2_8, "pll2_8", "pll2_4", 1, 2, 0}, |
| 84 | {MMP2_CLK_PLL2_16, "pll2_16", "pll2_8", 1, 2, 0}, |
| 85 | {MMP2_CLK_PLL2_3, "pll2_3", "pll2", 1, 3, 0}, |
| 86 | {MMP2_CLK_PLL2_6, "pll2_6", "pll2_3", 1, 2, 0}, |
| 87 | {MMP2_CLK_PLL2_12, "pll2_12", "pll2_6", 1, 2, 0}, |
| 88 | {MMP2_CLK_VCTCXO_2, "vctcxo_2", "vctcxo", 1, 2, 0}, |
| 89 | {MMP2_CLK_VCTCXO_4, "vctcxo_4", "vctcxo_2", 1, 2, 0}, |
| 90 | }; |
| 91 | |
| 92 | static struct mmp_clk_factor_masks uart_factor_masks = { |
| 93 | .factor = 2, |
| 94 | .num_mask = 0x1fff, |
| 95 | .den_mask = 0x1fff, |
| 96 | .num_shift = 16, |
| 97 | .den_shift = 0, |
| 98 | }; |
| 99 | |
| 100 | static struct mmp_clk_factor_tbl uart_factor_tbl[] = { |
| 101 | {.num = 14634, .den = 2165}, /*14.745MHZ */ |
| 102 | {.num = 3521, .den = 689}, /*19.23MHZ */ |
| 103 | {.num = 9679, .den = 5728}, /*58.9824MHZ */ |
| 104 | {.num = 15850, .den = 9451}, /*59.429MHZ */ |
| 105 | }; |
| 106 | |
| 107 | static void mmp2_pll_init(struct mmp2_clk_unit *pxa_unit) |
| 108 | { |
| 109 | struct clk *clk; |
| 110 | struct mmp_clk_unit *unit = &pxa_unit->unit; |
| 111 | |
| 112 | mmp_register_fixed_rate_clks(unit, fixed_rate_clks, |
| 113 | ARRAY_SIZE(fixed_rate_clks)); |
| 114 | |
| 115 | mmp_register_fixed_factor_clks(unit, fixed_factor_clks, |
| 116 | ARRAY_SIZE(fixed_factor_clks)); |
| 117 | |
| 118 | clk = mmp_clk_register_factor("uart_pll", "pll1_4", |
| 119 | CLK_SET_RATE_PARENT, |
| 120 | pxa_unit->mpmu_base + MPMU_UART_PLL, |
| 121 | &uart_factor_masks, uart_factor_tbl, |
| 122 | ARRAY_SIZE(uart_factor_tbl), NULL); |
| 123 | mmp_clk_add(unit, MMP2_CLK_UART_PLL, clk); |
| 124 | } |
| 125 | |
| 126 | static DEFINE_SPINLOCK(uart0_lock); |
| 127 | static DEFINE_SPINLOCK(uart1_lock); |
| 128 | static DEFINE_SPINLOCK(uart2_lock); |
| 129 | static const char *uart_parent_names[] = {"uart_pll", "vctcxo"}; |
| 130 | |
| 131 | static DEFINE_SPINLOCK(ssp0_lock); |
| 132 | static DEFINE_SPINLOCK(ssp1_lock); |
| 133 | static DEFINE_SPINLOCK(ssp2_lock); |
| 134 | static DEFINE_SPINLOCK(ssp3_lock); |
| 135 | static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"}; |
| 136 | |
| 137 | static DEFINE_SPINLOCK(reset_lock); |
| 138 | |
| 139 | static struct mmp_param_mux_clk apbc_mux_clks[] = { |
| 140 | {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock}, |
| 141 | {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock}, |
| 142 | {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART2, 4, 3, 0, &uart2_lock}, |
| 143 | {0, "uart3_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART3, 4, 3, 0, &uart2_lock}, |
| 144 | {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock}, |
| 145 | {0, "ssp1_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock}, |
| 146 | {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP2, 4, 3, 0, &ssp2_lock}, |
| 147 | {0, "ssp3_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP3, 4, 3, 0, &ssp3_lock}, |
| 148 | }; |
| 149 | |
| 150 | static struct mmp_param_gate_clk apbc_gate_clks[] = { |
| 151 | {MMP2_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 152 | {MMP2_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 153 | {MMP2_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 154 | {MMP2_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 155 | {MMP2_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 156 | {MMP2_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 157 | {MMP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 158 | {MMP2_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, |
| 159 | {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock}, |
| 160 | {MMP2_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 161 | {MMP2_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 162 | {MMP2_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 163 | {MMP2_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x7, 0x3, 0x0, 0, &reset_lock}, |
| 164 | /* The gate clocks has mux parent. */ |
| 165 | {MMP2_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 0x3, 0x0, 0, &uart0_lock}, |
| 166 | {MMP2_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 0x3, 0x0, 0, &uart1_lock}, |
| 167 | {MMP2_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBC_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock}, |
| 168 | {MMP2_CLK_UART3, "uart3_clk", "uart3_mux", CLK_SET_RATE_PARENT, APBC_UART3, 0x7, 0x3, 0x0, 0, &uart2_lock}, |
| 169 | {MMP2_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x7, 0x3, 0x0, 0, &ssp0_lock}, |
| 170 | {MMP2_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x7, 0x3, 0x0, 0, &ssp1_lock}, |
| 171 | {MMP2_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x7, 0x3, 0x0, 0, &ssp2_lock}, |
| 172 | {MMP2_CLK_SSP3, "ssp3_clk", "ssp3_mux", CLK_SET_RATE_PARENT, APBC_SSP3, 0x7, 0x3, 0x0, 0, &ssp3_lock}, |
| 173 | }; |
| 174 | |
| 175 | static void mmp2_apb_periph_clk_init(struct mmp2_clk_unit *pxa_unit) |
| 176 | { |
| 177 | struct mmp_clk_unit *unit = &pxa_unit->unit; |
| 178 | |
| 179 | mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base, |
| 180 | ARRAY_SIZE(apbc_mux_clks)); |
| 181 | |
| 182 | mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base, |
| 183 | ARRAY_SIZE(apbc_gate_clks)); |
| 184 | } |
| 185 | |
| 186 | static DEFINE_SPINLOCK(sdh_lock); |
| 187 | static const char *sdh_parent_names[] = {"pll1_4", "pll2", "usb_pll", "pll1"}; |
| 188 | static struct mmp_clk_mix_config sdh_mix_config = { |
| 189 | .reg_info = DEFINE_MIX_REG_INFO(4, 10, 2, 8, 32), |
| 190 | }; |
| 191 | |
| 192 | static DEFINE_SPINLOCK(usb_lock); |
| 193 | |
| 194 | static DEFINE_SPINLOCK(disp0_lock); |
| 195 | static DEFINE_SPINLOCK(disp1_lock); |
| 196 | static const char *disp_parent_names[] = {"pll1", "pll1_16", "pll2", "vctcxo"}; |
| 197 | |
| 198 | static DEFINE_SPINLOCK(ccic0_lock); |
| 199 | static DEFINE_SPINLOCK(ccic1_lock); |
| 200 | static const char *ccic_parent_names[] = {"pll1_2", "pll1_16", "vctcxo"}; |
| 201 | static struct mmp_clk_mix_config ccic0_mix_config = { |
| 202 | .reg_info = DEFINE_MIX_REG_INFO(4, 17, 2, 6, 32), |
| 203 | }; |
| 204 | static struct mmp_clk_mix_config ccic1_mix_config = { |
| 205 | .reg_info = DEFINE_MIX_REG_INFO(4, 16, 2, 6, 32), |
| 206 | }; |
| 207 | |
| 208 | static struct mmp_param_mux_clk apmu_mux_clks[] = { |
| 209 | {MMP2_CLK_DISP0_MUX, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 2, 0, &disp0_lock}, |
| 210 | {MMP2_CLK_DISP1_MUX, "disp1_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP1, 6, 2, 0, &disp1_lock}, |
| 211 | }; |
| 212 | |
| 213 | static struct mmp_param_div_clk apmu_div_clks[] = { |
| 214 | {0, "disp0_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 8, 4, 0, &disp0_lock}, |
| 215 | {0, "disp0_sphy_div", "disp0_mux", CLK_SET_RATE_PARENT, APMU_DISP0, 15, 5, 0, &disp0_lock}, |
| 216 | {0, "disp1_div", "disp1_mux", CLK_SET_RATE_PARENT, APMU_DISP1, 8, 4, 0, &disp1_lock}, |
| 217 | {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock}, |
| 218 | {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock}, |
| 219 | }; |
| 220 | |
| 221 | static struct mmp_param_gate_clk apmu_gate_clks[] = { |
| 222 | {MMP2_CLK_USB, "usb_clk", "usb_pll", 0, APMU_USB, 0x9, 0x9, 0x0, 0, &usb_lock}, |
| 223 | /* The gate clocks has mux parent. */ |
| 224 | {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, |
| 225 | {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, |
| 226 | {MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, |
| 227 | {MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock}, |
| 228 | {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock}, |
| 229 | {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock}, |
| 230 | {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock}, |
| 231 | {MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800, 0x0, 0, &ccic0_lock}, |
| 232 | {MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, &ccic0_lock}, |
| 233 | {MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24, 0x0, 0, &ccic0_lock}, |
| 234 | {MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, 0x300, 0x0, 0, &ccic0_lock}, |
| 235 | {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock}, |
| 236 | {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock}, |
| 237 | {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock}, |
| 238 | }; |
| 239 | |
| 240 | static void mmp2_axi_periph_clk_init(struct mmp2_clk_unit *pxa_unit) |
| 241 | { |
| 242 | struct clk *clk; |
| 243 | struct mmp_clk_unit *unit = &pxa_unit->unit; |
| 244 | |
| 245 | sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_SDH0; |
| 246 | clk = mmp_clk_register_mix(NULL, "sdh_mix_clk", sdh_parent_names, |
| 247 | ARRAY_SIZE(sdh_parent_names), |
| 248 | CLK_SET_RATE_PARENT, |
| 249 | &sdh_mix_config, &sdh_lock); |
| 250 | |
| 251 | ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0; |
| 252 | clk = mmp_clk_register_mix(NULL, "ccic0_mix_clk", ccic_parent_names, |
| 253 | ARRAY_SIZE(ccic_parent_names), |
| 254 | CLK_SET_RATE_PARENT, |
| 255 | &ccic0_mix_config, &ccic0_lock); |
| 256 | mmp_clk_add(unit, MMP2_CLK_CCIC0_MIX, clk); |
| 257 | |
| 258 | ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1; |
| 259 | clk = mmp_clk_register_mix(NULL, "ccic1_mix_clk", ccic_parent_names, |
| 260 | ARRAY_SIZE(ccic_parent_names), |
| 261 | CLK_SET_RATE_PARENT, |
| 262 | &ccic1_mix_config, &ccic1_lock); |
| 263 | mmp_clk_add(unit, MMP2_CLK_CCIC1_MIX, clk); |
| 264 | |
| 265 | mmp_register_mux_clks(unit, apmu_mux_clks, pxa_unit->apmu_base, |
| 266 | ARRAY_SIZE(apmu_mux_clks)); |
| 267 | |
| 268 | mmp_register_div_clks(unit, apmu_div_clks, pxa_unit->apmu_base, |
| 269 | ARRAY_SIZE(apmu_div_clks)); |
| 270 | |
| 271 | mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base, |
| 272 | ARRAY_SIZE(apmu_gate_clks)); |
| 273 | } |
| 274 | |
| 275 | static void mmp2_clk_reset_init(struct device_node *np, |
| 276 | struct mmp2_clk_unit *pxa_unit) |
| 277 | { |
| 278 | struct mmp_clk_reset_cell *cells; |
| 279 | int i, nr_resets; |
| 280 | |
| 281 | nr_resets = ARRAY_SIZE(apbc_gate_clks); |
| 282 | cells = kcalloc(nr_resets, sizeof(*cells), GFP_KERNEL); |
| 283 | if (!cells) |
| 284 | return; |
| 285 | |
| 286 | for (i = 0; i < nr_resets; i++) { |
| 287 | cells[i].clk_id = apbc_gate_clks[i].id; |
| 288 | cells[i].reg = pxa_unit->apbc_base + apbc_gate_clks[i].offset; |
| 289 | cells[i].flags = 0; |
| 290 | cells[i].lock = apbc_gate_clks[i].lock; |
| 291 | cells[i].bits = 0x4; |
| 292 | } |
| 293 | |
| 294 | mmp_clk_reset_register(np, cells, nr_resets); |
| 295 | } |
| 296 | |
| 297 | static void __init mmp2_clk_init(struct device_node *np) |
| 298 | { |
| 299 | struct mmp2_clk_unit *pxa_unit; |
| 300 | |
| 301 | pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL); |
| 302 | if (!pxa_unit) |
| 303 | return; |
| 304 | |
| 305 | pxa_unit->mpmu_base = of_iomap(np, 0); |
| 306 | if (!pxa_unit->mpmu_base) { |
| 307 | pr_err("failed to map mpmu registers\n"); |
| 308 | return; |
| 309 | } |
| 310 | |
| 311 | pxa_unit->apmu_base = of_iomap(np, 1); |
| 312 | if (!pxa_unit->mpmu_base) { |
| 313 | pr_err("failed to map apmu registers\n"); |
| 314 | return; |
| 315 | } |
| 316 | |
| 317 | pxa_unit->apbc_base = of_iomap(np, 2); |
| 318 | if (!pxa_unit->apbc_base) { |
| 319 | pr_err("failed to map apbc registers\n"); |
| 320 | return; |
| 321 | } |
| 322 | |
| 323 | mmp_clk_init(np, &pxa_unit->unit, MMP2_NR_CLKS); |
| 324 | |
| 325 | mmp2_pll_init(pxa_unit); |
| 326 | |
| 327 | mmp2_apb_periph_clk_init(pxa_unit); |
| 328 | |
| 329 | mmp2_axi_periph_clk_init(pxa_unit); |
| 330 | |
| 331 | mmp2_clk_reset_init(np, pxa_unit); |
| 332 | } |
| 333 | |
| 334 | CLK_OF_DECLARE(mmp2_clk, "marvell,mmp2-clock", mmp2_clk_init); |