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gerrit-public.fairphone.software / kernel / msm-4.9 / 43154f6fd46bb3bcd363843c9e48f0b8b3a03a08 / . / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob: 6b39e4d0abfb10be139c1ba044fd9132251468a7 [file] [log] [blame]
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
45static int rtl8xxxu_debug;
46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
57
58module_param_named(debug, rtl8xxxu_debug, int, 0600);
59MODULE_PARM_DESC(debug, "Set debug mask");
60module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
61MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
62
63#define USB_VENDOR_ID_REALTEK 0x0bda
64/* Minimum IEEE80211_MAX_FRAME_LEN */
65#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
66#define RTL8XXXU_RX_URBS 32
67#define RTL8XXXU_RX_URB_PENDING_WATER 8
68#define RTL8XXXU_TX_URBS 64
69#define RTL8XXXU_TX_URB_LOW_WATER 25
70#define RTL8XXXU_TX_URB_HIGH_WATER 32
71
72static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
73 struct rtl8xxxu_rx_urb *rx_urb);
74
75static struct ieee80211_rate rtl8xxxu_rates[] = {
76 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
77 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
78 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
79 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
80 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
81 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
82 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
83 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
84 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
85 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
86 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
87 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
88};
89
90static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
91 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
92 .hw_value = 1, .max_power = 30 },
93 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
94 .hw_value = 2, .max_power = 30 },
95 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
96 .hw_value = 3, .max_power = 30 },
97 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
98 .hw_value = 4, .max_power = 30 },
99 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
100 .hw_value = 5, .max_power = 30 },
101 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
102 .hw_value = 6, .max_power = 30 },
103 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
104 .hw_value = 7, .max_power = 30 },
105 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
106 .hw_value = 8, .max_power = 30 },
107 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
108 .hw_value = 9, .max_power = 30 },
109 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
110 .hw_value = 10, .max_power = 30 },
111 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
112 .hw_value = 11, .max_power = 30 },
113 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
114 .hw_value = 12, .max_power = 30 },
115 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
116 .hw_value = 13, .max_power = 30 },
117 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
118 .hw_value = 14, .max_power = 30 }
119};
120
121static struct ieee80211_supported_band rtl8xxxu_supported_band = {
122 .channels = rtl8xxxu_channels_2g,
123 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
124 .bitrates = rtl8xxxu_rates,
125 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
126};
127
128static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
129 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
130 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
131 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
132 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
133 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
134 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
135 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
136 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
137 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
138 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
139 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
140 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
141 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
142 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
143 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
144 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
145 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
146 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
147 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
148 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
149 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
150 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
151};
152
153static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
154 {0x800, 0x80040000}, {0x804, 0x00000003},
155 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
156 {0x810, 0x10001331}, {0x814, 0x020c3d10},
157 {0x818, 0x02200385}, {0x81c, 0x00000000},
158 {0x820, 0x01000100}, {0x824, 0x00390004},
159 {0x828, 0x00000000}, {0x82c, 0x00000000},
160 {0x830, 0x00000000}, {0x834, 0x00000000},
161 {0x838, 0x00000000}, {0x83c, 0x00000000},
162 {0x840, 0x00010000}, {0x844, 0x00000000},
163 {0x848, 0x00000000}, {0x84c, 0x00000000},
164 {0x850, 0x00000000}, {0x854, 0x00000000},
165 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
166 {0x860, 0x66f60110}, {0x864, 0x061f0130},
167 {0x868, 0x00000000}, {0x86c, 0x32323200},
168 {0x870, 0x07000760}, {0x874, 0x22004000},
169 {0x878, 0x00000808}, {0x87c, 0x00000000},
170 {0x880, 0xc0083070}, {0x884, 0x000004d5},
171 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
172 {0x890, 0x00000800}, {0x894, 0xfffffffe},
173 {0x898, 0x40302010}, {0x89c, 0x00706050},
174 {0x900, 0x00000000}, {0x904, 0x00000023},
175 {0x908, 0x00000000}, {0x90c, 0x81121111},
176 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
177 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
178 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
179 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
180 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
181 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
182 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
183 {0xa78, 0x00000900},
184 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
185 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
186 {0xc10, 0x08800000}, {0xc14, 0x40000100},
187 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
188 {0xc20, 0x00000000}, {0xc24, 0x00000000},
189 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
190 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
191 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
192 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
193 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
194 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
195 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
196 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
197 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
198 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
199 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
200 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
201 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
202 {0xc90, 0x00121820}, {0xc94, 0x00000000},
203 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
204 {0xca0, 0x00000000}, {0xca4, 0x00000080},
205 {0xca8, 0x00000000}, {0xcac, 0x00000000},
206 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
207 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
208 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
209 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
210 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
211 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
212 {0xce0, 0x00222222}, {0xce4, 0x00000000},
213 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
214 {0xd00, 0x00080740}, {0xd04, 0x00020401},
215 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
216 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
217 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
218 {0xd30, 0x00000000}, {0xd34, 0x80608000},
219 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
220 {0xd40, 0x00000000}, {0xd44, 0x00000000},
221 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
222 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
223 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
224 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
225 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
226 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
227 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
228 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
229 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
230 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
231 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
232 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
233 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
234 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
235 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
236 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
237 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
238 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
239 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
240 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
241 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
242 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
243 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
244 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
245 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
246 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
247 {0xf00, 0x00000300},
248 {0xffff, 0xffffffff},
249};
250
251static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
252 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
253 {0x800, 0x80040002}, {0x804, 0x00000003},
254 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
255 {0x810, 0x10000330}, {0x814, 0x020c3d10},
256 {0x818, 0x02200385}, {0x81c, 0x00000000},
257 {0x820, 0x01000100}, {0x824, 0x00390004},
258 {0x828, 0x01000100}, {0x82c, 0x00390004},
259 {0x830, 0x27272727}, {0x834, 0x27272727},
260 {0x838, 0x27272727}, {0x83c, 0x27272727},
261 {0x840, 0x00010000}, {0x844, 0x00010000},
262 {0x848, 0x27272727}, {0x84c, 0x27272727},
263 {0x850, 0x00000000}, {0x854, 0x00000000},
264 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
265 {0x860, 0x66e60230}, {0x864, 0x061f0130},
266 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
267 {0x870, 0x07000700}, {0x874, 0x22184000},
268 {0x878, 0x08080808}, {0x87c, 0x00000000},
269 {0x880, 0xc0083070}, {0x884, 0x000004d5},
270 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
271 {0x890, 0x00000800}, {0x894, 0xfffffffe},
272 {0x898, 0x40302010}, {0x89c, 0x00706050},
273 {0x900, 0x00000000}, {0x904, 0x00000023},
274 {0x908, 0x00000000}, {0x90c, 0x81121313},
275 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
276 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
277 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
278 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
279 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
280 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
281 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
282 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
283 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
284 {0xc10, 0x08800000}, {0xc14, 0x40000100},
285 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
286 {0xc20, 0x00000000}, {0xc24, 0x00000000},
287 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
288 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
289 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
290 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
291 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
292 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
293 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
294 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
295 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
296 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
297 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
298 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
299 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
300 {0xc90, 0x00121820}, {0xc94, 0x00000000},
301 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
302 {0xca0, 0x00000000}, {0xca4, 0x00000080},
303 {0xca8, 0x00000000}, {0xcac, 0x00000000},
304 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
305 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
306 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
307 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
308 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
309 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
310 {0xce0, 0x00222222}, {0xce4, 0x00000000},
311 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
312 {0xd00, 0x00080740}, {0xd04, 0x00020403},
313 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
314 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
315 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
316 {0xd30, 0x00000000}, {0xd34, 0x80608000},
317 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
318 {0xd40, 0x00000000}, {0xd44, 0x00000000},
319 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
320 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
321 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
322 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
323 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
324 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
325 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
326 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
327 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
328 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
329 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
330 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
331 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
332 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
333 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
334 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
335 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
336 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
337 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
338 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
339 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
340 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
341 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
342 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
343 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
344 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
345 {0xf00, 0x00000300},
346 {0xffff, 0xffffffff},
347};
348
349static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
350 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
351 {0x040, 0x000c0004}, {0x800, 0x80040000},
352 {0x804, 0x00000001}, {0x808, 0x0000fc00},
353 {0x80c, 0x0000000a}, {0x810, 0x10005388},
354 {0x814, 0x020c3d10}, {0x818, 0x02200385},
355 {0x81c, 0x00000000}, {0x820, 0x01000100},
356 {0x824, 0x00390204}, {0x828, 0x00000000},
357 {0x82c, 0x00000000}, {0x830, 0x00000000},
358 {0x834, 0x00000000}, {0x838, 0x00000000},
359 {0x83c, 0x00000000}, {0x840, 0x00010000},
360 {0x844, 0x00000000}, {0x848, 0x00000000},
361 {0x84c, 0x00000000}, {0x850, 0x00000000},
362 {0x854, 0x00000000}, {0x858, 0x569a569a},
363 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
364 {0x864, 0x061f0130}, {0x868, 0x00000000},
365 {0x86c, 0x20202000}, {0x870, 0x03000300},
366 {0x874, 0x22004000}, {0x878, 0x00000808},
367 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
368 {0x884, 0x000004d5}, {0x888, 0x00000000},
369 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
370 {0x894, 0xfffffffe}, {0x898, 0x40302010},
371 {0x89c, 0x00706050}, {0x900, 0x00000000},
372 {0x904, 0x00000023}, {0x908, 0x00000000},
373 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
374 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
375 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
376 {0xa14, 0x11144028}, {0xa18, 0x00881117},
377 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
378 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
379 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
380 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
381 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
382 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
383 {0xc14, 0x40000100}, {0xc18, 0x08800000},
384 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
385 {0xc24, 0x00000000}, {0xc28, 0x00000000},
386 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
387 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
388 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
389 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
390 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
391 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
392 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
393 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
394 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
395 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
396 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
397 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
398 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
399 {0xc94, 0x00000000}, {0xc98, 0x00121820},
400 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
401 {0xca4, 0x00000080}, {0xca8, 0x00000000},
402 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
403 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
404 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
405 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
406 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
407 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
408 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
409 {0xce4, 0x00000000}, {0xce8, 0x37644302},
410 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
411 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
412 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
413 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
414 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
415 {0xd34, 0x80608000}, {0xd38, 0x00000000},
416 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
417 {0xd44, 0x00000000}, {0xd48, 0x00000000},
418 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
419 {0xd54, 0x00000000}, {0xd58, 0x00000000},
420 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
421 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
422 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
423 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
424 {0xe00, 0x24242424}, {0xe04, 0x24242424},
425 {0xe08, 0x03902024}, {0xe10, 0x24242424},
426 {0xe14, 0x24242424}, {0xe18, 0x24242424},
427 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
428 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
429 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
430 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
431 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
432 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
433 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
434 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
435 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
436 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
437 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
438 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
439 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
440 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
441 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
442 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
443 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
444 {0xf00, 0x00000300},
445 {0xffff, 0xffffffff},
446};
447
448static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
449 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
450 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
451 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
452 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
453 {0xc78, 0x78080001}, {0xc78, 0x77090001},
454 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
455 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
456 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
457 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
458 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
459 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
460 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
461 {0xc78, 0x68180001}, {0xc78, 0x67190001},
462 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
463 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
464 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
465 {0xc78, 0x60200001}, {0xc78, 0x49210001},
466 {0xc78, 0x48220001}, {0xc78, 0x47230001},
467 {0xc78, 0x46240001}, {0xc78, 0x45250001},
468 {0xc78, 0x44260001}, {0xc78, 0x43270001},
469 {0xc78, 0x42280001}, {0xc78, 0x41290001},
470 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
471 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
472 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
473 {0xc78, 0x21300001}, {0xc78, 0x20310001},
474 {0xc78, 0x06320001}, {0xc78, 0x05330001},
475 {0xc78, 0x04340001}, {0xc78, 0x03350001},
476 {0xc78, 0x02360001}, {0xc78, 0x01370001},
477 {0xc78, 0x00380001}, {0xc78, 0x00390001},
478 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
479 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
480 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
481 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
482 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
483 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
484 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
485 {0xc78, 0x78480001}, {0xc78, 0x77490001},
486 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
487 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
488 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
489 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
490 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
491 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
492 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
493 {0xc78, 0x68580001}, {0xc78, 0x67590001},
494 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
495 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
496 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
497 {0xc78, 0x60600001}, {0xc78, 0x49610001},
498 {0xc78, 0x48620001}, {0xc78, 0x47630001},
499 {0xc78, 0x46640001}, {0xc78, 0x45650001},
500 {0xc78, 0x44660001}, {0xc78, 0x43670001},
501 {0xc78, 0x42680001}, {0xc78, 0x41690001},
502 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
503 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
504 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
505 {0xc78, 0x21700001}, {0xc78, 0x20710001},
506 {0xc78, 0x06720001}, {0xc78, 0x05730001},
507 {0xc78, 0x04740001}, {0xc78, 0x03750001},
508 {0xc78, 0x02760001}, {0xc78, 0x01770001},
509 {0xc78, 0x00780001}, {0xc78, 0x00790001},
510 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
511 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
512 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
513 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
514 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
515 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
516 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
517 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
518 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
519 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
520 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
521 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
522 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
523 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
524 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
525 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
526 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
527 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
528 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
529 {0xffff, 0xffffffff}
530};
531
532static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
533 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
534 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
535 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
536 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
537 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
538 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
539 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
540 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
541 {0xc78, 0x73100001}, {0xc78, 0x72110001},
542 {0xc78, 0x71120001}, {0xc78, 0x70130001},
543 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
544 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
545 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
546 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
547 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
548 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
549 {0xc78, 0x63200001}, {0xc78, 0x62210001},
550 {0xc78, 0x61220001}, {0xc78, 0x60230001},
551 {0xc78, 0x46240001}, {0xc78, 0x45250001},
552 {0xc78, 0x44260001}, {0xc78, 0x43270001},
553 {0xc78, 0x42280001}, {0xc78, 0x41290001},
554 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
555 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
556 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
557 {0xc78, 0x21300001}, {0xc78, 0x20310001},
558 {0xc78, 0x06320001}, {0xc78, 0x05330001},
559 {0xc78, 0x04340001}, {0xc78, 0x03350001},
560 {0xc78, 0x02360001}, {0xc78, 0x01370001},
561 {0xc78, 0x00380001}, {0xc78, 0x00390001},
562 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
563 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
564 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
565 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
566 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
567 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
568 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
569 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
570 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
571 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
572 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
573 {0xc78, 0x73500001}, {0xc78, 0x72510001},
574 {0xc78, 0x71520001}, {0xc78, 0x70530001},
575 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
576 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
577 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
578 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
579 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
580 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
581 {0xc78, 0x63600001}, {0xc78, 0x62610001},
582 {0xc78, 0x61620001}, {0xc78, 0x60630001},
583 {0xc78, 0x46640001}, {0xc78, 0x45650001},
584 {0xc78, 0x44660001}, {0xc78, 0x43670001},
585 {0xc78, 0x42680001}, {0xc78, 0x41690001},
586 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
587 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
588 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
589 {0xc78, 0x21700001}, {0xc78, 0x20710001},
590 {0xc78, 0x06720001}, {0xc78, 0x05730001},
591 {0xc78, 0x04740001}, {0xc78, 0x03750001},
592 {0xc78, 0x02760001}, {0xc78, 0x01770001},
593 {0xc78, 0x00780001}, {0xc78, 0x00790001},
594 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
595 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
596 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
597 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
598 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
599 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
600 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
601 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
602 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
603 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
604 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
605 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
606 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
607 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
608 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
609 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
610 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
611 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
612 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
613 {0xffff, 0xffffffff}
614};
615
616static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
617 {0x00, 0x00030159}, {0x01, 0x00031284},
618 {0x02, 0x00098000}, {0x03, 0x00039c63},
619 {0x04, 0x000210e7}, {0x09, 0x0002044f},
620 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
621 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
622 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
623 {0x19, 0x00000000}, {0x1a, 0x00030355},
624 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
625 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
626 {0x1f, 0x00000000}, {0x20, 0x0000b614},
627 {0x21, 0x0006c000}, {0x22, 0x00000000},
628 {0x23, 0x00001558}, {0x24, 0x00000060},
629 {0x25, 0x00000483}, {0x26, 0x0004f000},
630 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
631 {0x29, 0x00004783}, {0x2a, 0x00000001},
632 {0x2b, 0x00021334}, {0x2a, 0x00000000},
633 {0x2b, 0x00000054}, {0x2a, 0x00000001},
634 {0x2b, 0x00000808}, {0x2b, 0x00053333},
635 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
636 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
637 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
638 {0x2b, 0x00000808}, {0x2b, 0x00063333},
639 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
640 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
641 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
642 {0x2b, 0x00000808}, {0x2b, 0x00073333},
643 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
644 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
645 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
646 {0x2b, 0x00000709}, {0x2b, 0x00063333},
647 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
648 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
649 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
650 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
651 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
652 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
653 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
654 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
655 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
656 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
657 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
658 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
659 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
660 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
661 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
662 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
663 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
664 {0x10, 0x0002000f}, {0x11, 0x000203f9},
665 {0x10, 0x0003000f}, {0x11, 0x000ff500},
666 {0x10, 0x00000000}, {0x11, 0x00000000},
667 {0x10, 0x0008000f}, {0x11, 0x0003f100},
668 {0x10, 0x0009000f}, {0x11, 0x00023100},
669 {0x12, 0x00032000}, {0x12, 0x00071000},
670 {0x12, 0x000b0000}, {0x12, 0x000fc000},
671 {0x13, 0x000287b3}, {0x13, 0x000244b7},
672 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
673 {0x13, 0x00018493}, {0x13, 0x0001429b},
674 {0x13, 0x00010299}, {0x13, 0x0000c29c},
675 {0x13, 0x000081a0}, {0x13, 0x000040ac},
676 {0x13, 0x00000020}, {0x14, 0x0001944c},
677 {0x14, 0x00059444}, {0x14, 0x0009944c},
678 {0x14, 0x000d9444}, {0x15, 0x0000f474},
679 {0x15, 0x0004f477}, {0x15, 0x0008f455},
680 {0x15, 0x000cf455}, {0x16, 0x00000339},
681 {0x16, 0x00040339}, {0x16, 0x00080339},
682 {0x16, 0x000c0366}, {0x00, 0x00010159},
683 {0x18, 0x0000f401}, {0xfe, 0x00000000},
684 {0xfe, 0x00000000}, {0x1f, 0x00000003},
685 {0xfe, 0x00000000}, {0xfe, 0x00000000},
686 {0x1e, 0x00000247}, {0x1f, 0x00000000},
687 {0x00, 0x00030159},
688 {0xff, 0xffffffff}
689};
690
691static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
692 {0x00, 0x00030159}, {0x01, 0x00031284},
693 {0x02, 0x00098000}, {0x03, 0x00018c63},
694 {0x04, 0x000210e7}, {0x09, 0x0002044f},
695 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
696 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
697 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
698 {0x19, 0x00000000}, {0x1a, 0x00010255},
699 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
700 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
701 {0x1f, 0x00080001}, {0x20, 0x0000b614},
702 {0x21, 0x0006c000}, {0x22, 0x00000000},
703 {0x23, 0x00001558}, {0x24, 0x00000060},
704 {0x25, 0x00000483}, {0x26, 0x0004f000},
705 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
706 {0x29, 0x00004783}, {0x2a, 0x00000001},
707 {0x2b, 0x00021334}, {0x2a, 0x00000000},
708 {0x2b, 0x00000054}, {0x2a, 0x00000001},
709 {0x2b, 0x00000808}, {0x2b, 0x00053333},
710 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
711 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
712 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
713 {0x2b, 0x00000808}, {0x2b, 0x00063333},
714 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
715 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
716 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
717 {0x2b, 0x00000808}, {0x2b, 0x00073333},
718 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
719 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
720 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
721 {0x2b, 0x00000709}, {0x2b, 0x00063333},
722 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
723 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
724 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
725 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
726 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
727 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
728 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
729 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
730 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
731 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
732 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
733 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
734 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
735 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
736 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
737 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
738 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
739 {0x10, 0x0002000f}, {0x11, 0x000203f9},
740 {0x10, 0x0003000f}, {0x11, 0x000ff500},
741 {0x10, 0x00000000}, {0x11, 0x00000000},
742 {0x10, 0x0008000f}, {0x11, 0x0003f100},
743 {0x10, 0x0009000f}, {0x11, 0x00023100},
744 {0x12, 0x00032000}, {0x12, 0x00071000},
745 {0x12, 0x000b0000}, {0x12, 0x000fc000},
746 {0x13, 0x000287b3}, {0x13, 0x000244b7},
747 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
748 {0x13, 0x00018493}, {0x13, 0x0001429b},
749 {0x13, 0x00010299}, {0x13, 0x0000c29c},
750 {0x13, 0x000081a0}, {0x13, 0x000040ac},
751 {0x13, 0x00000020}, {0x14, 0x0001944c},
752 {0x14, 0x00059444}, {0x14, 0x0009944c},
753 {0x14, 0x000d9444}, {0x15, 0x0000f424},
754 {0x15, 0x0004f424}, {0x15, 0x0008f424},
755 {0x15, 0x000cf424}, {0x16, 0x000e0330},
756 {0x16, 0x000a0330}, {0x16, 0x00060330},
757 {0x16, 0x00020330}, {0x00, 0x00010159},
758 {0x18, 0x0000f401}, {0xfe, 0x00000000},
759 {0xfe, 0x00000000}, {0x1f, 0x00080003},
760 {0xfe, 0x00000000}, {0xfe, 0x00000000},
761 {0x1e, 0x00044457}, {0x1f, 0x00080000},
762 {0x00, 0x00030159},
763 {0xff, 0xffffffff}
764};
765
766static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
767 {0x00, 0x00030159}, {0x01, 0x00031284},
768 {0x02, 0x00098000}, {0x03, 0x00018c63},
769 {0x04, 0x000210e7}, {0x09, 0x0002044f},
770 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
771 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
772 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
773 {0x12, 0x00032000}, {0x12, 0x00071000},
774 {0x12, 0x000b0000}, {0x12, 0x000fc000},
775 {0x13, 0x000287af}, {0x13, 0x000244b7},
776 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
777 {0x13, 0x00018493}, {0x13, 0x00014297},
778 {0x13, 0x00010295}, {0x13, 0x0000c298},
779 {0x13, 0x0000819c}, {0x13, 0x000040a8},
780 {0x13, 0x0000001c}, {0x14, 0x0001944c},
781 {0x14, 0x00059444}, {0x14, 0x0009944c},
782 {0x14, 0x000d9444}, {0x15, 0x0000f424},
783 {0x15, 0x0004f424}, {0x15, 0x0008f424},
784 {0x15, 0x000cf424}, {0x16, 0x000e0330},
785 {0x16, 0x000a0330}, {0x16, 0x00060330},
786 {0x16, 0x00020330},
787 {0xff, 0xffffffff}
788};
789
790static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
791 {0x00, 0x00030159}, {0x01, 0x00031284},
792 {0x02, 0x00098000}, {0x03, 0x00018c63},
793 {0x04, 0x000210e7}, {0x09, 0x0002044f},
794 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
795 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
796 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
797 {0x19, 0x00000000}, {0x1a, 0x00010255},
798 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
799 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
800 {0x1f, 0x00080001}, {0x20, 0x0000b614},
801 {0x21, 0x0006c000}, {0x22, 0x00000000},
802 {0x23, 0x00001558}, {0x24, 0x00000060},
803 {0x25, 0x00000483}, {0x26, 0x0004f000},
804 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
805 {0x29, 0x00004783}, {0x2a, 0x00000001},
806 {0x2b, 0x00021334}, {0x2a, 0x00000000},
807 {0x2b, 0x00000054}, {0x2a, 0x00000001},
808 {0x2b, 0x00000808}, {0x2b, 0x00053333},
809 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
810 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
811 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
812 {0x2b, 0x00000808}, {0x2b, 0x00063333},
813 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
814 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
815 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
816 {0x2b, 0x00000808}, {0x2b, 0x00073333},
817 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
818 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
819 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
820 {0x2b, 0x00000709}, {0x2b, 0x00063333},
821 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
822 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
823 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
824 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
825 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
826 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
827 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
828 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
829 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
830 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
831 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
832 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
833 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
834 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
835 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
836 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
837 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
838 {0x10, 0x0002000f}, {0x11, 0x000203f9},
839 {0x10, 0x0003000f}, {0x11, 0x000ff500},
840 {0x10, 0x00000000}, {0x11, 0x00000000},
841 {0x10, 0x0008000f}, {0x11, 0x0003f100},
842 {0x10, 0x0009000f}, {0x11, 0x00023100},
843 {0x12, 0x00032000}, {0x12, 0x00071000},
844 {0x12, 0x000b0000}, {0x12, 0x000fc000},
845 {0x13, 0x000287b3}, {0x13, 0x000244b7},
846 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
847 {0x13, 0x00018493}, {0x13, 0x0001429b},
848 {0x13, 0x00010299}, {0x13, 0x0000c29c},
849 {0x13, 0x000081a0}, {0x13, 0x000040ac},
850 {0x13, 0x00000020}, {0x14, 0x0001944c},
851 {0x14, 0x00059444}, {0x14, 0x0009944c},
852 {0x14, 0x000d9444}, {0x15, 0x0000f405},
853 {0x15, 0x0004f405}, {0x15, 0x0008f405},
854 {0x15, 0x000cf405}, {0x16, 0x000e0330},
855 {0x16, 0x000a0330}, {0x16, 0x00060330},
856 {0x16, 0x00020330}, {0x00, 0x00010159},
857 {0x18, 0x0000f401}, {0xfe, 0x00000000},
858 {0xfe, 0x00000000}, {0x1f, 0x00080003},
859 {0xfe, 0x00000000}, {0xfe, 0x00000000},
860 {0x1e, 0x00044457}, {0x1f, 0x00080000},
861 {0x00, 0x00030159},
862 {0xff, 0xffffffff}
863};
864
865static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
866 {0x00, 0x00030159}, {0x01, 0x00031284},
867 {0x02, 0x00098000}, {0x03, 0x00018c63},
868 {0x04, 0x000210e7}, {0x09, 0x0002044f},
869 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
870 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
871 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
872 {0x19, 0x00000000}, {0x1a, 0x00000255},
873 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
874 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
875 {0x1f, 0x00080001}, {0x20, 0x0000b614},
876 {0x21, 0x0006c000}, {0x22, 0x0000083c},
877 {0x23, 0x00001558}, {0x24, 0x00000060},
878 {0x25, 0x00000483}, {0x26, 0x0004f000},
879 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
880 {0x29, 0x00004783}, {0x2a, 0x00000001},
881 {0x2b, 0x00021334}, {0x2a, 0x00000000},
882 {0x2b, 0x00000054}, {0x2a, 0x00000001},
883 {0x2b, 0x00000808}, {0x2b, 0x00053333},
884 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
885 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
886 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
887 {0x2b, 0x00000808}, {0x2b, 0x00063333},
888 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
889 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
890 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
891 {0x2b, 0x00000808}, {0x2b, 0x00073333},
892 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
893 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
894 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
895 {0x2b, 0x00000709}, {0x2b, 0x00063333},
896 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
897 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
898 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
899 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
900 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
901 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
902 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
903 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
904 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
905 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
906 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
907 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
908 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
909 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
910 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
911 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
912 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
913 {0x10, 0x0002000f}, {0x11, 0x000203f9},
914 {0x10, 0x0003000f}, {0x11, 0x000ff500},
915 {0x10, 0x00000000}, {0x11, 0x00000000},
916 {0x10, 0x0008000f}, {0x11, 0x0003f100},
917 {0x10, 0x0009000f}, {0x11, 0x00023100},
918 {0x12, 0x000d8000}, {0x12, 0x00090000},
919 {0x12, 0x00051000}, {0x12, 0x00012000},
920 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
921 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
922 {0x13, 0x000183a4}, {0x13, 0x00014398},
923 {0x13, 0x000101a4}, {0x13, 0x0000c198},
924 {0x13, 0x000080a4}, {0x13, 0x00004098},
925 {0x13, 0x00000000}, {0x14, 0x0001944c},
926 {0x14, 0x00059444}, {0x14, 0x0009944c},
927 {0x14, 0x000d9444}, {0x15, 0x0000f405},
928 {0x15, 0x0004f405}, {0x15, 0x0008f405},
929 {0x15, 0x000cf405}, {0x16, 0x000e0330},
930 {0x16, 0x000a0330}, {0x16, 0x00060330},
931 {0x16, 0x00020330}, {0x00, 0x00010159},
932 {0x18, 0x0000f401}, {0xfe, 0x00000000},
933 {0xfe, 0x00000000}, {0x1f, 0x00080003},
934 {0xfe, 0x00000000}, {0xfe, 0x00000000},
935 {0x1e, 0x00044457}, {0x1f, 0x00080000},
936 {0x00, 0x00030159},
937 {0xff, 0xffffffff}
938};
939
940static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
941 { /* RF_A */
942 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
943 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
944 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
945 .hspiread = REG_HSPI_XA_READBACK,
946 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
947 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
948 },
949 { /* RF_B */
950 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
951 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
952 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
953 .hspiread = REG_HSPI_XB_READBACK,
954 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
955 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
956 },
957};
958
959static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
960 REG_OFDM0_XA_RX_IQ_IMBALANCE,
961 REG_OFDM0_XB_RX_IQ_IMBALANCE,
962 REG_OFDM0_ENERGY_CCA_THRES,
963 REG_OFDM0_AGCR_SSI_TABLE,
964 REG_OFDM0_XA_TX_IQ_IMBALANCE,
965 REG_OFDM0_XB_TX_IQ_IMBALANCE,
966 REG_OFDM0_XC_TX_AFE,
967 REG_OFDM0_XD_TX_AFE,
968 REG_OFDM0_RX_IQ_EXT_ANTA
969};
970
971static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
972{
973 struct usb_device *udev = priv->udev;
974 int len;
975 u8 data;
976
977 mutex_lock(&priv->usb_buf_mutex);
978 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
979 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
980 addr, 0, &priv->usb_buf.val8, sizeof(u8),
981 RTW_USB_CONTROL_MSG_TIMEOUT);
982 data = priv->usb_buf.val8;
983 mutex_unlock(&priv->usb_buf_mutex);
984
985 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
986 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
987 __func__, addr, data, len);
988 return data;
989}
990
991static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
992{
993 struct usb_device *udev = priv->udev;
994 int len;
995 u16 data;
996
997 mutex_lock(&priv->usb_buf_mutex);
998 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
999 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1000 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1001 RTW_USB_CONTROL_MSG_TIMEOUT);
1002 data = le16_to_cpu(priv->usb_buf.val16);
1003 mutex_unlock(&priv->usb_buf_mutex);
1004
1005 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1006 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1007 __func__, addr, data, len);
1008 return data;
1009}
1010
1011static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1012{
1013 struct usb_device *udev = priv->udev;
1014 int len;
1015 u32 data;
1016
1017 mutex_lock(&priv->usb_buf_mutex);
1018 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1019 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1020 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1021 RTW_USB_CONTROL_MSG_TIMEOUT);
1022 data = le32_to_cpu(priv->usb_buf.val32);
1023 mutex_unlock(&priv->usb_buf_mutex);
1024
1025 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1026 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1027 __func__, addr, data, len);
1028 return data;
1029}
1030
1031static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1032{
1033 struct usb_device *udev = priv->udev;
1034 int ret;
1035
1036 mutex_lock(&priv->usb_buf_mutex);
1037 priv->usb_buf.val8 = val;
1038 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1039 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1040 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1041 RTW_USB_CONTROL_MSG_TIMEOUT);
1042
1043 mutex_unlock(&priv->usb_buf_mutex);
1044
1045 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1046 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1047 __func__, addr, val);
1048 return ret;
1049}
1050
1051static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1052{
1053 struct usb_device *udev = priv->udev;
1054 int ret;
1055
1056 mutex_lock(&priv->usb_buf_mutex);
1057 priv->usb_buf.val16 = cpu_to_le16(val);
1058 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1059 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1060 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1061 RTW_USB_CONTROL_MSG_TIMEOUT);
1062 mutex_unlock(&priv->usb_buf_mutex);
1063
1064 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1065 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1066 __func__, addr, val);
1067 return ret;
1068}
1069
1070static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1071{
1072 struct usb_device *udev = priv->udev;
1073 int ret;
1074
1075 mutex_lock(&priv->usb_buf_mutex);
1076 priv->usb_buf.val32 = cpu_to_le32(val);
1077 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1078 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1079 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1080 RTW_USB_CONTROL_MSG_TIMEOUT);
1081 mutex_unlock(&priv->usb_buf_mutex);
1082
1083 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1084 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1085 __func__, addr, val);
1086 return ret;
1087}
1088
1089static int
1090rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1091{
1092 struct usb_device *udev = priv->udev;
1093 int blocksize = priv->fops->writeN_block_size;
1094 int ret, i, count, remainder;
1095
1096 count = len / blocksize;
1097 remainder = len % blocksize;
1098
1099 for (i = 0; i < count; i++) {
1100 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1101 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1102 addr, 0, buf, blocksize,
1103 RTW_USB_CONTROL_MSG_TIMEOUT);
1104 if (ret != blocksize)
1105 goto write_error;
1106
1107 addr += blocksize;
1108 buf += blocksize;
1109 }
1110
1111 if (remainder) {
1112 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1113 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1114 addr, 0, buf, remainder,
1115 RTW_USB_CONTROL_MSG_TIMEOUT);
1116 if (ret != remainder)
1117 goto write_error;
1118 }
1119
1120 return len;
1121
1122write_error:
1123 dev_info(&udev->dev,
1124 "%s: Failed to write block at addr: %04x size: %04x\n",
1125 __func__, addr, blocksize);
1126 return -EAGAIN;
1127}
1128
1129static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1130 enum rtl8xxxu_rfpath path, u8 reg)
1131{
1132 u32 hssia, val32, retval;
1133
1134 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1135 if (path != RF_A)
1136 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1137 else
1138 val32 = hssia;
1139
1140 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1141 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1142 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1143 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1144 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1145
1146 udelay(10);
1147
1148 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1149 udelay(100);
1150
1151 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1152 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1153 udelay(10);
1154
1155 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1156 if (val32 & FPGA0_HSSI_PARM1_PI)
1157 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1158 else
1159 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1160
1161 retval &= 0xfffff;
1162
1163 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1164 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1165 __func__, reg, retval);
1166 return retval;
1167}
1168
1169static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1170 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1171{
1172 int ret, retval;
1173 u32 dataaddr;
1174
1175 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1176 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1177 __func__, reg, data);
1178
1179 data &= FPGA0_LSSI_PARM_DATA_MASK;
1180 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1181
1182 /* Use XB for path B */
1183 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1184 if (ret != sizeof(dataaddr))
1185 retval = -EIO;
1186 else
1187 retval = 0;
1188
1189 udelay(1);
1190
1191 return retval;
1192}
1193
1194static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1195{
1196 struct device *dev = &priv->udev->dev;
1197 int mbox_nr, retry, retval = 0;
1198 int mbox_reg, mbox_ext_reg;
1199 u8 val8;
1200
1201 mutex_lock(&priv->h2c_mutex);
1202
1203 mbox_nr = priv->next_mbox;
1204 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1205 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1206
1207 /*
1208 * MBOX ready?
1209 */
1210 retry = 100;
1211 do {
1212 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1213 if (!(val8 & BIT(mbox_nr)))
1214 break;
1215 } while (retry--);
1216
1217 if (!retry) {
1218 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1219 retval = -EBUSY;
1220 goto error;
1221 }
1222
1223 /*
1224 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1225 */
1226 if (h2c->cmd.cmd & H2C_EXT) {
1227 rtl8xxxu_write16(priv, mbox_ext_reg,
1228 le16_to_cpu(h2c->raw.ext));
1229 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230 dev_info(dev, "H2C_EXT %04x\n",
1231 le16_to_cpu(h2c->raw.ext));
1232 }
1233 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1234 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1235 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1236
1237 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1238
1239error:
1240 mutex_unlock(&priv->h2c_mutex);
1241 return retval;
1242}
1243
1244static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1245{
1246 u8 val8;
1247 u32 val32;
1248
1249 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1250 val8 |= BIT(0) | BIT(3);
1251 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1252
1253 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1254 val32 &= ~(BIT(4) | BIT(5));
1255 val32 |= BIT(3);
1256 if (priv->rf_paths == 2) {
1257 val32 &= ~(BIT(20) | BIT(21));
1258 val32 |= BIT(19);
1259 }
1260 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1261
1262 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1263 val32 &= ~OFDM_RF_PATH_TX_MASK;
1264 if (priv->tx_paths == 2)
1265 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1266 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1267 val32 |= OFDM_RF_PATH_TX_B;
1268 else
1269 val32 |= OFDM_RF_PATH_TX_A;
1270 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1271
1272 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1273 val32 &= ~FPGA_RF_MODE_JAPAN;
1274 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1275
1276 if (priv->rf_paths == 2)
1277 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1278 else
1279 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1280
1281 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1282 if (priv->rf_paths == 2)
1283 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1284
1285 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1286}
1287
1288static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1289{
1290 u8 sps0;
1291 u32 val32;
1292
1293 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1294
1295 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1296
1297 /* RF RX code for preamble power saving */
1298 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1299 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1300 if (priv->rf_paths == 2)
1301 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1302 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1303
1304 /* Disable TX for four paths */
1305 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1306 val32 &= ~OFDM_RF_PATH_TX_MASK;
1307 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1308
1309 /* Enable power saving */
1310 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1311 val32 |= FPGA_RF_MODE_JAPAN;
1312 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1313
1314 /* AFE control register to power down bits [30:22] */
1315 if (priv->rf_paths == 2)
1316 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1317 else
1318 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1319
1320 /* Power down RF module */
1321 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1322 if (priv->rf_paths == 2)
1323 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1324
1325 sps0 &= ~(BIT(0) | BIT(3));
1326 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1327}
1328
1329
1330static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1331{
1332 u8 val8;
1333
1334 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1335 val8 &= ~BIT(6);
1336 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1337
1338 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1339 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1340 val8 &= ~BIT(0);
1341 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1342}
1343
1344
1345/*
1346 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1347 * supports the 2.4GHz band, so channels 1 - 14:
1348 * group 0: channels 1 - 3
1349 * group 1: channels 4 - 9
1350 * group 2: channels 10 - 14
1351 *
1352 * Note: We index from 0 in the code
1353 */
1354static int rtl8723a_channel_to_group(int channel)
1355{
1356 int group;
1357
1358 if (channel < 4)
1359 group = 0;
1360 else if (channel < 10)
1361 group = 1;
1362 else
1363 group = 2;
1364
1365 return group;
1366}
1367
1368static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1369{
1370 struct rtl8xxxu_priv *priv = hw->priv;
1371 u32 val32, rsr;
1372 u8 val8, opmode;
1373 bool ht = true;
1374 int sec_ch_above, channel;
1375 int i;
1376
1377 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1378 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1379 channel = hw->conf.chandef.chan->hw_value;
1380
1381 switch (hw->conf.chandef.width) {
1382 case NL80211_CHAN_WIDTH_20_NOHT:
1383 ht = false;
1384 case NL80211_CHAN_WIDTH_20:
1385 opmode |= BW_OPMODE_20MHZ;
1386 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1387
1388 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1389 val32 &= ~FPGA_RF_MODE;
1390 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1391
1392 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1393 val32 &= ~FPGA_RF_MODE;
1394 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1395
1396 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1397 val32 |= FPGA0_ANALOG2_20MHZ;
1398 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1399 break;
1400 case NL80211_CHAN_WIDTH_40:
1401 if (hw->conf.chandef.center_freq1 >
1402 hw->conf.chandef.chan->center_freq) {
1403 sec_ch_above = 1;
1404 channel += 2;
1405 } else {
1406 sec_ch_above = 0;
1407 channel -= 2;
1408 }
1409
1410 opmode &= ~BW_OPMODE_20MHZ;
1411 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1412 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1413 if (sec_ch_above)
1414 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1415 else
1416 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1417 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1418
1419 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1420 val32 |= FPGA_RF_MODE;
1421 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1422
1423 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1424 val32 |= FPGA_RF_MODE;
1425 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1426
1427 /*
1428 * Set Control channel to upper or lower. These settings
1429 * are required only for 40MHz
1430 */
1431 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1432 val32 &= ~CCK0_SIDEBAND;
1433 if (!sec_ch_above)
1434 val32 |= CCK0_SIDEBAND;
1435 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1436
1437 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1438 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1439 if (sec_ch_above)
1440 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1441 else
1442 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1443 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1444
1445 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1446 val32 &= ~FPGA0_ANALOG2_20MHZ;
1447 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1448
1449 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1450 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1451 if (sec_ch_above)
1452 val32 |= FPGA0_PS_UPPER_CHANNEL;
1453 else
1454 val32 |= FPGA0_PS_LOWER_CHANNEL;
1455 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1456 break;
1457
1458 default:
1459 break;
1460 }
1461
1462 for (i = RF_A; i < priv->rf_paths; i++) {
1463 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1464 val32 &= ~MODE_AG_CHANNEL_MASK;
1465 val32 |= channel;
1466 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1467 }
1468
1469 if (ht)
1470 val8 = 0x0e;
1471 else
1472 val8 = 0x0a;
1473
1474 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1475 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1476
1477 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1478 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1479
1480 for (i = RF_A; i < priv->rf_paths; i++) {
1481 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1482 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1483 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1484 else
1485 val32 |= MODE_AG_CHANNEL_20MHZ;
1486 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1487 }
1488}
1489
1490static void
1491rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1492{
1493 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1494 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1495 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1496 u8 val8;
1497 int group, i;
1498
1499 group = rtl8723a_channel_to_group(channel);
1500
1501 cck[0] = priv->cck_tx_power_index_A[group];
1502 cck[1] = priv->cck_tx_power_index_B[group];
1503
1504 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1505 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1506
1507 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1508 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1509
1510 mcsbase[0] = ofdm[0];
1511 mcsbase[1] = ofdm[1];
1512 if (!ht40) {
1513 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1514 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1515 }
1516
1517 if (priv->tx_paths > 1) {
1518 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1519 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1520 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1521 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1522 }
1523
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1525 dev_info(&priv->udev->dev,
1526 "%s: Setting TX power CCK A: %02x, "
1527 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1528 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1529
1530 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1531 if (cck[i] > RF6052_MAX_TX_PWR)
1532 cck[i] = RF6052_MAX_TX_PWR;
1533 if (ofdm[i] > RF6052_MAX_TX_PWR)
1534 ofdm[i] = RF6052_MAX_TX_PWR;
1535 }
1536
1537 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1538 val32 &= 0xffff00ff;
1539 val32 |= (cck[0] << 8);
1540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1541
1542 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543 val32 &= 0xff;
1544 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1548 val32 &= 0xffffff00;
1549 val32 |= cck[1];
1550 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1551
1552 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1553 val32 &= 0xff;
1554 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1555 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1556
1557 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1558 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1559 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1560 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1561 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1562 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1563
1564 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1565 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1566
1567 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1568 mcsbase[0] << 16 | mcsbase[0] << 24;
1569 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1570 mcsbase[1] << 16 | mcsbase[1] << 24;
1571
1572 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1573 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1574
1575 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1576 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1577
1578 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1580
1581 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1582 for (i = 0; i < 3; i++) {
1583 if (i != 2)
1584 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1585 else
1586 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1587 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1588 }
1589 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1590 for (i = 0; i < 3; i++) {
1591 if (i != 2)
1592 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1593 else
1594 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1595 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1596 }
1597}
1598
1599static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1600 enum nl80211_iftype linktype)
1601{
1602 u16 val8;
1603
1604 val8 = rtl8xxxu_read16(priv, REG_MSR);
1605 val8 &= ~MSR_LINKTYPE_MASK;
1606
1607 switch (linktype) {
1608 case NL80211_IFTYPE_UNSPECIFIED:
1609 val8 |= MSR_LINKTYPE_NONE;
1610 break;
1611 case NL80211_IFTYPE_ADHOC:
1612 val8 |= MSR_LINKTYPE_ADHOC;
1613 break;
1614 case NL80211_IFTYPE_STATION:
1615 val8 |= MSR_LINKTYPE_STATION;
1616 break;
1617 case NL80211_IFTYPE_AP:
1618 val8 |= MSR_LINKTYPE_AP;
1619 break;
1620 default:
1621 goto out;
1622 }
1623
1624 rtl8xxxu_write8(priv, REG_MSR, val8);
1625out:
1626 return;
1627}
1628
1629static void
1630rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1631{
1632 u16 val16;
1633
1634 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1635 RETRY_LIMIT_SHORT_MASK) |
1636 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1637 RETRY_LIMIT_LONG_MASK);
1638
1639 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1640}
1641
1642static void
1643rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1644{
1645 u16 val16;
1646
1647 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1648 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1649
1650 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1651}
1652
1653static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1654{
1655 struct device *dev = &priv->udev->dev;
1656 char *cut;
1657
1658 switch (priv->chip_cut) {
1659 case 0:
1660 cut = "A";
1661 break;
1662 case 1:
1663 cut = "B";
1664 break;
1665 default:
1666 cut = "unknown";
1667 }
1668
1669 dev_info(dev,
1670 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1671 priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1672 priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1673 priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1674 priv->hi_pa);
1675
1676 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1677}
1678
1679static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1680{
1681 struct device *dev = &priv->udev->dev;
1682 u32 val32, bonding;
1683 u16 val16;
1684
1685 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1686 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1687 SYS_CFG_CHIP_VERSION_SHIFT;
1688 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1689 dev_info(dev, "Unsupported test chip\n");
1690 return -ENOTSUPP;
1691 }
1692
1693 if (val32 & SYS_CFG_BT_FUNC) {
1694 sprintf(priv->chip_name, "8723AU");
1695 priv->rf_paths = 1;
1696 priv->rx_paths = 1;
1697 priv->tx_paths = 1;
1698 priv->rtlchip = 0x8723a;
1699
1700 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1701 if (val32 & MULTI_WIFI_FUNC_EN)
1702 priv->has_wifi = 1;
1703 if (val32 & MULTI_BT_FUNC_EN)
1704 priv->has_bluetooth = 1;
1705 if (val32 & MULTI_GPS_FUNC_EN)
1706 priv->has_gps = 1;
1707 } else if (val32 & SYS_CFG_TYPE_ID) {
1708 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1709 bonding &= HPON_FSM_BONDING_MASK;
1710 if (bonding == HPON_FSM_BONDING_1T2R) {
1711 sprintf(priv->chip_name, "8191CU");
1712 priv->rf_paths = 2;
1713 priv->rx_paths = 2;
1714 priv->tx_paths = 1;
1715 priv->rtlchip = 0x8191c;
1716 } else {
1717 sprintf(priv->chip_name, "8192CU");
1718 priv->rf_paths = 2;
1719 priv->rx_paths = 2;
1720 priv->tx_paths = 2;
1721 priv->rtlchip = 0x8192c;
1722 }
1723 priv->has_wifi = 1;
1724 } else {
1725 sprintf(priv->chip_name, "8188CU");
1726 priv->rf_paths = 1;
1727 priv->rx_paths = 1;
1728 priv->tx_paths = 1;
1729 priv->rtlchip = 0x8188c;
1730 priv->has_wifi = 1;
1731 }
1732
1733 if (val32 & SYS_CFG_VENDOR_ID)
1734 priv->vendor_umc = 1;
1735
1736 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1737 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1738
1739 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1740 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1741 priv->ep_tx_high_queue = 1;
1742 priv->ep_tx_count++;
1743 }
1744
1745 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1746 priv->ep_tx_normal_queue = 1;
1747 priv->ep_tx_count++;
1748 }
1749
1750 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1751 priv->ep_tx_low_queue = 1;
1752 priv->ep_tx_count++;
1753 }
1754
1755 /*
1756 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1757 */
1758 if (!priv->ep_tx_count) {
1759 switch (priv->nr_out_eps) {
1760 case 3:
1761 priv->ep_tx_low_queue = 1;
1762 priv->ep_tx_count++;
1763 case 2:
1764 priv->ep_tx_normal_queue = 1;
1765 priv->ep_tx_count++;
1766 case 1:
1767 priv->ep_tx_high_queue = 1;
1768 priv->ep_tx_count++;
1769 break;
1770 default:
1771 dev_info(dev, "Unsupported USB TX end-points\n");
1772 return -ENOTSUPP;
1773 }
1774 }
1775
1776 return 0;
1777}
1778
1779static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1780{
1781 if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1782 return -EINVAL;
1783
1784 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1785
1786 memcpy(priv->cck_tx_power_index_A,
1787 priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1788 sizeof(priv->cck_tx_power_index_A));
1789 memcpy(priv->cck_tx_power_index_B,
1790 priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1791 sizeof(priv->cck_tx_power_index_B));
1792
1793 memcpy(priv->ht40_1s_tx_power_index_A,
1794 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1795 sizeof(priv->ht40_1s_tx_power_index_A));
1796 memcpy(priv->ht40_1s_tx_power_index_B,
1797 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1798 sizeof(priv->ht40_1s_tx_power_index_B));
1799
1800 memcpy(priv->ht20_tx_power_index_diff,
1801 priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1802 sizeof(priv->ht20_tx_power_index_diff));
1803 memcpy(priv->ofdm_tx_power_index_diff,
1804 priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1805 sizeof(priv->ofdm_tx_power_index_diff));
1806
1807 memcpy(priv->ht40_max_power_offset,
1808 priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1809 sizeof(priv->ht40_max_power_offset));
1810 memcpy(priv->ht20_max_power_offset,
1811 priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1812 sizeof(priv->ht20_max_power_offset));
1813
1814 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1815 priv->efuse_wifi.efuse8723.vendor_name);
1816 dev_info(&priv->udev->dev, "Product: %.41s\n",
1817 priv->efuse_wifi.efuse8723.device_name);
1818 return 0;
1819}
1820
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1821#ifdef CONFIG_RTL8XXXU_UNTESTED
1822
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1823static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1824{
1825 int i;
1826
1827 if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1828 return -EINVAL;
1829
1830 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1831
1832 memcpy(priv->cck_tx_power_index_A,
1833 priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1834 sizeof(priv->cck_tx_power_index_A));
1835 memcpy(priv->cck_tx_power_index_B,
1836 priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1837 sizeof(priv->cck_tx_power_index_B));
1838
1839 memcpy(priv->ht40_1s_tx_power_index_A,
1840 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1841 sizeof(priv->ht40_1s_tx_power_index_A));
1842 memcpy(priv->ht40_1s_tx_power_index_B,
1843 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1844 sizeof(priv->ht40_1s_tx_power_index_B));
1845 memcpy(priv->ht40_2s_tx_power_index_diff,
1846 priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1847 sizeof(priv->ht40_2s_tx_power_index_diff));
1848
1849 memcpy(priv->ht20_tx_power_index_diff,
1850 priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1851 sizeof(priv->ht20_tx_power_index_diff));
1852 memcpy(priv->ofdm_tx_power_index_diff,
1853 priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1854 sizeof(priv->ofdm_tx_power_index_diff));
1855
1856 memcpy(priv->ht40_max_power_offset,
1857 priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1858 sizeof(priv->ht40_max_power_offset));
1859 memcpy(priv->ht20_max_power_offset,
1860 priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1861 sizeof(priv->ht20_max_power_offset));
1862
1863 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1864 priv->efuse_wifi.efuse8192.vendor_name);
1865 dev_info(&priv->udev->dev, "Product: %.20s\n",
1866 priv->efuse_wifi.efuse8192.device_name);
1867
1868 if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1869 sprintf(priv->chip_name, "8188RU");
1870 priv->hi_pa = 1;
1871 }
1872
1873 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1874 unsigned char *raw = priv->efuse_wifi.raw;
1875
1876 dev_info(&priv->udev->dev,
1877 "%s: dumping efuse (0x%02zx bytes):\n",
1878 __func__, sizeof(struct rtl8192cu_efuse));
1879 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1880 dev_info(&priv->udev->dev, "%02x: "
1881 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1882 raw[i], raw[i + 1], raw[i + 2],
1883 raw[i + 3], raw[i + 4], raw[i + 5],
1884 raw[i + 6], raw[i + 7]);
1885 }
1886 }
1887 return 0;
1888}
1889
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1890#endif
1891
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1892static int
1893rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1894{
1895 int i;
1896 u8 val8;
1897 u32 val32;
1898
1899 /* Write Address */
1900 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1901 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1902 val8 &= 0xfc;
1903 val8 |= (offset >> 8) & 0x03;
1904 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1905
1906 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1907 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1908
1909 /* Poll for data read */
1910 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1911 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1912 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1913 if (val32 & BIT(31))
1914 break;
1915 }
1916
1917 if (i == RTL8XXXU_MAX_REG_POLL)
1918 return -EIO;
1919
1920 udelay(50);
1921 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1922
1923 *data = val32 & 0xff;
1924 return 0;
1925}
1926
1927static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1928{
1929 struct device *dev = &priv->udev->dev;
1930 int i, ret = 0;
1931 u8 val8, word_mask, header, extheader;
1932 u16 val16, efuse_addr, offset;
1933 u32 val32;
1934
1935 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1936 if (val16 & EEPROM_ENABLE)
1937 priv->has_eeprom = 1;
1938 if (val16 & EEPROM_BOOT)
1939 priv->boot_eeprom = 1;
1940
1941 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1942 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1943 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1944
1945 dev_dbg(dev, "Booting from %s\n",
1946 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1947
1948 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1949
1950 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1951 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1952 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1953 val16 |= SYS_ISO_PWC_EV12V;
1954 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1955 }
1956 /* Reset: 0x0000[28], default valid */
1957 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1958 if (!(val16 & SYS_FUNC_ELDR)) {
1959 val16 |= SYS_FUNC_ELDR;
1960 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1961 }
1962
1963 /*
1964 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1965 */
1966 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1967 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1968 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1969 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1970 }
1971
1972 /* Default value is 0xff */
1973 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1974
1975 efuse_addr = 0;
1976 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1977 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1978 if (ret || header == 0xff)
1979 goto exit;
1980
1981 if ((header & 0x1f) == 0x0f) { /* extended header */
1982 offset = (header & 0xe0) >> 5;
1983
1984 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1985 &extheader);
1986 if (ret)
1987 goto exit;
1988 /* All words disabled */
1989 if ((extheader & 0x0f) == 0x0f)
1990 continue;
1991
1992 offset |= ((extheader & 0xf0) >> 1);
1993 word_mask = extheader & 0x0f;
1994 } else {
1995 offset = (header >> 4) & 0x0f;
1996 word_mask = header & 0x0f;
1997 }
1998
1999 if (offset < EFUSE_MAX_SECTION_8723A) {
2000 u16 map_addr;
2001 /* Get word enable value from PG header */
2002
2003 /* We have 8 bits to indicate validity */
2004 map_addr = offset * 8;
2005 if (map_addr >= EFUSE_MAP_LEN_8723A) {
2006 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2007 "efuse corrupt!\n",
2008 __func__, map_addr);
2009 ret = -EINVAL;
2010 goto exit;
2011 }
2012 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2013 /* Check word enable condition in the section */
2014 if (!(word_mask & BIT(i))) {
2015 ret = rtl8xxxu_read_efuse8(priv,
2016 efuse_addr++,
2017 &val8);
2018 if (ret)
2019 goto exit;
2020 priv->efuse_wifi.raw[map_addr++] = val8;
2021
2022 ret = rtl8xxxu_read_efuse8(priv,
2023 efuse_addr++,
2024 &val8);
2025 if (ret)
2026 goto exit;
2027 priv->efuse_wifi.raw[map_addr++] = val8;
2028 } else
2029 map_addr += 2;
2030 }
2031 } else {
2032 dev_warn(dev,
2033 "%s: Illegal offset (%04x), efuse corrupt!\n",
2034 __func__, offset);
2035 ret = -EINVAL;
2036 goto exit;
2037 }
2038 }
2039
2040exit:
2041 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2042
2043 return ret;
2044}
2045
2046static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2047{
2048 struct device *dev = &priv->udev->dev;
2049 int ret = 0, i;
2050 u32 val32;
2051
2052 /* Poll checksum report */
2053 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2054 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2055 if (val32 & MCU_FW_DL_CSUM_REPORT)
2056 break;
2057 }
2058
2059 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2060 dev_warn(dev, "Firmware checksum poll timed out\n");
2061 ret = -EAGAIN;
2062 goto exit;
2063 }
2064
2065 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2066 val32 |= MCU_FW_DL_READY;
2067 val32 &= ~MCU_WINT_INIT_READY;
2068 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2069
2070 /* Wait for firmware to become ready */
2071 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2072 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2073 if (val32 & MCU_WINT_INIT_READY)
2074 break;
2075
2076 udelay(100);
2077 }
2078
2079 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2080 dev_warn(dev, "Firmware failed to start\n");
2081 ret = -EAGAIN;
2082 goto exit;
2083 }
2084
2085exit:
2086 return ret;
2087}
2088
2089static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2090{
2091 int pages, remainder, i, ret;
2092 u8 val8;
2093 u16 val16;
2094 u32 val32;
2095 u8 *fwptr;
2096
2097 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2098 val8 |= 4;
2099 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2100
2101 /* 8051 enable */
2102 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
Jes Sorensen43154f62016-02-03 13:39:35 -0500[diff] [blame^]2103 val16 |= SYS_FUNC_CPU_ENABLE;
2104 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2105
2106 /* MCU firmware download enable */
2107 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2108 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_ENABLE);
2109
2110 /* 8051 reset */
2111 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2112 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32 & ~BIT(19));
2113
2114 /* Reset firmware download checksum */
2115 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2116 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_CSUM_REPORT);
2117
2118 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2119 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2120
2121 fwptr = priv->fw_data->data;
2122
2123 for (i = 0; i < pages; i++) {
2124 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2125 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i);
2126
2127 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2128 fwptr, RTL_FW_PAGE_SIZE);
2129 if (ret != RTL_FW_PAGE_SIZE) {
2130 ret = -EAGAIN;
2131 goto fw_abort;
2132 }
2133
2134 fwptr += RTL_FW_PAGE_SIZE;
2135 }
2136
2137 if (remainder) {
2138 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2139 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i);
2140 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2141 fwptr, remainder);
2142 if (ret != remainder) {
2143 ret = -EAGAIN;
2144 goto fw_abort;
2145 }
2146 }
2147
2148 ret = 0;
2149fw_abort:
2150 /* MCU firmware download disable */
2151 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2152 rtl8xxxu_write16(priv, REG_MCU_FW_DL,
2153 val16 & (~MCU_FW_DL_ENABLE & 0xff));
2154
2155 return ret;
2156}
2157
2158static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2159{
2160 struct device *dev = &priv->udev->dev;
2161 const struct firmware *fw;
2162 int ret = 0;
2163 u16 signature;
2164
2165 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2166 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2167 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2168 ret = -EAGAIN;
2169 goto exit;
2170 }
2171 if (!fw) {
2172 dev_warn(dev, "Firmware data not available\n");
2173 ret = -EINVAL;
2174 goto exit;
2175 }
2176
2177 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2178 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2179
2180 signature = le16_to_cpu(priv->fw_data->signature);
2181 switch (signature & 0xfff0) {
2182 case 0x92c0:
2183 case 0x88c0:
2184 case 0x2300:
2185 break;
2186 default:
2187 ret = -EINVAL;
2188 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2189 __func__, signature);
2190 }
2191
2192 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2193 le16_to_cpu(priv->fw_data->major_version),
2194 priv->fw_data->minor_version, signature);
2195
2196exit:
2197 release_firmware(fw);
2198 return ret;
2199}
2200
2201static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2202{
2203 char *fw_name;
2204 int ret;
2205
2206 switch (priv->chip_cut) {
2207 case 0:
2208 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2209 break;
2210 case 1:
2211 if (priv->enable_bluetooth)
2212 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2213 else
2214 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2215
2216 break;
2217 default:
2218 return -EINVAL;
2219 }
2220
2221 ret = rtl8xxxu_load_firmware(priv, fw_name);
2222 return ret;
2223}
2224
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2225#ifdef CONFIG_RTL8XXXU_UNTESTED
2226
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2227static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2228{
2229 char *fw_name;
2230 int ret;
2231
2232 if (!priv->vendor_umc)
2233 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2234 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2235 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2236 else
2237 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2238
2239 ret = rtl8xxxu_load_firmware(priv, fw_name);
2240
2241 return ret;
2242}
2243
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2244#endif
2245
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2246static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2247{
2248 u16 val16;
2249 int i = 100;
2250
2251 /* Inform 8051 to perform reset */
2252 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2253
2254 for (i = 100; i > 0; i--) {
2255 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2256
2257 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2258 dev_dbg(&priv->udev->dev,
2259 "%s: Firmware self reset success!\n", __func__);
2260 break;
2261 }
2262 udelay(50);
2263 }
2264
2265 if (!i) {
2266 /* Force firmware reset */
2267 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2268 val16 &= ~SYS_FUNC_CPU_ENABLE;
2269 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2270 }
2271}
2272
2273static int
2274rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2275{
2276 int i, ret;
2277 u16 reg;
2278 u8 val;
2279
2280 for (i = 0; ; i++) {
2281 reg = array[i].reg;
2282 val = array[i].val;
2283
2284 if (reg == 0xffff && val == 0xff)
2285 break;
2286
2287 ret = rtl8xxxu_write8(priv, reg, val);
2288 if (ret != 1) {
2289 dev_warn(&priv->udev->dev,
2290 "Failed to initialize MAC\n");
2291 return -EAGAIN;
2292 }
2293 }
2294
2295 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2296
2297 return 0;
2298}
2299
2300static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2301 struct rtl8xxxu_reg32val *array)
2302{
2303 int i, ret;
2304 u16 reg;
2305 u32 val;
2306
2307 for (i = 0; ; i++) {
2308 reg = array[i].reg;
2309 val = array[i].val;
2310
2311 if (reg == 0xffff && val == 0xffffffff)
2312 break;
2313
2314 ret = rtl8xxxu_write32(priv, reg, val);
2315 if (ret != sizeof(val)) {
2316 dev_warn(&priv->udev->dev,
2317 "Failed to initialize PHY\n");
2318 return -EAGAIN;
2319 }
2320 udelay(1);
2321 }
2322
2323 return 0;
2324}
2325
2326/*
2327 * Most of this is black magic retrieved from the old rtl8723au driver
2328 */
2329static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2330{
2331 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2332 u32 val32;
2333
2334 /*
2335 * Todo: The vendor driver maintains a table of PHY register
2336 * addresses, which is initialized here. Do we need this?
2337 */
2338
2339 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2340 udelay(2);
2341 val8 |= AFE_PLL_320_ENABLE;
2342 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2343 udelay(2);
2344
2345 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2346 udelay(2);
2347
2348 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2349 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2350 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2351
2352 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2353 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2354 val32 &= ~AFE_XTAL_RF_GATE;
2355 if (priv->has_bluetooth)
2356 val32 &= ~AFE_XTAL_BT_GATE;
2357 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2358
2359 /* 6. 0x1f[7:0] = 0x07 */
2360 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2361 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2362
2363 if (priv->hi_pa)
2364 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2365 else if (priv->tx_paths == 2)
2366 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2367 else
2368 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2369
2370
2371 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2372 priv->vendor_umc && priv->chip_cut == 1)
2373 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2374
2375 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2376 /*
2377 * For 1T2R boards, patch the registers.
2378 *
2379 * It looks like 8191/2 1T2R boards use path B for TX
2380 */
2381 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2382 val32 &= ~(BIT(0) | BIT(1));
2383 val32 |= BIT(1);
2384 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2385
2386 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2387 val32 &= ~0x300033;
2388 val32 |= 0x200022;
2389 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2390
2391 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2392 val32 &= 0xff000000;
2393 val32 |= 0x45000000;
2394 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2395
2396 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2397 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2398 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2399 OFDM_RF_PATH_TX_B);
2400 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2401
2402 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2403 val32 &= ~(BIT(4) | BIT(5));
2404 val32 |= BIT(4);
2405 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2406
2407 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2408 val32 &= ~(BIT(27) | BIT(26));
2409 val32 |= BIT(27);
2410 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2411
2412 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2413 val32 &= ~(BIT(27) | BIT(26));
2414 val32 |= BIT(27);
2415 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2416
2417 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2418 val32 &= ~(BIT(27) | BIT(26));
2419 val32 |= BIT(27);
2420 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2421
2422 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2423 val32 &= ~(BIT(27) | BIT(26));
2424 val32 |= BIT(27);
2425 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2426
2427 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2428 val32 &= ~(BIT(27) | BIT(26));
2429 val32 |= BIT(27);
2430 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2431 }
2432
2433 if (priv->hi_pa)
2434 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2435 else
2436 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2437
2438 if (priv->rtlchip == 0x8723a &&
2439 priv->efuse_wifi.efuse8723.version >= 0x01) {
2440 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2441
2442 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2443 val32 &= 0xff000fff;
2444 val32 |= ((val8 | (val8 << 6)) << 12);
2445
2446 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2447 }
2448
2449 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2450 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2451 ldohci12 = 0x57;
2452 lpldo = 1;
2453 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2454
2455 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2456
2457 return 0;
2458}
2459
2460static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2461 struct rtl8xxxu_rfregval *array,
2462 enum rtl8xxxu_rfpath path)
2463{
2464 int i, ret;
2465 u8 reg;
2466 u32 val;
2467
2468 for (i = 0; ; i++) {
2469 reg = array[i].reg;
2470 val = array[i].val;
2471
2472 if (reg == 0xff && val == 0xffffffff)
2473 break;
2474
2475 switch (reg) {
2476 case 0xfe:
2477 msleep(50);
2478 continue;
2479 case 0xfd:
2480 mdelay(5);
2481 continue;
2482 case 0xfc:
2483 mdelay(1);
2484 continue;
2485 case 0xfb:
2486 udelay(50);
2487 continue;
2488 case 0xfa:
2489 udelay(5);
2490 continue;
2491 case 0xf9:
2492 udelay(1);
2493 continue;
2494 }
2495
2496 reg &= 0x3f;
2497
2498 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2499 if (ret) {
2500 dev_warn(&priv->udev->dev,
2501 "Failed to initialize RF\n");
2502 return -EAGAIN;
2503 }
2504 udelay(1);
2505 }
2506
2507 return 0;
2508}
2509
2510static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2511 struct rtl8xxxu_rfregval *table,
2512 enum rtl8xxxu_rfpath path)
2513{
2514 u32 val32;
2515 u16 val16, rfsi_rfenv;
2516 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2517
2518 switch (path) {
2519 case RF_A:
2520 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2521 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2522 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2523 break;
2524 case RF_B:
2525 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2526 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2527 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2528 break;
2529 default:
2530 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2531 __func__, path + 'A');
2532 return -EINVAL;
2533 }
2534 /* For path B, use XB */
2535 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2536 rfsi_rfenv &= FPGA0_RF_RFENV;
2537
2538 /*
2539 * These two we might be able to optimize into one
2540 */
2541 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2542 val32 |= BIT(20); /* 0x10 << 16 */
2543 rtl8xxxu_write32(priv, reg_int_oe, val32);
2544 udelay(1);
2545
2546 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2547 val32 |= BIT(4);
2548 rtl8xxxu_write32(priv, reg_int_oe, val32);
2549 udelay(1);
2550
2551 /*
2552 * These two we might be able to optimize into one
2553 */
2554 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2555 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2556 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2557 udelay(1);
2558
2559 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2560 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2561 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2562 udelay(1);
2563
2564 rtl8xxxu_init_rf_regs(priv, table, path);
2565
2566 /* For path B, use XB */
2567 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2568 val16 &= ~FPGA0_RF_RFENV;
2569 val16 |= rfsi_rfenv;
2570 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2571
2572 return 0;
2573}
2574
2575static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2576{
2577 int ret = -EBUSY;
2578 int count = 0;
2579 u32 value;
2580
2581 value = LLT_OP_WRITE | address << 8 | data;
2582
2583 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2584
2585 do {
2586 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2587 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2588 ret = 0;
2589 break;
2590 }
2591 } while (count++ < 20);
2592
2593 return ret;
2594}
2595
2596static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2597{
2598 int ret;
2599 int i;
2600
2601 for (i = 0; i < last_tx_page; i++) {
2602 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2603 if (ret)
2604 goto exit;
2605 }
2606
2607 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2608 if (ret)
2609 goto exit;
2610
2611 /* Mark remaining pages as a ring buffer */
2612 for (i = last_tx_page + 1; i < 0xff; i++) {
2613 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2614 if (ret)
2615 goto exit;
2616 }
2617
2618 /* Let last entry point to the start entry of ring buffer */
2619 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2620 if (ret)
2621 goto exit;
2622
2623exit:
2624 return ret;
2625}
2626
2627static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2628{
2629 u16 val16, hi, lo;
2630 u16 hiq, mgq, bkq, beq, viq, voq;
2631 int hip, mgp, bkp, bep, vip, vop;
2632 int ret = 0;
2633
2634 switch (priv->ep_tx_count) {
2635 case 1:
2636 if (priv->ep_tx_high_queue) {
2637 hi = TRXDMA_QUEUE_HIGH;
2638 } else if (priv->ep_tx_low_queue) {
2639 hi = TRXDMA_QUEUE_LOW;
2640 } else if (priv->ep_tx_normal_queue) {
2641 hi = TRXDMA_QUEUE_NORMAL;
2642 } else {
2643 hi = 0;
2644 ret = -EINVAL;
2645 }
2646
2647 hiq = hi;
2648 mgq = hi;
2649 bkq = hi;
2650 beq = hi;
2651 viq = hi;
2652 voq = hi;
2653
2654 hip = 0;
2655 mgp = 0;
2656 bkp = 0;
2657 bep = 0;
2658 vip = 0;
2659 vop = 0;
2660 break;
2661 case 2:
2662 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2663 hi = TRXDMA_QUEUE_HIGH;
2664 lo = TRXDMA_QUEUE_LOW;
2665 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2666 hi = TRXDMA_QUEUE_NORMAL;
2667 lo = TRXDMA_QUEUE_LOW;
2668 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2669 hi = TRXDMA_QUEUE_HIGH;
2670 lo = TRXDMA_QUEUE_NORMAL;
2671 } else {
2672 ret = -EINVAL;
2673 hi = 0;
2674 lo = 0;
2675 }
2676
2677 hiq = hi;
2678 mgq = hi;
2679 bkq = lo;
2680 beq = lo;
2681 viq = hi;
2682 voq = hi;
2683
2684 hip = 0;
2685 mgp = 0;
2686 bkp = 1;
2687 bep = 1;
2688 vip = 0;
2689 vop = 0;
2690 break;
2691 case 3:
2692 beq = TRXDMA_QUEUE_LOW;
2693 bkq = TRXDMA_QUEUE_LOW;
2694 viq = TRXDMA_QUEUE_NORMAL;
2695 voq = TRXDMA_QUEUE_HIGH;
2696 mgq = TRXDMA_QUEUE_HIGH;
2697 hiq = TRXDMA_QUEUE_HIGH;
2698
2699 hip = hiq ^ 3;
2700 mgp = mgq ^ 3;
2701 bkp = bkq ^ 3;
2702 bep = beq ^ 3;
2703 vip = viq ^ 3;
2704 vop = viq ^ 3;
2705 break;
2706 default:
2707 ret = -EINVAL;
2708 }
2709
2710 /*
2711 * None of the vendor drivers are configuring the beacon
2712 * queue here .... why?
2713 */
2714 if (!ret) {
2715 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2716 val16 &= 0x7;
2717 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2718 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2719 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2720 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2721 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2722 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2723 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2724
2725 priv->pipe_out[TXDESC_QUEUE_VO] =
2726 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2727 priv->pipe_out[TXDESC_QUEUE_VI] =
2728 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2729 priv->pipe_out[TXDESC_QUEUE_BE] =
2730 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2731 priv->pipe_out[TXDESC_QUEUE_BK] =
2732 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2733 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2734 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2735 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2736 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2737 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2738 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2739 priv->pipe_out[TXDESC_QUEUE_CMD] =
2740 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2741 }
2742
2743 return ret;
2744}
2745
2746static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2747 bool iqk_ok, int result[][8],
2748 int candidate, bool tx_only)
2749{
2750 u32 oldval, x, tx0_a, reg;
2751 int y, tx0_c;
2752 u32 val32;
2753
2754 if (!iqk_ok)
2755 return;
2756
2757 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2758 oldval = val32 >> 22;
2759
2760 x = result[candidate][0];
2761 if ((x & 0x00000200) != 0)
2762 x = x | 0xfffffc00;
2763 tx0_a = (x * oldval) >> 8;
2764
2765 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2766 val32 &= ~0x3ff;
2767 val32 |= tx0_a;
2768 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2769
2770 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2771 val32 &= ~BIT(31);
2772 if ((x * oldval >> 7) & 0x1)
2773 val32 |= BIT(31);
2774 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2775
2776 y = result[candidate][1];
2777 if ((y & 0x00000200) != 0)
2778 y = y | 0xfffffc00;
2779 tx0_c = (y * oldval) >> 8;
2780
2781 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2782 val32 &= ~0xf0000000;
2783 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2784 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2785
2786 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2787 val32 &= ~0x003f0000;
2788 val32 |= ((tx0_c & 0x3f) << 16);
2789 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2790
2791 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2792 val32 &= ~BIT(29);
2793 if ((y * oldval >> 7) & 0x1)
2794 val32 |= BIT(29);
2795 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2796
2797 if (tx_only) {
2798 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2799 return;
2800 }
2801
2802 reg = result[candidate][2];
2803
2804 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2805 val32 &= ~0x3ff;
2806 val32 |= (reg & 0x3ff);
2807 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2808
2809 reg = result[candidate][3] & 0x3F;
2810
2811 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2812 val32 &= ~0xfc00;
2813 val32 |= ((reg << 10) & 0xfc00);
2814 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2815
2816 reg = (result[candidate][3] >> 6) & 0xF;
2817
2818 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2819 val32 &= ~0xf0000000;
2820 val32 |= (reg << 28);
2821 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2822}
2823
2824static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2825 bool iqk_ok, int result[][8],
2826 int candidate, bool tx_only)
2827{
2828 u32 oldval, x, tx1_a, reg;
2829 int y, tx1_c;
2830 u32 val32;
2831
2832 if (!iqk_ok)
2833 return;
2834
2835 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2836 oldval = val32 >> 22;
2837
2838 x = result[candidate][4];
2839 if ((x & 0x00000200) != 0)
2840 x = x | 0xfffffc00;
2841 tx1_a = (x * oldval) >> 8;
2842
2843 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2844 val32 &= ~0x3ff;
2845 val32 |= tx1_a;
2846 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2847
2848 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2849 val32 &= ~BIT(27);
2850 if ((x * oldval >> 7) & 0x1)
2851 val32 |= BIT(27);
2852 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2853
2854 y = result[candidate][5];
2855 if ((y & 0x00000200) != 0)
2856 y = y | 0xfffffc00;
2857 tx1_c = (y * oldval) >> 8;
2858
2859 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2860 val32 &= ~0xf0000000;
2861 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2862 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2863
2864 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2865 val32 &= ~0x003f0000;
2866 val32 |= ((tx1_c & 0x3f) << 16);
2867 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2868
2869 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2870 val32 &= ~BIT(25);
2871 if ((y * oldval >> 7) & 0x1)
2872 val32 |= BIT(25);
2873 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2874
2875 if (tx_only) {
2876 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2877 return;
2878 }
2879
2880 reg = result[candidate][6];
2881
2882 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2883 val32 &= ~0x3ff;
2884 val32 |= (reg & 0x3ff);
2885 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2886
2887 reg = result[candidate][7] & 0x3f;
2888
2889 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2890 val32 &= ~0xfc00;
2891 val32 |= ((reg << 10) & 0xfc00);
2892 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2893
2894 reg = (result[candidate][7] >> 6) & 0xf;
2895
2896 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2897 val32 &= ~0x0000f000;
2898 val32 |= (reg << 12);
2899 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2900}
2901
2902#define MAX_TOLERANCE 5
2903
2904static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2905 int result[][8], int c1, int c2)
2906{
2907 u32 i, j, diff, simubitmap, bound = 0;
2908 int candidate[2] = {-1, -1}; /* for path A and path B */
2909 bool retval = true;
2910
2911 if (priv->tx_paths > 1)
2912 bound = 8;
2913 else
2914 bound = 4;
2915
2916 simubitmap = 0;
2917
2918 for (i = 0; i < bound; i++) {
2919 diff = (result[c1][i] > result[c2][i]) ?
2920 (result[c1][i] - result[c2][i]) :
2921 (result[c2][i] - result[c1][i]);
2922 if (diff > MAX_TOLERANCE) {
2923 if ((i == 2 || i == 6) && !simubitmap) {
2924 if (result[c1][i] + result[c1][i + 1] == 0)
2925 candidate[(i / 4)] = c2;
2926 else if (result[c2][i] + result[c2][i + 1] == 0)
2927 candidate[(i / 4)] = c1;
2928 else
2929 simubitmap = simubitmap | (1 << i);
2930 } else {
2931 simubitmap = simubitmap | (1 << i);
2932 }
2933 }
2934 }
2935
2936 if (simubitmap == 0) {
2937 for (i = 0; i < (bound / 4); i++) {
2938 if (candidate[i] >= 0) {
2939 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2940 result[3][j] = result[candidate[i]][j];
2941 retval = false;
2942 }
2943 }
2944 return retval;
2945 } else if (!(simubitmap & 0x0f)) {
2946 /* path A OK */
2947 for (i = 0; i < 4; i++)
2948 result[3][i] = result[c1][i];
2949 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2950 /* path B OK */
2951 for (i = 4; i < 8; i++)
2952 result[3][i] = result[c1][i];
2953 }
2954
2955 return false;
2956}
2957
2958static void
2959rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2960{
2961 int i;
2962
2963 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2964 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2965
2966 backup[i] = rtl8xxxu_read32(priv, reg[i]);
2967}
2968
2969static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2970 const u32 *reg, u32 *backup)
2971{
2972 int i;
2973
2974 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2975 rtl8xxxu_write8(priv, reg[i], backup[i]);
2976
2977 rtl8xxxu_write32(priv, reg[i], backup[i]);
2978}
2979
2980static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2981 u32 *backup, int count)
2982{
2983 int i;
2984
2985 for (i = 0; i < count; i++)
2986 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2987}
2988
2989static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2990 u32 *backup, int count)
2991{
2992 int i;
2993
2994 for (i = 0; i < count; i++)
2995 rtl8xxxu_write32(priv, regs[i], backup[i]);
2996}
2997
2998
2999static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3000 bool path_a_on)
3001{
3002 u32 path_on;
3003 int i;
3004
3005 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3006 if (priv->tx_paths == 1) {
3007 path_on = 0x0bdb25a0;
3008 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3009 } else {
3010 rtl8xxxu_write32(priv, regs[0], path_on);
3011 }
3012
3013 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3014 rtl8xxxu_write32(priv, regs[i], path_on);
3015}
3016
3017static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3018 const u32 *regs, u32 *backup)
3019{
3020 int i = 0;
3021
3022 rtl8xxxu_write8(priv, regs[i], 0x3f);
3023
3024 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3025 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3026
3027 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3028}
3029
3030static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3031{
3032 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3033 int result = 0;
3034
3035 /* path-A IQK setting */
3036 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3037 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3038 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3039
3040 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3041 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3042 0x28160502;
3043 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3044
3045 /* path-B IQK setting */
3046 if (priv->rf_paths > 1) {
3047 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3048 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3049 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3050 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3051 }
3052
3053 /* LO calibration setting */
3054 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3055
3056 /* One shot, path A LOK & IQK */
3057 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3058 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3059
3060 mdelay(1);
3061
3062 /* Check failed */
3063 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3064 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3065 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3066 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3067
3068 if (!(reg_eac & BIT(28)) &&
3069 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3070 ((reg_e9c & 0x03ff0000) != 0x00420000))
3071 result |= 0x01;
3072 else /* If TX not OK, ignore RX */
3073 goto out;
3074
3075 /* If TX is OK, check whether RX is OK */
3076 if (!(reg_eac & BIT(27)) &&
3077 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3078 ((reg_eac & 0x03ff0000) != 0x00360000))
3079 result |= 0x02;
3080 else
3081 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3082 __func__);
3083out:
3084 return result;
3085}
3086
3087static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3088{
3089 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3090 int result = 0;
3091
3092 /* One shot, path B LOK & IQK */
3093 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3094 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3095
3096 mdelay(1);
3097
3098 /* Check failed */
3099 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3100 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3101 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3102 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3103 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3104
3105 if (!(reg_eac & BIT(31)) &&
3106 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3107 ((reg_ebc & 0x03ff0000) != 0x00420000))
3108 result |= 0x01;
3109 else
3110 goto out;
3111
3112 if (!(reg_eac & BIT(30)) &&
3113 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3114 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3115 result |= 0x02;
3116 else
3117 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3118 __func__);
3119out:
3120 return result;
3121}
3122
3123static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3124 int result[][8], int t)
3125{
3126 struct device *dev = &priv->udev->dev;
3127 u32 i, val32;
3128 int path_a_ok, path_b_ok;
3129 int retry = 2;
3130 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3131 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3132 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3133 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3134 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3135 REG_TX_TO_TX, REG_RX_CCK,
3136 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3137 REG_RX_TO_RX, REG_STANDBY,
3138 REG_SLEEP, REG_PMPD_ANAEN
3139 };
3140 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3141 REG_TXPAUSE, REG_BEACON_CTRL,
3142 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3143 };
3144 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3145 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3146 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3147 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3148 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3149 };
3150
3151 /*
3152 * Note: IQ calibration must be performed after loading
3153 * PHY_REG.txt , and radio_a, radio_b.txt
3154 */
3155
3156 if (t == 0) {
3157 /* Save ADDA parameters, turn Path A ADDA on */
3158 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3159 RTL8XXXU_ADDA_REGS);
3160 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3161 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3162 priv->bb_backup, RTL8XXXU_BB_REGS);
3163 }
3164
3165 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3166
3167 if (t == 0) {
3168 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3169 if (val32 & FPGA0_HSSI_PARM1_PI)
3170 priv->pi_enabled = 1;
3171 }
3172
3173 if (!priv->pi_enabled) {
3174 /* Switch BB to PI mode to do IQ Calibration. */
3175 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3176 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3177 }
3178
3179 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3180 val32 &= ~FPGA_RF_MODE_CCK;
3181 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3182
3183 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3184 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3185 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3186
3187 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3188 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3189 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3190
3191 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3192 val32 &= ~BIT(10);
3193 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3194 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3195 val32 &= ~BIT(10);
3196 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3197
3198 if (priv->tx_paths > 1) {
3199 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3200 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3201 }
3202
3203 /* MAC settings */
3204 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3205
3206 /* Page B init */
3207 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3208
3209 if (priv->tx_paths > 1)
3210 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3211
3212 /* IQ calibration setting */
3213 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3214 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3215 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3216
3217 for (i = 0; i < retry; i++) {
3218 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3219 if (path_a_ok == 0x03) {
3220 val32 = rtl8xxxu_read32(priv,
3221 REG_TX_POWER_BEFORE_IQK_A);
3222 result[t][0] = (val32 >> 16) & 0x3ff;
3223 val32 = rtl8xxxu_read32(priv,
3224 REG_TX_POWER_AFTER_IQK_A);
3225 result[t][1] = (val32 >> 16) & 0x3ff;
3226 val32 = rtl8xxxu_read32(priv,
3227 REG_RX_POWER_BEFORE_IQK_A_2);
3228 result[t][2] = (val32 >> 16) & 0x3ff;
3229 val32 = rtl8xxxu_read32(priv,
3230 REG_RX_POWER_AFTER_IQK_A_2);
3231 result[t][3] = (val32 >> 16) & 0x3ff;
3232 break;
3233 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3234 /* TX IQK OK */
3235 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3236 __func__);
3237
3238 val32 = rtl8xxxu_read32(priv,
3239 REG_TX_POWER_BEFORE_IQK_A);
3240 result[t][0] = (val32 >> 16) & 0x3ff;
3241 val32 = rtl8xxxu_read32(priv,
3242 REG_TX_POWER_AFTER_IQK_A);
3243 result[t][1] = (val32 >> 16) & 0x3ff;
3244 }
3245 }
3246
3247 if (!path_a_ok)
3248 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3249
3250 if (priv->tx_paths > 1) {
3251 /*
3252 * Path A into standby
3253 */
3254 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3255 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3256 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3257
3258 /* Turn Path B ADDA on */
3259 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3260
3261 for (i = 0; i < retry; i++) {
3262 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3263 if (path_b_ok == 0x03) {
3264 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3265 result[t][4] = (val32 >> 16) & 0x3ff;
3266 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3267 result[t][5] = (val32 >> 16) & 0x3ff;
3268 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3269 result[t][6] = (val32 >> 16) & 0x3ff;
3270 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3271 result[t][7] = (val32 >> 16) & 0x3ff;
3272 break;
3273 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3274 /* TX IQK OK */
3275 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3276 result[t][4] = (val32 >> 16) & 0x3ff;
3277 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3278 result[t][5] = (val32 >> 16) & 0x3ff;
3279 }
3280 }
3281
3282 if (!path_b_ok)
3283 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3284 }
3285
3286 /* Back to BB mode, load original value */
3287 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3288
3289 if (t) {
3290 if (!priv->pi_enabled) {
3291 /*
3292 * Switch back BB to SI mode after finishing
3293 * IQ Calibration
3294 */
3295 val32 = 0x01000000;
3296 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3297 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3298 }
3299
3300 /* Reload ADDA power saving parameters */
3301 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3302 RTL8XXXU_ADDA_REGS);
3303
3304 /* Reload MAC parameters */
3305 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3306
3307 /* Reload BB parameters */
3308 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3309 priv->bb_backup, RTL8XXXU_BB_REGS);
3310
3311 /* Restore RX initial gain */
3312 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3313
3314 if (priv->tx_paths > 1) {
3315 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3316 0x00032ed3);
3317 }
3318
3319 /* Load 0xe30 IQC default value */
3320 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3321 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3322 }
3323}
3324
3325static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3326{
3327 struct device *dev = &priv->udev->dev;
3328 int result[4][8]; /* last is final result */
3329 int i, candidate;
3330 bool path_a_ok, path_b_ok;
3331 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3332 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3333 s32 reg_tmp = 0;
3334 bool simu;
3335
3336 memset(result, 0, sizeof(result));
3337 candidate = -1;
3338
3339 path_a_ok = false;
3340 path_b_ok = false;
3341
3342 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3343
3344 for (i = 0; i < 3; i++) {
3345 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3346
3347 if (i == 1) {
3348 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3349 if (simu) {
3350 candidate = 0;
3351 break;
3352 }
3353 }
3354
3355 if (i == 2) {
3356 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3357 if (simu) {
3358 candidate = 0;
3359 break;
3360 }
3361
3362 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3363 if (simu) {
3364 candidate = 1;
3365 } else {
3366 for (i = 0; i < 8; i++)
3367 reg_tmp += result[3][i];
3368
3369 if (reg_tmp)
3370 candidate = 3;
3371 else
3372 candidate = -1;
3373 }
3374 }
3375 }
3376
3377 for (i = 0; i < 4; i++) {
3378 reg_e94 = result[i][0];
3379 reg_e9c = result[i][1];
3380 reg_ea4 = result[i][2];
3381 reg_eac = result[i][3];
3382 reg_eb4 = result[i][4];
3383 reg_ebc = result[i][5];
3384 reg_ec4 = result[i][6];
3385 reg_ecc = result[i][7];
3386 }
3387
3388 if (candidate >= 0) {
3389 reg_e94 = result[candidate][0];
3390 priv->rege94 = reg_e94;
3391 reg_e9c = result[candidate][1];
3392 priv->rege9c = reg_e9c;
3393 reg_ea4 = result[candidate][2];
3394 reg_eac = result[candidate][3];
3395 reg_eb4 = result[candidate][4];
3396 priv->regeb4 = reg_eb4;
3397 reg_ebc = result[candidate][5];
3398 priv->regebc = reg_ebc;
3399 reg_ec4 = result[candidate][6];
3400 reg_ecc = result[candidate][7];
3401 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3402 dev_dbg(dev,
3403 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3404 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3405 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3406 path_a_ok = true;
3407 path_b_ok = true;
3408 } else {
3409 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3410 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3411 }
3412
3413 if (reg_e94 && candidate >= 0)
3414 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3415 candidate, (reg_ea4 == 0));
3416
3417 if (priv->tx_paths > 1 && reg_eb4)
3418 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3419 candidate, (reg_ec4 == 0));
3420
3421 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3422 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3423}
3424
3425static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3426{
3427 u32 val32;
3428 u32 rf_amode, rf_bmode = 0, lstf;
3429
3430 /* Check continuous TX and Packet TX */
3431 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3432
3433 if (lstf & OFDM_LSTF_MASK) {
3434 /* Disable all continuous TX */
3435 val32 = lstf & ~OFDM_LSTF_MASK;
3436 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3437
3438 /* Read original RF mode Path A */
3439 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3440
3441 /* Set RF mode to standby Path A */
3442 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3443 (rf_amode & 0x8ffff) | 0x10000);
3444
3445 /* Path-B */
3446 if (priv->tx_paths > 1) {
3447 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3448 RF6052_REG_AC);
3449
3450 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3451 (rf_bmode & 0x8ffff) | 0x10000);
3452 }
3453 } else {
3454 /* Deal with Packet TX case */
3455 /* block all queues */
3456 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3457 }
3458
3459 /* Start LC calibration */
3460 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3461 val32 |= 0x08000;
3462 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3463
3464 msleep(100);
3465
3466 /* Restore original parameters */
3467 if (lstf & OFDM_LSTF_MASK) {
3468 /* Path-A */
3469 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3470 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3471
3472 /* Path-B */
3473 if (priv->tx_paths > 1)
3474 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3475 rf_bmode);
3476 } else /* Deal with Packet TX case */
3477 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3478}
3479
3480static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3481{
3482 int i;
3483 u16 reg;
3484
3485 reg = REG_MACID;
3486
3487 for (i = 0; i < ETH_ALEN; i++)
3488 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3489
3490 return 0;
3491}
3492
3493static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3494{
3495 int i;
3496 u16 reg;
3497
3498 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3499
3500 reg = REG_BSSID;
3501
3502 for (i = 0; i < ETH_ALEN; i++)
3503 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3504
3505 return 0;
3506}
3507
3508static void
3509rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3510{
3511 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3512 u8 max_agg = 0xf;
3513 int i;
3514
3515 ampdu_factor = 1 << (ampdu_factor + 2);
3516 if (ampdu_factor > max_agg)
3517 ampdu_factor = max_agg;
3518
3519 for (i = 0; i < 4; i++) {
3520 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3521 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3522
3523 if ((vals[i] & 0x0f) > ampdu_factor)
3524 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3525
3526 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3527 }
3528}
3529
3530static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3531{
3532 u8 val8;
3533
3534 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3535 val8 &= 0xf8;
3536 val8 |= density;
3537 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3538}
3539
3540static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3541{
3542 u8 val8;
3543 int count, ret;
3544
3545 /* Start of rtl8723AU_card_enable_flow */
3546 /* Act to Cardemu sequence*/
3547 /* Turn off RF */
3548 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3549
3550 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3551 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3552 val8 &= ~LEDCFG2_DPDT_SELECT;
3553 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3554
3555 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3556 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3557 val8 |= BIT(1);
3558 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3559
3560 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3561 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3562 if ((val8 & BIT(1)) == 0)
3563 break;
3564 udelay(10);
3565 }
3566
3567 if (!count) {
3568 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3569 __func__);
3570 ret = -EBUSY;
3571 goto exit;
3572 }
3573
3574 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3575 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3576 val8 |= SYS_ISO_ANALOG_IPS;
3577 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3578
3579 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3580 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3581 val8 &= ~LDOA15_ENABLE;
3582 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3583
3584exit:
3585 return ret;
3586}
3587
3588static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3589{
3590 u8 val8;
3591 u8 val32;
3592 int count, ret;
3593
3594 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3595
3596 /*
3597 * Poll - wait for RX packet to complete
3598 */
3599 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3600 val32 = rtl8xxxu_read32(priv, 0x5f8);
3601 if (!val32)
3602 break;
3603 udelay(10);
3604 }
3605
3606 if (!count) {
3607 dev_warn(&priv->udev->dev,
3608 "%s: RX poll timed out (0x05f8)\n", __func__);
3609 ret = -EBUSY;
3610 goto exit;
3611 }
3612
3613 /* Disable CCK and OFDM, clock gated */
3614 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3615 val8 &= ~SYS_FUNC_BBRSTB;
3616 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3617
3618 udelay(2);
3619
3620 /* Reset baseband */
3621 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3622 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3623 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3624
3625 /* Reset MAC TRX */
3626 val8 = rtl8xxxu_read8(priv, REG_CR);
3627 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3628 rtl8xxxu_write8(priv, REG_CR, val8);
3629
3630 /* Reset MAC TRX */
3631 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3632 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3633 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3634
3635 /* Respond TX OK to scheduler */
3636 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3637 val8 |= DUAL_TSF_TX_OK;
3638 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3639
3640exit:
3641 return ret;
3642}
3643
3644static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3645{
3646 u8 val8;
3647
3648 /* Clear suspend enable and power down enable*/
3649 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3650 val8 &= ~(BIT(3) | BIT(7));
3651 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3652
3653 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3654 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3655 val8 &= ~BIT(0);
3656 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3657
3658 /* 0x04[12:11] = 11 enable WL suspend*/
3659 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3660 val8 &= ~(BIT(3) | BIT(4));
3661 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3662}
3663
3664static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3665{
3666 u8 val8;
3667 u32 val32;
3668 int count, ret = 0;
3669
3670 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3671 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3672 val8 |= LDOA15_ENABLE;
3673 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3674
3675 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3676 val8 = rtl8xxxu_read8(priv, 0x0067);
3677 val8 &= ~BIT(4);
3678 rtl8xxxu_write8(priv, 0x0067, val8);
3679
3680 mdelay(1);
3681
3682 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3683 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3684 val8 &= ~SYS_ISO_ANALOG_IPS;
3685 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3686
3687 /* disable SW LPS 0x04[10]= 0 */
3688 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3689 val8 &= ~BIT(2);
3690 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3691
3692 /* wait till 0x04[17] = 1 power ready*/
3693 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3694 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3695 if (val32 & BIT(17))
3696 break;
3697
3698 udelay(10);
3699 }
3700
3701 if (!count) {
3702 ret = -EBUSY;
3703 goto exit;
3704 }
3705
3706 /* We should be able to optimize the following three entries into one */
3707
3708 /* release WLON reset 0x04[16]= 1*/
3709 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3710 val8 |= BIT(0);
3711 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3712
3713 /* disable HWPDN 0x04[15]= 0*/
3714 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3715 val8 &= ~BIT(7);
3716 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3717
3718 /* disable WL suspend*/
3719 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3720 val8 &= ~(BIT(3) | BIT(4));
3721 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3722
3723 /* set, then poll until 0 */
3724 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3725 val32 |= APS_FSMCO_MAC_ENABLE;
3726 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3727
3728 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3729 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3730 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3731 ret = 0;
3732 break;
3733 }
3734 udelay(10);
3735 }
3736
3737 if (!count) {
3738 ret = -EBUSY;
3739 goto exit;
3740 }
3741
3742 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3743 /*
3744 * Note: Vendor driver actually clears this bit, despite the
3745 * documentation claims it's being set!
3746 */
3747 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3748 val8 |= LEDCFG2_DPDT_SELECT;
3749 val8 &= ~LEDCFG2_DPDT_SELECT;
3750 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3751
3752exit:
3753 return ret;
3754}
3755
3756static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3757{
3758 u8 val8;
3759
3760 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3761 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3762
3763 /* 0x04[12:11] = 01 enable WL suspend */
3764 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3765 val8 &= ~BIT(4);
3766 val8 |= BIT(3);
3767 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3768
3769 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3770 val8 |= BIT(7);
3771 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3772
3773 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3774 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3775 val8 |= BIT(0);
3776 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3777
3778 return 0;
3779}
3780
3781static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3782{
3783 u8 val8;
3784 u16 val16;
3785 u32 val32;
3786 int ret;
3787
3788 /*
3789 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3790 */
3791 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3792
3793 rtl8xxxu_disabled_to_emu(priv);
3794
3795 ret = rtl8xxxu_emu_to_active(priv);
3796 if (ret)
3797 goto exit;
3798
3799 /*
3800 * 0x0004[19] = 1, reset 8051
3801 */
3802 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3803 val8 |= BIT(3);
3804 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3805
3806 /*
3807 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3808 * Set CR bit10 to enable 32k calibration.
3809 */
3810 val16 = rtl8xxxu_read16(priv, REG_CR);
3811 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3812 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3813 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3814 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3815 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3816 rtl8xxxu_write16(priv, REG_CR, val16);
3817
3818 /* For EFuse PG */
3819 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3820 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3821 val32 |= (0x06 << 28);
3822 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3823exit:
3824 return ret;
3825}
3826
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3827#ifdef CONFIG_RTL8XXXU_UNTESTED
3828
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3829static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3830{
3831 u8 val8;
3832 u16 val16;
3833 u32 val32;
3834 int i;
3835
3836 for (i = 100; i; i--) {
3837 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3838 if (val8 & APS_FSMCO_PFM_ALDN)
3839 break;
3840 }
3841
3842 if (!i) {
3843 pr_info("%s: Poll failed\n", __func__);
3844 return -ENODEV;
3845 }
3846
3847 /*
3848 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3849 */
3850 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3851 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3852 udelay(100);
3853
3854 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3855 if (!(val8 & LDOV12D_ENABLE)) {
3856 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3857 val8 |= LDOV12D_ENABLE;
3858 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3859
3860 udelay(100);
3861
3862 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3863 val8 &= ~SYS_ISO_MD2PP;
3864 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3865 }
3866
3867 /*
3868 * Auto enable WLAN
3869 */
3870 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3871 val16 |= APS_FSMCO_MAC_ENABLE;
3872 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3873
3874 for (i = 1000; i; i--) {
3875 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3876 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3877 break;
3878 }
3879 if (!i) {
3880 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3881 return -EBUSY;
3882 }
3883
3884 /*
3885 * Enable radio, GPIO, LED
3886 */
3887 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3888 APS_FSMCO_PFM_ALDN;
3889 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3890
3891 /*
3892 * Release RF digital isolation
3893 */
3894 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3895 val16 &= ~SYS_ISO_DIOR;
3896 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3897
3898 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3899 val8 &= ~APSD_CTRL_OFF;
3900 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3901 for (i = 200; i; i--) {
3902 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3903 if (!(val8 & APSD_CTRL_OFF_STATUS))
3904 break;
3905 }
3906
3907 if (!i) {
3908 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3909 return -EBUSY;
3910 }
3911
3912 /*
3913 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3914 */
3915 val16 = rtl8xxxu_read16(priv, REG_CR);
3916 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3917 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3918 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3919 rtl8xxxu_write16(priv, REG_CR, val16);
3920
3921 /*
3922 * Workaround for 8188RU LNA power leakage problem.
3923 */
3924 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3925 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3926 val32 &= ~BIT(1);
3927 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3928 }
3929 return 0;
3930}
3931
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3932#endif
3933
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3934static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3935{
3936 u8 val8;
3937 u16 val16;
3938 u32 val32;
3939
3940 /*
3941 * Workaround for 8188RU LNA power leakage problem.
3942 */
3943 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3944 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3945 val32 |= BIT(1);
3946 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3947 }
3948
3949 rtl8xxxu_active_to_lps(priv);
3950
3951 /* Turn off RF */
3952 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3953
3954 /* Reset Firmware if running in RAM */
3955 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3956 rtl8xxxu_firmware_self_reset(priv);
3957
3958 /* Reset MCU */
3959 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3960 val16 &= ~SYS_FUNC_CPU_ENABLE;
3961 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3962
3963 /* Reset MCU ready status */
3964 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3965
3966 rtl8xxxu_active_to_emu(priv);
3967 rtl8xxxu_emu_to_disabled(priv);
3968
3969 /* Reset MCU IO Wrapper */
3970 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3971 val8 &= ~BIT(0);
3972 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3973
3974 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3975 val8 |= BIT(0);
3976 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3977
3978 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3979 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3980}
3981
3982static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
3983{
3984 if (!priv->has_bluetooth)
3985 return;
3986}
3987
3988static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3989{
3990 struct rtl8xxxu_priv *priv = hw->priv;
3991 struct device *dev = &priv->udev->dev;
3992 struct rtl8xxxu_rfregval *rftable;
3993 bool macpower;
3994 int ret;
3995 u8 val8;
3996 u16 val16;
3997 u32 val32;
3998
3999 /* Check if MAC is already powered on */
4000 val8 = rtl8xxxu_read8(priv, REG_CR);
4001
4002 /*
4003 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4004 * initialized. First MAC returns 0xea, second MAC returns 0x00
4005 */
4006 if (val8 == 0xea)
4007 macpower = false;
4008 else
4009 macpower = true;
4010
4011 ret = priv->fops->power_on(priv);
4012 if (ret < 0) {
4013 dev_warn(dev, "%s: Failed power on\n", __func__);
4014 goto exit;
4015 }
4016
4017 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4018 if (!macpower) {
4019 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4020 if (ret) {
4021 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4022 goto exit;
4023 }
4024 }
4025
4026 ret = rtl8xxxu_download_firmware(priv);
4027 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4028 if (ret)
4029 goto exit;
4030 ret = rtl8xxxu_start_firmware(priv);
4031 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4032 if (ret)
4033 goto exit;
4034
4035 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4036 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4037 if (ret)
4038 goto exit;
4039
4040 ret = rtl8xxxu_init_phy_bb(priv);
4041 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4042 if (ret)
4043 goto exit;
4044
4045 switch(priv->rtlchip) {
4046 case 0x8723a:
4047 rftable = rtl8723au_radioa_1t_init_table;
4048 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4049 break;
4050 case 0x8188c:
4051 if (priv->hi_pa)
4052 rftable = rtl8188ru_radioa_1t_highpa_table;
4053 else
4054 rftable = rtl8192cu_radioa_1t_init_table;
4055 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4056 break;
4057 case 0x8191c:
4058 rftable = rtl8192cu_radioa_1t_init_table;
4059 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4060 break;
4061 case 0x8192c:
4062 rftable = rtl8192cu_radioa_2t_init_table;
4063 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4064 if (ret)
4065 break;
4066 rftable = rtl8192cu_radiob_2t_init_table;
4067 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4068 break;
4069 default:
4070 ret = -EINVAL;
4071 }
4072
4073 if (ret)
4074 goto exit;
4075
4076 /* Reduce 80M spur */
4077 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4078 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4079 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4080 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4081
4082 /* RFSW Control - clear bit 14 ?? */
4083 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4084 /* 0x07000760 */
4085 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4086 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4087 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4088 FPGA0_RF_BD_CTRL_SHIFT);
4089 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4090 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4091 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4092
4093 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4094 RF6052_REG_MODE_AG);
4095
4096 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4097 if (!macpower) {
4098 if (priv->ep_tx_normal_queue)
4099 val8 = TX_PAGE_NUM_NORM_PQ;
4100 else
4101 val8 = 0;
4102
4103 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4104
4105 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4106
4107 if (priv->ep_tx_high_queue)
4108 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4109 if (priv->ep_tx_low_queue)
4110 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4111
4112 rtl8xxxu_write32(priv, REG_RQPN, val32);
4113
4114 /*
4115 * Set TX buffer boundary
4116 */
4117 val8 = TX_TOTAL_PAGE_NUM + 1;
4118 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4119 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4120 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4121 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4122 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4123 }
4124
4125 ret = rtl8xxxu_init_queue_priority(priv);
4126 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4127 if (ret)
4128 goto exit;
4129
4130 /*
4131 * Set RX page boundary
4132 */
4133 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4134 /*
4135 * Transfer page size is always 128
4136 */
4137 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4138 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4139 rtl8xxxu_write8(priv, REG_PBP, val8);
4140
4141 /*
4142 * Unit in 8 bytes, not obvious what it is used for
4143 */
4144 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4145
4146 /*
4147 * Enable all interrupts - not obvious USB needs to do this
4148 */
4149 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4150 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4151
4152 rtl8xxxu_set_mac(priv);
4153 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4154
4155 /*
4156 * Configure initial WMAC settings
4157 */
4158 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4159 /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */
4160 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4161 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4162 rtl8xxxu_write32(priv, REG_RCR, val32);
4163
4164 /*
4165 * Accept all multicast
4166 */
4167 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4168 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4169
4170 /*
4171 * Init adaptive controls
4172 */
4173 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4174 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4175 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4176 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4177
4178 /* CCK = 0x0a, OFDM = 0x10 */
4179 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4180 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4181 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4182
4183 /*
4184 * Init EDCA
4185 */
4186 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4187
4188 /* Set CCK SIFS */
4189 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4190
4191 /* Set OFDM SIFS */
4192 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4193
4194 /* TXOP */
4195 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4196 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4197 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4198 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4199
4200 /* Set data auto rate fallback retry count */
4201 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4202 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4203 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4204 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4205
4206 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4207 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4208 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4209
4210 /* Set ACK timeout */
4211 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4212
4213 /*
4214 * Initialize beacon parameters
4215 */
4216 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4217 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4218 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4219 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4220 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4221 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4222
4223 /*
4224 * Enable CCK and OFDM block
4225 */
4226 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4227 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4228 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4229
4230 /*
4231 * Invalidate all CAM entries - bit 30 is undocumented
4232 */
4233 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4234
4235 /*
4236 * Start out with default power levels for channel 6, 20MHz
4237 */
4238 rtl8723a_set_tx_power(priv, 1, false);
4239
4240 /* Let the 8051 take control of antenna setting */
4241 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4242 val8 |= LEDCFG2_DPDT_SELECT;
4243 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4244
4245 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4246
4247 /* Disable BAR - not sure if this has any effect on USB */
4248 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4249
4250 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4251
4252 /*
4253 * Not sure if we should get into this at all
4254 */
4255 if (priv->iqk_initialized) {
4256 rtl8xxxu_restore_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4257 priv->bb_recovery_backup,
4258 RTL8XXXU_BB_REGS);
4259 } else {
4260 rtl8723a_phy_iq_calibrate(priv);
4261 priv->iqk_initialized = true;
4262 }
4263
4264 /*
4265 * This should enable thermal meter
4266 */
4267 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4268
4269 rtl8723a_phy_lc_calibrate(priv);
4270
4271 /* fix USB interface interference issue */
4272 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4273 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4274 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4275 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4276
4277 /* Solve too many protocol error on USB bus */
4278 /* Can't do this for 8188/8192 UMC A cut parts */
4279 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4280 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4281 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4282
4283 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4284 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4285 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4286
4287 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4288 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4289 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4290
4291 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4292 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4293 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4294
4295 /* Init BT hw config. */
4296 rtl8xxxu_init_bt(priv);
4297
4298 /*
4299 * Not sure if we really need to save these parameters, but the
4300 * vendor driver does
4301 */
4302 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4303 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4304 priv->path_a_hi_power = 1;
4305
4306 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4307 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4308
4309 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4310 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4311
4312 /* Set NAV_UPPER to 30000us */
4313 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4314 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4315
4316 /*
4317 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4318 * but we need to fin root cause.
4319 */
4320 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4321 if ((val32 & 0xff000000) != 0x83000000) {
4322 val32 |= FPGA_RF_MODE_CCK;
4323 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4324 }
4325
4326 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4327 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4328 /* ack for xmit mgmt frames. */
4329 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4330
4331exit:
4332 return ret;
4333}
4334
4335static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4336{
4337 struct rtl8xxxu_priv *priv = hw->priv;
4338
4339 rtl8xxxu_power_off(priv);
4340}
4341
4342static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4343 struct ieee80211_key_conf *key, const u8 *mac)
4344{
4345 u32 cmd, val32, addr, ctrl;
4346 int j, i, tmp_debug;
4347
4348 tmp_debug = rtl8xxxu_debug;
4349 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4350 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4351
4352 /*
4353 * This is a bit of a hack - the lower bits of the cipher
4354 * suite selector happens to match the cipher index in the CAM
4355 */
4356 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4357 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4358
4359 for (j = 5; j >= 0; j--) {
4360 switch (j) {
4361 case 0:
4362 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4363 break;
4364 case 1:
4365 val32 = mac[2] | (mac[3] << 8) |
4366 (mac[4] << 16) | (mac[5] << 24);
4367 break;
4368 default:
4369 i = (j - 2) << 2;
4370 val32 = key->key[i] | (key->key[i + 1] << 8) |
4371 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4372 break;
4373 }
4374
4375 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4376 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4377 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4378 udelay(100);
4379 }
4380
4381 rtl8xxxu_debug = tmp_debug;
4382}
4383
4384static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4385 struct ieee80211_vif *vif, const u8* mac)
4386{
4387 struct rtl8xxxu_priv *priv = hw->priv;
4388 u8 val8;
4389
4390 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4391 val8 |= BEACON_DISABLE_TSF_UPDATE;
4392 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4393}
4394
4395static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4396 struct ieee80211_vif *vif)
4397{
4398 struct rtl8xxxu_priv *priv = hw->priv;
4399 u8 val8;
4400
4401 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4402 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4403 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4404}
4405
4406static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4407 u32 ramask, int sgi)
4408{
4409 struct h2c_cmd h2c;
4410
4411 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4412 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4413 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4414
4415 h2c.ramask.arg = 0x80;
4416 if (sgi)
4417 h2c.ramask.arg |= 0x20;
4418
4419 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4420 ramask, h2c.ramask.arg);
4421 rtl8723a_h2c_cmd(priv, &h2c);
4422}
4423
4424static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4425{
4426 u32 val32;
4427 u8 rate_idx = 0;
4428
4429 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4430
4431 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4432 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4433 val32 |= rate_cfg;
4434 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4435
4436 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4437
4438 while (rate_cfg) {
4439 rate_cfg = (rate_cfg >> 1);
4440 rate_idx++;
4441 }
4442 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4443}
4444
4445static void
4446rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4447 struct ieee80211_bss_conf *bss_conf, u32 changed)
4448{
4449 struct rtl8xxxu_priv *priv = hw->priv;
4450 struct device *dev = &priv->udev->dev;
4451 struct ieee80211_sta *sta;
4452 u32 val32;
4453 u8 val8;
4454
4455 if (changed & BSS_CHANGED_ASSOC) {
4456 struct h2c_cmd h2c;
4457
4458 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4459
4460 memset(&h2c, 0, sizeof(struct h2c_cmd));
4461 rtl8xxxu_set_linktype(priv, vif->type);
4462
4463 if (bss_conf->assoc) {
4464 u32 ramask;
4465 int sgi = 0;
4466
4467 rcu_read_lock();
4468 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4469 if (!sta) {
4470 dev_info(dev, "%s: ASSOC no sta found\n",
4471 __func__);
4472 rcu_read_unlock();
4473 goto error;
4474 }
4475
4476 if (sta->ht_cap.ht_supported)
4477 dev_info(dev, "%s: HT supported\n", __func__);
4478 if (sta->vht_cap.vht_supported)
4479 dev_info(dev, "%s: VHT supported\n", __func__);
4480
4481 /* TODO: Set bits 28-31 for rate adaptive id */
4482 ramask = (sta->supp_rates[0] & 0xfff) |
4483 sta->ht_cap.mcs.rx_mask[0] << 12 |
4484 sta->ht_cap.mcs.rx_mask[1] << 20;
4485 if (sta->ht_cap.cap &
4486 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4487 sgi = 1;
4488 rcu_read_unlock();
4489
4490 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4491
4492 val32 = rtl8xxxu_read32(priv, REG_RCR);
4493 val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON;
4494 rtl8xxxu_write32(priv, REG_RCR, val32);
4495
4496 /* Enable RX of data frames */
4497 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4498
4499 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4500
4501 rtl8723a_stop_tx_beacon(priv);
4502
4503 /* joinbss sequence */
4504 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4505 0xc000 | bss_conf->aid);
4506
4507 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4508 } else {
4509 val32 = rtl8xxxu_read32(priv, REG_RCR);
4510 val32 &= ~(RCR_CHECK_BSSID_MATCH |
4511 RCR_CHECK_BSSID_BEACON);
4512 rtl8xxxu_write32(priv, REG_RCR, val32);
4513
4514 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4515 val8 |= BEACON_DISABLE_TSF_UPDATE;
4516 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4517
4518 /* Disable RX of data frames */
4519 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
4520 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4521 }
4522 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4523 rtl8723a_h2c_cmd(priv, &h2c);
4524 }
4525
4526 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4527 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4528 bss_conf->use_short_preamble);
4529 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4530 if (bss_conf->use_short_preamble)
4531 val32 |= RSR_ACK_SHORT_PREAMBLE;
4532 else
4533 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4534 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4535 }
4536
4537 if (changed & BSS_CHANGED_ERP_SLOT) {
4538 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4539 bss_conf->use_short_slot);
4540
4541 if (bss_conf->use_short_slot)
4542 val8 = 9;
4543 else
4544 val8 = 20;
4545 rtl8xxxu_write8(priv, REG_SLOT, val8);
4546 }
4547
4548 if (changed & BSS_CHANGED_BSSID) {
4549 dev_dbg(dev, "Changed BSSID!\n");
4550 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4551 }
4552
4553 if (changed & BSS_CHANGED_BASIC_RATES) {
4554 dev_dbg(dev, "Changed BASIC_RATES!\n");
4555 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4556 }
4557error:
4558 return;
4559}
4560
4561static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4562{
4563 u32 rtlqueue;
4564
4565 switch (queue) {
4566 case IEEE80211_AC_VO:
4567 rtlqueue = TXDESC_QUEUE_VO;
4568 break;
4569 case IEEE80211_AC_VI:
4570 rtlqueue = TXDESC_QUEUE_VI;
4571 break;
4572 case IEEE80211_AC_BE:
4573 rtlqueue = TXDESC_QUEUE_BE;
4574 break;
4575 case IEEE80211_AC_BK:
4576 rtlqueue = TXDESC_QUEUE_BK;
4577 break;
4578 default:
4579 rtlqueue = TXDESC_QUEUE_BE;
4580 }
4581
4582 return rtlqueue;
4583}
4584
4585static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4586{
4587 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4588 u32 queue;
4589
4590 if (ieee80211_is_mgmt(hdr->frame_control))
4591 queue = TXDESC_QUEUE_MGNT;
4592 else
4593 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4594
4595 return queue;
4596}
4597
4598static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4599{
4600 __le16 *ptr = (__le16 *)tx_desc;
4601 u16 csum = 0;
4602 int i;
4603
4604 /*
4605 * Clear csum field before calculation, as the csum field is
4606 * in the middle of the struct.
4607 */
4608 tx_desc->csum = cpu_to_le16(0);
4609
4610 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4611 csum = csum ^ le16_to_cpu(ptr[i]);
4612
4613 tx_desc->csum |= cpu_to_le16(csum);
4614}
4615
4616static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4617{
4618 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4619 unsigned long flags;
4620
4621 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4622 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4623 list_del(&tx_urb->list);
4624 priv->tx_urb_free_count--;
4625 usb_free_urb(&tx_urb->urb);
4626 }
4627 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4628}
4629
4630static struct rtl8xxxu_tx_urb *
4631rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4632{
4633 struct rtl8xxxu_tx_urb *tx_urb;
4634 unsigned long flags;
4635
4636 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4637 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4638 struct rtl8xxxu_tx_urb, list);
4639 if (tx_urb) {
4640 list_del(&tx_urb->list);
4641 priv->tx_urb_free_count--;
4642 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4643 !priv->tx_stopped) {
4644 priv->tx_stopped = true;
4645 ieee80211_stop_queues(priv->hw);
4646 }
4647 }
4648
4649 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4650
4651 return tx_urb;
4652}
4653
4654static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4655 struct rtl8xxxu_tx_urb *tx_urb)
4656{
4657 unsigned long flags;
4658
4659 INIT_LIST_HEAD(&tx_urb->list);
4660
4661 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4662
4663 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4664 priv->tx_urb_free_count++;
4665 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4666 priv->tx_stopped) {
4667 priv->tx_stopped = false;
4668 ieee80211_wake_queues(priv->hw);
4669 }
4670
4671 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4672}
4673
4674static void rtl8xxxu_tx_complete(struct urb *urb)
4675{
4676 struct sk_buff *skb = (struct sk_buff *)urb->context;
4677 struct ieee80211_tx_info *tx_info;
4678 struct ieee80211_hw *hw;
4679 struct rtl8xxxu_tx_urb *tx_urb =
4680 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4681
4682 tx_info = IEEE80211_SKB_CB(skb);
4683 hw = tx_info->rate_driver_data[0];
4684
4685 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4686
4687 ieee80211_tx_info_clear_status(tx_info);
4688 tx_info->status.rates[0].idx = -1;
4689 tx_info->status.rates[0].count = 0;
4690
4691 if (!urb->status)
4692 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4693
4694 ieee80211_tx_status_irqsafe(hw, skb);
4695
4696 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4697}
4698
4699static void rtl8xxxu_dump_action(struct device *dev,
4700 struct ieee80211_hdr *hdr)
4701{
4702 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4703 u16 cap, timeout;
4704
4705 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4706 return;
4707
4708 switch (mgmt->u.action.u.addba_resp.action_code) {
4709 case WLAN_ACTION_ADDBA_RESP:
4710 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4711 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4712 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4713 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4714 "status %02x\n",
4715 timeout,
4716 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4717 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4718 (cap >> 1) & 0x1,
4719 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4720 break;
4721 case WLAN_ACTION_ADDBA_REQ:
4722 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4723 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4724 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4725 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4726 timeout,
4727 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4728 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4729 (cap >> 1) & 0x1);
4730 break;
4731 default:
4732 dev_info(dev, "action frame %02x\n",
4733 mgmt->u.action.u.addba_resp.action_code);
4734 break;
4735 }
4736}
4737
4738static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4739 struct ieee80211_tx_control *control,
4740 struct sk_buff *skb)
4741{
4742 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4743 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4744 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4745 struct rtl8xxxu_priv *priv = hw->priv;
4746 struct rtl8xxxu_tx_desc *tx_desc;
4747 struct rtl8xxxu_tx_urb *tx_urb;
4748 struct ieee80211_sta *sta = NULL;
4749 struct ieee80211_vif *vif = tx_info->control.vif;
4750 struct device *dev = &priv->udev->dev;
4751 u32 queue, rate;
4752 u16 pktlen = skb->len;
4753 u16 seq_number;
4754 u16 rate_flag = tx_info->control.rates[0].flags;
4755 int ret;
4756
4757 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4758 dev_warn(dev,
4759 "%s: Not enough headroom (%i) for tx descriptor\n",
4760 __func__, skb_headroom(skb));
4761 goto error;
4762 }
4763
4764 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4765 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4766 __func__, skb->len);
4767 goto error;
4768 }
4769
4770 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4771 if (!tx_urb) {
4772 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4773 goto error;
4774 }
4775
4776 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4777 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4778 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4779
4780 if (ieee80211_is_action(hdr->frame_control))
4781 rtl8xxxu_dump_action(dev, hdr);
4782
4783 tx_info->rate_driver_data[0] = hw;
4784
4785 if (control && control->sta)
4786 sta = control->sta;
4787
4788 tx_desc = (struct rtl8xxxu_tx_desc *)
4789 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4790
4791 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4792 tx_desc->pkt_size = cpu_to_le16(pktlen);
4793 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4794
4795 tx_desc->txdw0 =
4796 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4797 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4798 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4799 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4800
4801 queue = rtl8xxxu_queue_select(hw, skb);
4802 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4803
4804 if (tx_info->control.hw_key) {
4805 switch (tx_info->control.hw_key->cipher) {
4806 case WLAN_CIPHER_SUITE_WEP40:
4807 case WLAN_CIPHER_SUITE_WEP104:
4808 case WLAN_CIPHER_SUITE_TKIP:
4809 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4810 break;
4811 case WLAN_CIPHER_SUITE_CCMP:
4812 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4813 break;
4814 default:
4815 break;
4816 }
4817 }
4818
4819 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4820 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4821
4822 if (rate_flag & IEEE80211_TX_RC_MCS)
4823 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4824 else
4825 rate = tx_rate->hw_value;
4826 tx_desc->txdw5 = cpu_to_le32(rate);
4827
4828 if (ieee80211_is_data(hdr->frame_control))
4829 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4830
4831 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4832 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4833 if (sta->ht_cap.ht_supported) {
4834 u32 ampdu, val32;
4835
4836 ampdu = (u32)sta->ht_cap.ampdu_density;
4837 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4838 tx_desc->txdw2 |= cpu_to_le32(val32);
4839 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4840 } else
4841 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4842 } else
4843 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4844
4845 if (ieee80211_is_data_qos(hdr->frame_control))
4846 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4847 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4848 (sta && vif && vif->bss_conf.use_short_preamble))
4849 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4850 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4851 (ieee80211_is_data_qos(hdr->frame_control) &&
4852 sta && sta->ht_cap.cap &
4853 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4854 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4855 }
4856 if (ieee80211_is_mgmt(hdr->frame_control)) {
4857 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4858 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4859 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4860 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4861 }
4862
4863 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4864 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4865 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4866 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4867 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4868 }
4869
4870 rtl8xxxu_calc_tx_desc_csum(tx_desc);
4871
4872 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4873 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4874
4875 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4876 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4877 if (ret) {
4878 usb_unanchor_urb(&tx_urb->urb);
4879 rtl8xxxu_free_tx_urb(priv, tx_urb);
4880 goto error;
4881 }
4882 return;
4883error:
4884 dev_kfree_skb(skb);
4885}
4886
4887static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4888 struct ieee80211_rx_status *rx_status,
4889 struct rtl8xxxu_rx_desc *rx_desc,
4890 struct rtl8723au_phy_stats *phy_stats)
4891{
4892 if (phy_stats->sgi_en)
4893 rx_status->flag |= RX_FLAG_SHORT_GI;
4894
4895 if (rx_desc->rxmcs < DESC_RATE_6M) {
4896 /*
4897 * Handle PHY stats for CCK rates
4898 */
4899 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4900
4901 switch (cck_agc_rpt & 0xc0) {
4902 case 0xc0:
4903 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4904 break;
4905 case 0x80:
4906 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4907 break;
4908 case 0x40:
4909 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4910 break;
4911 case 0x00:
4912 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4913 break;
4914 }
4915 } else {
4916 rx_status->signal =
4917 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4918 }
4919}
4920
4921static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4922{
4923 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4924 unsigned long flags;
4925
4926 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4927
4928 list_for_each_entry_safe(rx_urb, tmp,
4929 &priv->rx_urb_pending_list, list) {
4930 list_del(&rx_urb->list);
4931 priv->rx_urb_pending_count--;
4932 usb_free_urb(&rx_urb->urb);
4933 }
4934
4935 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4936}
4937
4938static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4939 struct rtl8xxxu_rx_urb *rx_urb)
4940{
4941 struct sk_buff *skb;
4942 unsigned long flags;
4943 int pending = 0;
4944
4945 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4946
4947 if (!priv->shutdown) {
4948 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4949 priv->rx_urb_pending_count++;
4950 pending = priv->rx_urb_pending_count;
4951 } else {
4952 skb = (struct sk_buff *)rx_urb->urb.context;
4953 dev_kfree_skb(skb);
4954 usb_free_urb(&rx_urb->urb);
4955 }
4956
4957 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4958
4959 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
4960 schedule_work(&priv->rx_urb_wq);
4961}
4962
4963static void rtl8xxxu_rx_urb_work(struct work_struct *work)
4964{
4965 struct rtl8xxxu_priv *priv;
4966 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4967 struct list_head local;
4968 struct sk_buff *skb;
4969 unsigned long flags;
4970 int ret;
4971
4972 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
4973 INIT_LIST_HEAD(&local);
4974
4975 spin_lock_irqsave(&priv->rx_urb_lock, flags);
4976
4977 list_splice_init(&priv->rx_urb_pending_list, &local);
4978 priv->rx_urb_pending_count = 0;
4979
4980 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4981
4982 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
4983 list_del_init(&rx_urb->list);
4984 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
4985 /*
4986 * If out of memory or temporary error, put it back on the
4987 * queue and try again. Otherwise the device is dead/gone
4988 * and we should drop it.
4989 */
4990 switch (ret) {
4991 case 0:
4992 break;
4993 case -ENOMEM:
4994 case -EAGAIN:
4995 rtl8xxxu_queue_rx_urb(priv, rx_urb);
4996 break;
4997 default:
4998 pr_info("failed to requeue urb %i\n", ret);
4999 skb = (struct sk_buff *)rx_urb->urb.context;
5000 dev_kfree_skb(skb);
5001 usb_free_urb(&rx_urb->urb);
5002 }
5003 }
5004}
5005
5006static void rtl8xxxu_rx_complete(struct urb *urb)
5007{
5008 struct rtl8xxxu_rx_urb *rx_urb =
5009 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5010 struct ieee80211_hw *hw = rx_urb->hw;
5011 struct rtl8xxxu_priv *priv = hw->priv;
5012 struct sk_buff *skb = (struct sk_buff *)urb->context;
5013 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5014 struct rtl8723au_phy_stats *phy_stats;
5015 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5016 struct ieee80211_mgmt *mgmt;
5017 struct device *dev = &priv->udev->dev;
5018 __le32 *_rx_desc_le = (__le32 *)skb->data;
5019 u32 *_rx_desc = (u32 *)skb->data;
5020 int cnt, len, drvinfo_sz, desc_shift, i;
5021
5022 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5023 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5024
5025 cnt = rx_desc->frag;
5026 len = rx_desc->pktlen;
5027 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5028 desc_shift = rx_desc->shift;
5029 skb_put(skb, urb->actual_length);
5030
5031 if (urb->status == 0) {
5032 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5033 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5034
5035 skb_pull(skb, drvinfo_sz + desc_shift);
5036
5037 mgmt = (struct ieee80211_mgmt *)skb->data;
5038
5039 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5040
5041 if (rx_desc->phy_stats)
5042 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5043 rx_desc, phy_stats);
5044
5045 rx_status->freq = hw->conf.chandef.chan->center_freq;
5046 rx_status->band = hw->conf.chandef.chan->band;
5047
5048 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5049 rx_status->flag |= RX_FLAG_MACTIME_START;
5050
5051 if (!rx_desc->swdec)
5052 rx_status->flag |= RX_FLAG_DECRYPTED;
5053 if (rx_desc->crc32)
5054 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5055 if (rx_desc->bw)
5056 rx_status->flag |= RX_FLAG_40MHZ;
5057
5058 if (rx_desc->rxht) {
5059 rx_status->flag |= RX_FLAG_HT;
5060 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5061 } else {
5062 rx_status->rate_idx = rx_desc->rxmcs;
5063 }
5064
5065 ieee80211_rx_irqsafe(hw, skb);
5066 skb = NULL;
5067 rx_urb->urb.context = NULL;
5068 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5069 } else {
5070 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5071 goto cleanup;
5072 }
5073 return;
5074
5075cleanup:
5076 usb_free_urb(urb);
5077 dev_kfree_skb(skb);
5078 return;
5079}
5080
5081static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5082 struct rtl8xxxu_rx_urb *rx_urb)
5083{
5084 struct sk_buff *skb;
5085 int skb_size;
5086 int ret;
5087
5088 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5089 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5090 if (!skb)
5091 return -ENOMEM;
5092
5093 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5094 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5095 skb_size, rtl8xxxu_rx_complete, skb);
5096 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5097 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5098 if (ret)
5099 usb_unanchor_urb(&rx_urb->urb);
5100 return ret;
5101}
5102
5103static void rtl8xxxu_int_complete(struct urb *urb)
5104{
5105 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5106 struct device *dev = &priv->udev->dev;
5107 int ret;
5108
5109 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5110 if (urb->status == 0) {
5111 usb_anchor_urb(urb, &priv->int_anchor);
5112 ret = usb_submit_urb(urb, GFP_ATOMIC);
5113 if (ret)
5114 usb_unanchor_urb(urb);
5115 } else {
5116 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5117 }
5118}
5119
5120
5121static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5122{
5123 struct rtl8xxxu_priv *priv = hw->priv;
5124 struct urb *urb;
5125 u32 val32;
5126 int ret;
5127
5128 urb = usb_alloc_urb(0, GFP_KERNEL);
5129 if (!urb)
5130 return -ENOMEM;
5131
5132 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5133 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5134 rtl8xxxu_int_complete, priv, 1);
5135 usb_anchor_urb(urb, &priv->int_anchor);
5136 ret = usb_submit_urb(urb, GFP_KERNEL);
5137 if (ret) {
5138 usb_unanchor_urb(urb);
5139 goto error;
5140 }
5141
5142 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5143 val32 |= USB_HIMR_CPWM;
5144 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5145
5146error:
5147 return ret;
5148}
5149
5150static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5151 struct ieee80211_vif *vif)
5152{
5153 struct rtl8xxxu_priv *priv = hw->priv;
5154 int ret;
5155 u8 val8;
5156
5157 switch (vif->type) {
5158 case NL80211_IFTYPE_STATION:
5159 rtl8723a_stop_tx_beacon(priv);
5160
5161 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5162 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5163 BEACON_DISABLE_TSF_UPDATE;
5164 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5165 ret = 0;
5166 break;
5167 default:
5168 ret = -EOPNOTSUPP;
5169 }
5170
5171 rtl8xxxu_set_linktype(priv, vif->type);
5172
5173 return ret;
5174}
5175
5176static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5177 struct ieee80211_vif *vif)
5178{
5179 struct rtl8xxxu_priv *priv = hw->priv;
5180
5181 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5182}
5183
5184static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5185{
5186 struct rtl8xxxu_priv *priv = hw->priv;
5187 struct device *dev = &priv->udev->dev;
5188 u16 val16;
5189 int ret = 0, channel;
5190 bool ht40;
5191
5192 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5193 dev_info(dev,
5194 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5195 __func__, hw->conf.chandef.chan->hw_value,
5196 changed, hw->conf.chandef.width);
5197
5198 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5199 val16 = ((hw->conf.long_frame_max_tx_count <<
5200 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5201 ((hw->conf.short_frame_max_tx_count <<
5202 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5203 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5204 }
5205
5206 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5207 switch (hw->conf.chandef.width) {
5208 case NL80211_CHAN_WIDTH_20_NOHT:
5209 case NL80211_CHAN_WIDTH_20:
5210 ht40 = false;
5211 break;
5212 case NL80211_CHAN_WIDTH_40:
5213 ht40 = true;
5214 break;
5215 default:
5216 ret = -ENOTSUPP;
5217 goto exit;
5218 }
5219
5220 channel = hw->conf.chandef.chan->hw_value;
5221
5222 rtl8723a_set_tx_power(priv, channel, ht40);
5223
5224 rtl8723au_config_channel(hw);
5225 }
5226
5227exit:
5228 return ret;
5229}
5230
5231static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5232 struct ieee80211_vif *vif, u16 queue,
5233 const struct ieee80211_tx_queue_params *param)
5234{
5235 struct rtl8xxxu_priv *priv = hw->priv;
5236 struct device *dev = &priv->udev->dev;
5237 u32 val32;
5238 u8 aifs, acm_ctrl, acm_bit;
5239
5240 aifs = param->aifs;
5241
5242 val32 = aifs |
5243 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5244 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5245 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5246
5247 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5248 dev_dbg(dev,
5249 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5250 __func__, queue, val32, param->acm, acm_ctrl);
5251
5252 switch (queue) {
5253 case IEEE80211_AC_VO:
5254 acm_bit = ACM_HW_CTRL_VO;
5255 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5256 break;
5257 case IEEE80211_AC_VI:
5258 acm_bit = ACM_HW_CTRL_VI;
5259 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5260 break;
5261 case IEEE80211_AC_BE:
5262 acm_bit = ACM_HW_CTRL_BE;
5263 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5264 break;
5265 case IEEE80211_AC_BK:
5266 acm_bit = ACM_HW_CTRL_BK;
5267 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5268 break;
5269 default:
5270 acm_bit = 0;
5271 break;
5272 }
5273
5274 if (param->acm)
5275 acm_ctrl |= acm_bit;
5276 else
5277 acm_ctrl &= ~acm_bit;
5278 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5279
5280 return 0;
5281}
5282
5283static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5284 unsigned int changed_flags,
5285 unsigned int *total_flags, u64 multicast)
5286{
5287 struct rtl8xxxu_priv *priv = hw->priv;
5288
5289 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5290 __func__, changed_flags, *total_flags);
5291
5292 *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC);
5293}
5294
5295static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5296{
5297 if (rts > 2347)
5298 return -EINVAL;
5299
5300 return 0;
5301}
5302
5303static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5304 struct ieee80211_vif *vif,
5305 struct ieee80211_sta *sta,
5306 struct ieee80211_key_conf *key)
5307{
5308 struct rtl8xxxu_priv *priv = hw->priv;
5309 struct device *dev = &priv->udev->dev;
5310 u8 mac_addr[ETH_ALEN];
5311 u8 val8;
5312 u16 val16;
5313 u32 val32;
5314 int retval = -EOPNOTSUPP;
5315
5316 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5317 __func__, cmd, key->cipher, key->keyidx);
5318
5319 if (vif->type != NL80211_IFTYPE_STATION)
5320 return -EOPNOTSUPP;
5321
5322 if (key->keyidx > 3)
5323 return -EOPNOTSUPP;
5324
5325 switch (key->cipher) {
5326 case WLAN_CIPHER_SUITE_WEP40:
5327 case WLAN_CIPHER_SUITE_WEP104:
5328
5329 break;
5330 case WLAN_CIPHER_SUITE_CCMP:
5331 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5332 break;
5333 case WLAN_CIPHER_SUITE_TKIP:
5334 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5335 default:
5336 return -EOPNOTSUPP;
5337 }
5338
5339 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5340 dev_dbg(dev, "%s: pairwise key\n", __func__);
5341 ether_addr_copy(mac_addr, sta->addr);
5342 } else {
5343 dev_dbg(dev, "%s: group key\n", __func__);
5344 eth_broadcast_addr(mac_addr);
5345 }
5346
5347 val16 = rtl8xxxu_read16(priv, REG_CR);
5348 val16 |= CR_SECURITY_ENABLE;
5349 rtl8xxxu_write16(priv, REG_CR, val16);
5350
5351 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5352 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5353 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5354 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5355
5356 switch (cmd) {
5357 case SET_KEY:
5358 key->hw_key_idx = key->keyidx;
5359 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5360 rtl8xxxu_cam_write(priv, key, mac_addr);
5361 retval = 0;
5362 break;
5363 case DISABLE_KEY:
5364 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5365 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5366 key->keyidx << CAM_CMD_KEY_SHIFT;
5367 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5368 retval = 0;
5369 break;
5370 default:
5371 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5372 }
5373
5374 return retval;
5375}
5376
5377static int
5378rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5379 enum ieee80211_ampdu_mlme_action action,
5380 struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size,
5381 bool amsdu)
5382{
5383 struct rtl8xxxu_priv *priv = hw->priv;
5384 struct device *dev = &priv->udev->dev;
5385 u8 ampdu_factor, ampdu_density;
5386
5387 switch (action) {
5388 case IEEE80211_AMPDU_TX_START:
5389 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5390 ampdu_factor = sta->ht_cap.ampdu_factor;
5391 ampdu_density = sta->ht_cap.ampdu_density;
5392 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5393 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5394 dev_dbg(dev,
5395 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5396 ampdu_factor, ampdu_density);
5397 break;
5398 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5399 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5400 rtl8xxxu_set_ampdu_factor(priv, 0);
5401 rtl8xxxu_set_ampdu_min_space(priv, 0);
5402 break;
5403 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5404 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5405 __func__);
5406 rtl8xxxu_set_ampdu_factor(priv, 0);
5407 rtl8xxxu_set_ampdu_min_space(priv, 0);
5408 break;
5409 case IEEE80211_AMPDU_RX_START:
5410 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5411 break;
5412 case IEEE80211_AMPDU_RX_STOP:
5413 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5414 break;
5415 default:
5416 break;
5417 }
5418 return 0;
5419}
5420
5421static int rtl8xxxu_start(struct ieee80211_hw *hw)
5422{
5423 struct rtl8xxxu_priv *priv = hw->priv;
5424 struct rtl8xxxu_rx_urb *rx_urb;
5425 struct rtl8xxxu_tx_urb *tx_urb;
5426 unsigned long flags;
5427 int ret, i;
5428
5429 ret = 0;
5430
5431 init_usb_anchor(&priv->rx_anchor);
5432 init_usb_anchor(&priv->tx_anchor);
5433 init_usb_anchor(&priv->int_anchor);
5434
5435 rtl8723a_enable_rf(priv);
5436 ret = rtl8xxxu_submit_int_urb(hw);
5437 if (ret)
5438 goto exit;
5439
5440 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5441 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5442 if (!tx_urb) {
5443 if (!i)
5444 ret = -ENOMEM;
5445
5446 goto error_out;
5447 }
5448 usb_init_urb(&tx_urb->urb);
5449 INIT_LIST_HEAD(&tx_urb->list);
5450 tx_urb->hw = hw;
5451 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5452 priv->tx_urb_free_count++;
5453 }
5454
5455 priv->tx_stopped = false;
5456
5457 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5458 priv->shutdown = false;
5459 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5460
5461 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5462 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5463 if (!rx_urb) {
5464 if (!i)
5465 ret = -ENOMEM;
5466
5467 goto error_out;
5468 }
5469 usb_init_urb(&rx_urb->urb);
5470 INIT_LIST_HEAD(&rx_urb->list);
5471 rx_urb->hw = hw;
5472
5473 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5474 }
5475exit:
5476 /*
5477 * Disable all data frames
5478 */
5479 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5480 /*
5481 * Accept all mgmt frames
5482 */
5483 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5484
5485 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5486
5487 return ret;
5488
5489error_out:
5490 rtl8xxxu_free_tx_resources(priv);
5491 /*
5492 * Disable all data and mgmt frames
5493 */
5494 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5495 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5496
5497 return ret;
5498}
5499
5500static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5501{
5502 struct rtl8xxxu_priv *priv = hw->priv;
5503 unsigned long flags;
5504
5505 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5506
5507 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5508 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5509
5510 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5511 priv->shutdown = true;
5512 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5513
5514 usb_kill_anchored_urbs(&priv->rx_anchor);
5515 usb_kill_anchored_urbs(&priv->tx_anchor);
5516 usb_kill_anchored_urbs(&priv->int_anchor);
5517
5518 rtl8723a_disable_rf(priv);
5519
5520 /*
5521 * Disable interrupts
5522 */
5523 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5524
5525 rtl8xxxu_free_rx_resources(priv);
5526 rtl8xxxu_free_tx_resources(priv);
5527}
5528
5529static const struct ieee80211_ops rtl8xxxu_ops = {
5530 .tx = rtl8xxxu_tx,
5531 .add_interface = rtl8xxxu_add_interface,
5532 .remove_interface = rtl8xxxu_remove_interface,
5533 .config = rtl8xxxu_config,
5534 .conf_tx = rtl8xxxu_conf_tx,
5535 .bss_info_changed = rtl8xxxu_bss_info_changed,
5536 .configure_filter = rtl8xxxu_configure_filter,
5537 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5538 .start = rtl8xxxu_start,
5539 .stop = rtl8xxxu_stop,
5540 .sw_scan_start = rtl8xxxu_sw_scan_start,
5541 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5542 .set_key = rtl8xxxu_set_key,
5543 .ampdu_action = rtl8xxxu_ampdu_action,
5544};
5545
5546static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5547 struct usb_interface *interface)
5548{
5549 struct usb_interface_descriptor *interface_desc;
5550 struct usb_host_interface *host_interface;
5551 struct usb_endpoint_descriptor *endpoint;
5552 struct device *dev = &priv->udev->dev;
5553 int i, j = 0, endpoints;
5554 u8 dir, xtype, num;
5555 int ret = 0;
5556
5557 host_interface = &interface->altsetting[0];
5558 interface_desc = &host_interface->desc;
5559 endpoints = interface_desc->bNumEndpoints;
5560
5561 for (i = 0; i < endpoints; i++) {
5562 endpoint = &host_interface->endpoint[i].desc;
5563
5564 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5565 num = usb_endpoint_num(endpoint);
5566 xtype = usb_endpoint_type(endpoint);
5567 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5568 dev_dbg(dev,
5569 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5570 __func__, dir, num, xtype);
5571 if (usb_endpoint_dir_in(endpoint) &&
5572 usb_endpoint_xfer_bulk(endpoint)) {
5573 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5574 dev_dbg(dev, "%s: in endpoint num %i\n",
5575 __func__, num);
5576
5577 if (priv->pipe_in) {
5578 dev_warn(dev,
5579 "%s: Too many IN pipes\n", __func__);
5580 ret = -EINVAL;
5581 goto exit;
5582 }
5583
5584 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5585 }
5586
5587 if (usb_endpoint_dir_in(endpoint) &&
5588 usb_endpoint_xfer_int(endpoint)) {
5589 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5590 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5591 __func__, num);
5592
5593 if (priv->pipe_interrupt) {
5594 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5595 __func__);
5596 ret = -EINVAL;
5597 goto exit;
5598 }
5599
5600 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5601 }
5602
5603 if (usb_endpoint_dir_out(endpoint) &&
5604 usb_endpoint_xfer_bulk(endpoint)) {
5605 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5606 dev_dbg(dev, "%s: out endpoint num %i\n",
5607 __func__, num);
5608 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5609 dev_warn(dev,
5610 "%s: Too many OUT pipes\n", __func__);
5611 ret = -EINVAL;
5612 goto exit;
5613 }
5614 priv->out_ep[j++] = num;
5615 }
5616 }
5617exit:
5618 priv->nr_out_eps = j;
5619 return ret;
5620}
5621
5622static int rtl8xxxu_probe(struct usb_interface *interface,
5623 const struct usb_device_id *id)
5624{
5625 struct rtl8xxxu_priv *priv;
5626 struct ieee80211_hw *hw;
5627 struct usb_device *udev;
5628 struct ieee80211_supported_band *sband;
5629 int ret = 0;
5630 int untested = 1;
5631
5632 udev = usb_get_dev(interface_to_usbdev(interface));
5633
5634 switch (id->idVendor) {
5635 case USB_VENDOR_ID_REALTEK:
5636 switch(id->idProduct) {
5637 case 0x1724:
5638 case 0x8176:
5639 case 0x8178:
5640 case 0x817f:
5641 untested = 0;
5642 break;
5643 }
5644 break;
5645 case 0x7392:
5646 if (id->idProduct == 0x7811)
5647 untested = 0;
5648 break;
5649 default:
5650 break;
5651 }
5652
5653 if (untested) {
5654 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5655 dev_info(&udev->dev,
5656 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5657 id->idVendor, id->idProduct);
5658 dev_info(&udev->dev,
5659 "Please report results to Jes.Sorensen@gmail.com\n");
5660 }
5661
5662 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5663 if (!hw) {
5664 ret = -ENOMEM;
5665 goto exit;
5666 }
5667
5668 priv = hw->priv;
5669 priv->hw = hw;
5670 priv->udev = udev;
5671 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5672 mutex_init(&priv->usb_buf_mutex);
5673 mutex_init(&priv->h2c_mutex);
5674 INIT_LIST_HEAD(&priv->tx_urb_free_list);
5675 spin_lock_init(&priv->tx_urb_lock);
5676 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5677 spin_lock_init(&priv->rx_urb_lock);
5678 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5679
5680 usb_set_intfdata(interface, hw);
5681
5682 ret = rtl8xxxu_parse_usb(priv, interface);
5683 if (ret)
5684 goto exit;
5685
5686 ret = rtl8xxxu_identify_chip(priv);
5687 if (ret) {
5688 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5689 goto exit;
5690 }
5691
5692 ret = rtl8xxxu_read_efuse(priv);
5693 if (ret) {
5694 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5695 goto exit;
5696 }
5697
5698 ret = priv->fops->parse_efuse(priv);
5699 if (ret) {
5700 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5701 goto exit;
5702 }
5703
5704 rtl8xxxu_print_chipinfo(priv);
5705
5706 ret = priv->fops->load_firmware(priv);
5707 if (ret) {
5708 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5709 goto exit;
5710 }
5711
5712 ret = rtl8xxxu_init_device(hw);
5713
5714 hw->wiphy->max_scan_ssids = 1;
5715 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5716 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5717 hw->queues = 4;
5718
5719 sband = &rtl8xxxu_supported_band;
5720 sband->ht_cap.ht_supported = true;
5721 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5722 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5723 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5724 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5725 sband->ht_cap.mcs.rx_mask[0] = 0xff;
5726 sband->ht_cap.mcs.rx_mask[4] = 0x01;
5727 if (priv->rf_paths > 1) {
5728 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5729 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5730 }
5731 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5732 /*
5733 * Some APs will negotiate HT20_40 in a noisy environment leading
5734 * to miserable performance. Rather than defaulting to this, only
5735 * enable it if explicitly requested at module load time.
5736 */
5737 if (rtl8xxxu_ht40_2g) {
5738 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5739 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5740 }
5741 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5742
5743 hw->wiphy->rts_threshold = 2347;
5744
5745 SET_IEEE80211_DEV(priv->hw, &interface->dev);
5746 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5747
5748 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5749 ieee80211_hw_set(hw, SIGNAL_DBM);
5750 /*
5751 * The firmware handles rate control
5752 */
5753 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5754 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5755
5756 ret = ieee80211_register_hw(priv->hw);
5757 if (ret) {
5758 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5759 __func__, ret);
5760 goto exit;
5761 }
5762
5763exit:
5764 if (ret < 0)
5765 usb_put_dev(udev);
5766 return ret;
5767}
5768
5769static void rtl8xxxu_disconnect(struct usb_interface *interface)
5770{
5771 struct rtl8xxxu_priv *priv;
5772 struct ieee80211_hw *hw;
5773
5774 hw = usb_get_intfdata(interface);
5775 priv = hw->priv;
5776
5777 rtl8xxxu_disable_device(hw);
5778 usb_set_intfdata(interface, NULL);
5779
5780 dev_info(&priv->udev->dev, "disconnecting\n");
5781
5782 ieee80211_unregister_hw(hw);
5783
5784 kfree(priv->fw_data);
5785 mutex_destroy(&priv->usb_buf_mutex);
5786 mutex_destroy(&priv->h2c_mutex);
5787
5788 usb_put_dev(priv->udev);
5789 ieee80211_free_hw(hw);
5790}
5791
5792static struct rtl8xxxu_fileops rtl8723au_fops = {
5793 .parse_efuse = rtl8723au_parse_efuse,
5794 .load_firmware = rtl8723au_load_firmware,
5795 .power_on = rtl8723au_power_on,
5796 .writeN_block_size = 1024,
5797};
5798
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5799#ifdef CONFIG_RTL8XXXU_UNTESTED
5800
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5801static struct rtl8xxxu_fileops rtl8192cu_fops = {
5802 .parse_efuse = rtl8192cu_parse_efuse,
5803 .load_firmware = rtl8192cu_load_firmware,
5804 .power_on = rtl8192cu_power_on,
5805 .writeN_block_size = 128,
5806};
5807
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5808#endif
5809
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5810static struct usb_device_id dev_table[] = {
5811{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5812 .driver_info = (unsigned long)&rtl8723au_fops},
5813{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5814 .driver_info = (unsigned long)&rtl8723au_fops},
5815{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5816 .driver_info = (unsigned long)&rtl8723au_fops},
Kalle Valo033695b2015-10-23 20:27:58 +0300[diff] [blame]5817#ifdef CONFIG_RTL8XXXU_UNTESTED
5818/* Still supported by rtlwifi */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5819{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5820 .driver_info = (unsigned long)&rtl8192cu_fops},
5821{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5822 .driver_info = (unsigned long)&rtl8192cu_fops},
5823{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5824 .driver_info = (unsigned long)&rtl8192cu_fops},
5825/* Tested by Larry Finger */
5826{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5827 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5828/* Currently untested 8188 series devices */
5829{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5830 .driver_info = (unsigned long)&rtl8192cu_fops},
5831{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5832 .driver_info = (unsigned long)&rtl8192cu_fops},
5833{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5834 .driver_info = (unsigned long)&rtl8192cu_fops},
5835{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5836 .driver_info = (unsigned long)&rtl8192cu_fops},
5837{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5838 .driver_info = (unsigned long)&rtl8192cu_fops},
5839{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5840 .driver_info = (unsigned long)&rtl8192cu_fops},
5841{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5842 .driver_info = (unsigned long)&rtl8192cu_fops},
5843{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5844 .driver_info = (unsigned long)&rtl8192cu_fops},
5845{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5846 .driver_info = (unsigned long)&rtl8192cu_fops},
5847{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5848 .driver_info = (unsigned long)&rtl8192cu_fops},
5849{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5850 .driver_info = (unsigned long)&rtl8192cu_fops},
5851{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5852 .driver_info = (unsigned long)&rtl8192cu_fops},
5853{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5854 .driver_info = (unsigned long)&rtl8192cu_fops},
5855{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5856 .driver_info = (unsigned long)&rtl8192cu_fops},
5857{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5858 .driver_info = (unsigned long)&rtl8192cu_fops},
5859{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5860 .driver_info = (unsigned long)&rtl8192cu_fops},
5861{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5862 .driver_info = (unsigned long)&rtl8192cu_fops},
5863{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5864 .driver_info = (unsigned long)&rtl8192cu_fops},
5865{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5866 .driver_info = (unsigned long)&rtl8192cu_fops},
5867{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5868 .driver_info = (unsigned long)&rtl8192cu_fops},
5869{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5870 .driver_info = (unsigned long)&rtl8192cu_fops},
5871{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5872 .driver_info = (unsigned long)&rtl8192cu_fops},
5873{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5874 .driver_info = (unsigned long)&rtl8192cu_fops},
5875{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5876 .driver_info = (unsigned long)&rtl8192cu_fops},
5877{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5878 .driver_info = (unsigned long)&rtl8192cu_fops},
5879{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5880 .driver_info = (unsigned long)&rtl8192cu_fops},
5881{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5882 .driver_info = (unsigned long)&rtl8192cu_fops},
5883{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5884 .driver_info = (unsigned long)&rtl8192cu_fops},
5885{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5886 .driver_info = (unsigned long)&rtl8192cu_fops},
5887{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5888 .driver_info = (unsigned long)&rtl8192cu_fops},
5889{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5890 .driver_info = (unsigned long)&rtl8192cu_fops},
5891{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5892 .driver_info = (unsigned long)&rtl8192cu_fops},
5893{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5894 .driver_info = (unsigned long)&rtl8192cu_fops},
5895{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5896 .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */
5897{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5898 .driver_info = (unsigned long)&rtl8192cu_fops},
5899{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5900 .driver_info = (unsigned long)&rtl8192cu_fops},
5901{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5902 .driver_info = (unsigned long)&rtl8192cu_fops},
5903{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5904 .driver_info = (unsigned long)&rtl8192cu_fops},
5905{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5906 .driver_info = (unsigned long)&rtl8192cu_fops},
5907{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5908 .driver_info = (unsigned long)&rtl8192cu_fops},
5909{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5910 .driver_info = (unsigned long)&rtl8192cu_fops},
5911/* Currently untested 8192 series devices */
5912{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5913 .driver_info = (unsigned long)&rtl8192cu_fops},
5914{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5915 .driver_info = (unsigned long)&rtl8192cu_fops},
5916{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5917 .driver_info = (unsigned long)&rtl8192cu_fops},
5918{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5919 .driver_info = (unsigned long)&rtl8192cu_fops},
5920{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5921 .driver_info = (unsigned long)&rtl8192cu_fops},
5922{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5923 .driver_info = (unsigned long)&rtl8192cu_fops},
5924{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5925 .driver_info = (unsigned long)&rtl8192cu_fops},
5926{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5927 .driver_info = (unsigned long)&rtl8192cu_fops},
5928{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5929 .driver_info = (unsigned long)&rtl8192cu_fops},
5930{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5931 .driver_info = (unsigned long)&rtl8192cu_fops},
5932{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5933 .driver_info = (unsigned long)&rtl8192cu_fops},
5934{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5935 .driver_info = (unsigned long)&rtl8192cu_fops},
5936{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5937 .driver_info = (unsigned long)&rtl8192cu_fops},
5938{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5939 .driver_info = (unsigned long)&rtl8192cu_fops},
5940{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5941 .driver_info = (unsigned long)&rtl8192cu_fops},
5942{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5943 .driver_info = (unsigned long)&rtl8192cu_fops},
5944{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5945 .driver_info = (unsigned long)&rtl8192cu_fops},
5946{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
5947 .driver_info = (unsigned long)&rtl8192cu_fops},
5948{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
5949 .driver_info = (unsigned long)&rtl8192cu_fops},
5950{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
5951 .driver_info = (unsigned long)&rtl8192cu_fops},
5952{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
5953 .driver_info = (unsigned long)&rtl8192cu_fops},
5954{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
5955 .driver_info = (unsigned long)&rtl8192cu_fops},
5956{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
5957 .driver_info = (unsigned long)&rtl8192cu_fops},
5958{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
5959 .driver_info = (unsigned long)&rtl8192cu_fops},
5960{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
5961 .driver_info = (unsigned long)&rtl8192cu_fops},
5962#endif
5963{ }
5964};
5965
5966static struct usb_driver rtl8xxxu_driver = {
5967 .name = DRIVER_NAME,
5968 .probe = rtl8xxxu_probe,
5969 .disconnect = rtl8xxxu_disconnect,
5970 .id_table = dev_table,
5971 .disable_hub_initiated_lpm = 1,
5972};
5973
5974static int __init rtl8xxxu_module_init(void)
5975{
5976 int res;
5977
5978 res = usb_register(&rtl8xxxu_driver);
5979 if (res < 0)
5980 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
5981
5982 return res;
5983}
5984
5985static void __exit rtl8xxxu_module_exit(void)
5986{
5987 usb_deregister(&rtl8xxxu_driver);
5988}
5989
5990
5991MODULE_DEVICE_TABLE(usb, dev_table);
5992
5993module_init(rtl8xxxu_module_init);
5994module_exit(rtl8xxxu_module_exit);