Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree Source for AM4372 SoC |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public License |
| 7 | * version 2. This program is licensed "as is" without any warranty of any |
| 8 | * kind, whether express or implied. |
| 9 | */ |
| 10 | |
Balaji T K | d2885db | 2014-03-03 20:20:20 +0530 | [diff] [blame] | 11 | #include <dt-bindings/gpio/gpio.h> |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 13 | |
| 14 | #include "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | compatible = "ti,am4372", "ti,am43"; |
| 18 | interrupt-parent = <&gic>; |
| 19 | |
| 20 | |
| 21 | aliases { |
Nishanth Menon | 6a96867 | 2013-10-16 15:21:04 -0500 | [diff] [blame] | 22 | i2c0 = &i2c0; |
| 23 | i2c1 = &i2c1; |
| 24 | i2c2 = &i2c2; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 25 | serial0 = &uart0; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 26 | ethernet0 = &cpsw_emac0; |
| 27 | ethernet1 = &cpsw_emac1; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | cpus { |
Afzal Mohammed | 738c740 | 2013-08-02 19:16:13 +0530 | [diff] [blame] | 31 | #address-cells = <1>; |
| 32 | #size-cells = <0>; |
Felipe Balbi | 08ecb28 | 2014-06-23 13:20:58 -0500 | [diff] [blame] | 33 | cpu: cpu@0 { |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 34 | compatible = "arm,cortex-a9"; |
Afzal Mohammed | 738c740 | 2013-08-02 19:16:13 +0530 | [diff] [blame] | 35 | device_type = "cpu"; |
| 36 | reg = <0>; |
Nishanth Menon | 8d766fa | 2014-01-29 12:19:17 -0600 | [diff] [blame] | 37 | |
| 38 | clocks = <&dpll_mpu_ck>; |
| 39 | clock-names = "cpu"; |
| 40 | |
| 41 | clock-latency = <300000>; /* From omap-cpufreq driver */ |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 42 | }; |
| 43 | }; |
| 44 | |
| 45 | gic: interrupt-controller@48241000 { |
| 46 | compatible = "arm,cortex-a9-gic"; |
| 47 | interrupt-controller; |
| 48 | #interrupt-cells = <3>; |
| 49 | reg = <0x48241000 0x1000>, |
| 50 | <0x48240100 0x0100>; |
| 51 | }; |
| 52 | |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 53 | l2-cache-controller@48242000 { |
| 54 | compatible = "arm,pl310-cache"; |
| 55 | reg = <0x48242000 0x1000>; |
| 56 | cache-unified; |
| 57 | cache-level = <2>; |
| 58 | }; |
| 59 | |
| 60 | am43xx_pinmux: pinmux@44e10800 { |
Nishanth Menon | d8c5bab | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 61 | compatible = "ti,am437-padconf", "pinctrl-single"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 62 | reg = <0x44e10800 0x31c>; |
| 63 | #address-cells = <1>; |
| 64 | #size-cells = <0>; |
Nishanth Menon | d8c5bab | 2014-05-22 23:47:46 -0500 | [diff] [blame] | 65 | #interrupt-cells = <1>; |
| 66 | interrupt-controller; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 67 | pinctrl-single,register-width = <32>; |
| 68 | pinctrl-single,function-mask = <0xffffffff>; |
| 69 | }; |
| 70 | |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 71 | ocp { |
Afzal Mohammed | 2eeddb8 | 2013-12-02 17:48:57 +0530 | [diff] [blame] | 72 | compatible = "ti,am4372-l3-noc", "simple-bus"; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 73 | #address-cells = <1>; |
| 74 | #size-cells = <1>; |
| 75 | ranges; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 76 | ti,hwmods = "l3_main"; |
Afzal Mohammed | 2eeddb8 | 2013-12-02 17:48:57 +0530 | [diff] [blame] | 77 | reg = <0x44000000 0x400000 |
| 78 | 0x44800000 0x400000>; |
| 79 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 81 | |
Tero Kristo | 6a67920 | 2013-08-02 19:12:04 +0300 | [diff] [blame] | 82 | prcm: prcm@44df0000 { |
| 83 | compatible = "ti,am4-prcm"; |
| 84 | reg = <0x44df0000 0x11000>; |
| 85 | |
| 86 | prcm_clocks: clocks { |
| 87 | #address-cells = <1>; |
| 88 | #size-cells = <0>; |
| 89 | }; |
| 90 | |
| 91 | prcm_clockdomains: clockdomains { |
| 92 | }; |
| 93 | }; |
| 94 | |
| 95 | scrm: scrm@44e10000 { |
| 96 | compatible = "ti,am4-scrm"; |
| 97 | reg = <0x44e10000 0x2000>; |
| 98 | |
| 99 | scrm_clocks: clocks { |
| 100 | #address-cells = <1>; |
| 101 | #size-cells = <0>; |
| 102 | }; |
| 103 | |
| 104 | scrm_clockdomains: clockdomains { |
| 105 | }; |
| 106 | }; |
| 107 | |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 108 | edma: edma@49000000 { |
| 109 | compatible = "ti,edma3"; |
| 110 | ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; |
| 111 | reg = <0x49000000 0x10000>, |
| 112 | <0x44e10f90 0x10>; |
| 113 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 114 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 115 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| 116 | #dma-cells = <1>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 117 | }; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 118 | |
| 119 | uart0: serial@44e09000 { |
| 120 | compatible = "ti,am4372-uart","ti,omap2-uart"; |
| 121 | reg = <0x44e09000 0x2000>; |
| 122 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 123 | ti,hwmods = "uart1"; |
| 124 | }; |
| 125 | |
| 126 | uart1: serial@48022000 { |
| 127 | compatible = "ti,am4372-uart","ti,omap2-uart"; |
| 128 | reg = <0x48022000 0x2000>; |
| 129 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 130 | ti,hwmods = "uart2"; |
| 131 | status = "disabled"; |
| 132 | }; |
| 133 | |
| 134 | uart2: serial@48024000 { |
| 135 | compatible = "ti,am4372-uart","ti,omap2-uart"; |
| 136 | reg = <0x48024000 0x2000>; |
| 137 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 138 | ti,hwmods = "uart3"; |
| 139 | status = "disabled"; |
| 140 | }; |
| 141 | |
| 142 | uart3: serial@481a6000 { |
| 143 | compatible = "ti,am4372-uart","ti,omap2-uart"; |
| 144 | reg = <0x481a6000 0x2000>; |
| 145 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
| 146 | ti,hwmods = "uart4"; |
| 147 | status = "disabled"; |
| 148 | }; |
| 149 | |
| 150 | uart4: serial@481a8000 { |
| 151 | compatible = "ti,am4372-uart","ti,omap2-uart"; |
| 152 | reg = <0x481a8000 0x2000>; |
| 153 | interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| 154 | ti,hwmods = "uart5"; |
| 155 | status = "disabled"; |
| 156 | }; |
| 157 | |
| 158 | uart5: serial@481aa000 { |
| 159 | compatible = "ti,am4372-uart","ti,omap2-uart"; |
| 160 | reg = <0x481aa000 0x2000>; |
| 161 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 162 | ti,hwmods = "uart6"; |
| 163 | status = "disabled"; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 164 | }; |
| 165 | |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 166 | mailbox: mailbox@480C8000 { |
| 167 | compatible = "ti,omap4-mailbox"; |
| 168 | reg = <0x480C8000 0x200>; |
| 169 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
| 170 | ti,hwmods = "mailbox"; |
| 171 | ti,mbox-num-users = <4>; |
| 172 | ti,mbox-num-fifos = <8>; |
Suman Anna | d27704d | 2014-09-10 14:27:23 -0500 | [diff] [blame] | 173 | mbox_wkupm3: wkup_m3 { |
| 174 | ti,mbox-tx = <0 0 0>; |
| 175 | ti,mbox-rx = <0 0 3>; |
| 176 | }; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 177 | }; |
| 178 | |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 179 | timer1: timer@44e31000 { |
| 180 | compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; |
| 181 | reg = <0x44e31000 0x400>; |
| 182 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| 183 | ti,timer-alwon; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 184 | ti,hwmods = "timer1"; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | timer2: timer@48040000 { |
| 188 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 189 | reg = <0x48040000 0x400>; |
| 190 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 191 | ti,hwmods = "timer2"; |
| 192 | }; |
| 193 | |
| 194 | timer3: timer@48042000 { |
| 195 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 196 | reg = <0x48042000 0x400>; |
| 197 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| 198 | ti,hwmods = "timer3"; |
| 199 | status = "disabled"; |
| 200 | }; |
| 201 | |
| 202 | timer4: timer@48044000 { |
| 203 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 204 | reg = <0x48044000 0x400>; |
| 205 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 206 | ti,timer-pwm; |
| 207 | ti,hwmods = "timer4"; |
| 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | timer5: timer@48046000 { |
| 212 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 213 | reg = <0x48046000 0x400>; |
| 214 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | ti,timer-pwm; |
| 216 | ti,hwmods = "timer5"; |
| 217 | status = "disabled"; |
| 218 | }; |
| 219 | |
| 220 | timer6: timer@48048000 { |
| 221 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 222 | reg = <0x48048000 0x400>; |
| 223 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 224 | ti,timer-pwm; |
| 225 | ti,hwmods = "timer6"; |
| 226 | status = "disabled"; |
| 227 | }; |
| 228 | |
| 229 | timer7: timer@4804a000 { |
| 230 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 231 | reg = <0x4804a000 0x400>; |
| 232 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| 233 | ti,timer-pwm; |
| 234 | ti,hwmods = "timer7"; |
| 235 | status = "disabled"; |
| 236 | }; |
| 237 | |
| 238 | timer8: timer@481c1000 { |
| 239 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 240 | reg = <0x481c1000 0x400>; |
| 241 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| 242 | ti,hwmods = "timer8"; |
| 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
| 246 | timer9: timer@4833d000 { |
| 247 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 248 | reg = <0x4833d000 0x400>; |
| 249 | interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; |
| 250 | ti,hwmods = "timer9"; |
| 251 | status = "disabled"; |
| 252 | }; |
| 253 | |
| 254 | timer10: timer@4833f000 { |
| 255 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 256 | reg = <0x4833f000 0x400>; |
| 257 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| 258 | ti,hwmods = "timer10"; |
| 259 | status = "disabled"; |
| 260 | }; |
| 261 | |
| 262 | timer11: timer@48341000 { |
| 263 | compatible = "ti,am4372-timer","ti,am335x-timer"; |
| 264 | reg = <0x48341000 0x400>; |
| 265 | interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| 266 | ti,hwmods = "timer11"; |
| 267 | status = "disabled"; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 268 | }; |
| 269 | |
| 270 | counter32k: counter@44e86000 { |
| 271 | compatible = "ti,am4372-counter32k","ti,omap-counter32k"; |
| 272 | reg = <0x44e86000 0x40>; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 273 | ti,hwmods = "counter_32k"; |
| 274 | }; |
| 275 | |
Felipe Balbi | 08ecb28 | 2014-06-23 13:20:58 -0500 | [diff] [blame] | 276 | rtc: rtc@44e3e000 { |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 277 | compatible = "ti,am4372-rtc","ti,da830-rtc"; |
| 278 | reg = <0x44e3e000 0x1000>; |
| 279 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH |
| 280 | GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| 281 | ti,hwmods = "rtc"; |
| 282 | status = "disabled"; |
| 283 | }; |
| 284 | |
Felipe Balbi | 08ecb28 | 2014-06-23 13:20:58 -0500 | [diff] [blame] | 285 | wdt: wdt@44e35000 { |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 286 | compatible = "ti,am4372-wdt","ti,omap3-wdt"; |
| 287 | reg = <0x44e35000 0x1000>; |
| 288 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
| 289 | ti,hwmods = "wd_timer2"; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | gpio0: gpio@44e07000 { |
| 293 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| 294 | reg = <0x44e07000 0x1000>; |
| 295 | interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 296 | gpio-controller; |
| 297 | #gpio-cells = <2>; |
| 298 | interrupt-controller; |
| 299 | #interrupt-cells = <2>; |
| 300 | ti,hwmods = "gpio1"; |
| 301 | status = "disabled"; |
| 302 | }; |
| 303 | |
| 304 | gpio1: gpio@4804c000 { |
| 305 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| 306 | reg = <0x4804c000 0x1000>; |
| 307 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 308 | gpio-controller; |
| 309 | #gpio-cells = <2>; |
| 310 | interrupt-controller; |
| 311 | #interrupt-cells = <2>; |
| 312 | ti,hwmods = "gpio2"; |
| 313 | status = "disabled"; |
| 314 | }; |
| 315 | |
| 316 | gpio2: gpio@481ac000 { |
| 317 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| 318 | reg = <0x481ac000 0x1000>; |
| 319 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 320 | gpio-controller; |
| 321 | #gpio-cells = <2>; |
| 322 | interrupt-controller; |
| 323 | #interrupt-cells = <2>; |
| 324 | ti,hwmods = "gpio3"; |
| 325 | status = "disabled"; |
| 326 | }; |
| 327 | |
| 328 | gpio3: gpio@481ae000 { |
| 329 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| 330 | reg = <0x481ae000 0x1000>; |
| 331 | interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| 332 | gpio-controller; |
| 333 | #gpio-cells = <2>; |
| 334 | interrupt-controller; |
| 335 | #interrupt-cells = <2>; |
| 336 | ti,hwmods = "gpio4"; |
| 337 | status = "disabled"; |
| 338 | }; |
| 339 | |
| 340 | gpio4: gpio@48320000 { |
| 341 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| 342 | reg = <0x48320000 0x1000>; |
| 343 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 344 | gpio-controller; |
| 345 | #gpio-cells = <2>; |
| 346 | interrupt-controller; |
| 347 | #interrupt-cells = <2>; |
| 348 | ti,hwmods = "gpio5"; |
| 349 | status = "disabled"; |
| 350 | }; |
| 351 | |
| 352 | gpio5: gpio@48322000 { |
| 353 | compatible = "ti,am4372-gpio","ti,omap4-gpio"; |
| 354 | reg = <0x48322000 0x1000>; |
| 355 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| 356 | gpio-controller; |
| 357 | #gpio-cells = <2>; |
| 358 | interrupt-controller; |
| 359 | #interrupt-cells = <2>; |
| 360 | ti,hwmods = "gpio6"; |
| 361 | status = "disabled"; |
| 362 | }; |
| 363 | |
Suman Anna | fd4a8a6 | 2014-01-13 18:26:47 -0600 | [diff] [blame] | 364 | hwspinlock: spinlock@480ca000 { |
| 365 | compatible = "ti,omap4-hwspinlock"; |
| 366 | reg = <0x480ca000 0x1000>; |
| 367 | ti,hwmods = "spinlock"; |
| 368 | #hwlock-cells = <1>; |
| 369 | }; |
| 370 | |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 371 | i2c0: i2c@44e0b000 { |
| 372 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| 373 | reg = <0x44e0b000 0x1000>; |
| 374 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 375 | ti,hwmods = "i2c1"; |
| 376 | #address-cells = <1>; |
| 377 | #size-cells = <0>; |
| 378 | status = "disabled"; |
| 379 | }; |
| 380 | |
| 381 | i2c1: i2c@4802a000 { |
| 382 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| 383 | reg = <0x4802a000 0x1000>; |
| 384 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 385 | ti,hwmods = "i2c2"; |
| 386 | #address-cells = <1>; |
| 387 | #size-cells = <0>; |
| 388 | status = "disabled"; |
| 389 | }; |
| 390 | |
| 391 | i2c2: i2c@4819c000 { |
| 392 | compatible = "ti,am4372-i2c","ti,omap4-i2c"; |
| 393 | reg = <0x4819c000 0x1000>; |
| 394 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 395 | ti,hwmods = "i2c3"; |
| 396 | #address-cells = <1>; |
| 397 | #size-cells = <0>; |
| 398 | status = "disabled"; |
| 399 | }; |
| 400 | |
| 401 | spi0: spi@48030000 { |
| 402 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| 403 | reg = <0x48030000 0x400>; |
| 404 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| 405 | ti,hwmods = "spi0"; |
| 406 | #address-cells = <1>; |
| 407 | #size-cells = <0>; |
| 408 | status = "disabled"; |
| 409 | }; |
| 410 | |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 411 | mmc1: mmc@48060000 { |
| 412 | compatible = "ti,omap4-hsmmc"; |
| 413 | reg = <0x48060000 0x1000>; |
| 414 | ti,hwmods = "mmc1"; |
| 415 | ti,dual-volt; |
| 416 | ti,needs-special-reset; |
| 417 | dmas = <&edma 24 |
| 418 | &edma 25>; |
| 419 | dma-names = "tx", "rx"; |
| 420 | interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| 421 | status = "disabled"; |
| 422 | }; |
| 423 | |
| 424 | mmc2: mmc@481d8000 { |
| 425 | compatible = "ti,omap4-hsmmc"; |
| 426 | reg = <0x481d8000 0x1000>; |
| 427 | ti,hwmods = "mmc2"; |
| 428 | ti,needs-special-reset; |
| 429 | dmas = <&edma 2 |
| 430 | &edma 3>; |
| 431 | dma-names = "tx", "rx"; |
| 432 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| 433 | status = "disabled"; |
| 434 | }; |
| 435 | |
| 436 | mmc3: mmc@47810000 { |
| 437 | compatible = "ti,omap4-hsmmc"; |
| 438 | reg = <0x47810000 0x1000>; |
| 439 | ti,hwmods = "mmc3"; |
| 440 | ti,needs-special-reset; |
| 441 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| 442 | status = "disabled"; |
| 443 | }; |
| 444 | |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 445 | spi1: spi@481a0000 { |
| 446 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| 447 | reg = <0x481a0000 0x400>; |
| 448 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| 449 | ti,hwmods = "spi1"; |
| 450 | #address-cells = <1>; |
| 451 | #size-cells = <0>; |
| 452 | status = "disabled"; |
| 453 | }; |
| 454 | |
| 455 | spi2: spi@481a2000 { |
| 456 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| 457 | reg = <0x481a2000 0x400>; |
| 458 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 459 | ti,hwmods = "spi2"; |
| 460 | #address-cells = <1>; |
| 461 | #size-cells = <0>; |
| 462 | status = "disabled"; |
| 463 | }; |
| 464 | |
| 465 | spi3: spi@481a4000 { |
| 466 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| 467 | reg = <0x481a4000 0x400>; |
| 468 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 469 | ti,hwmods = "spi3"; |
| 470 | #address-cells = <1>; |
| 471 | #size-cells = <0>; |
| 472 | status = "disabled"; |
| 473 | }; |
| 474 | |
| 475 | spi4: spi@48345000 { |
| 476 | compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; |
| 477 | reg = <0x48345000 0x400>; |
| 478 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| 479 | ti,hwmods = "spi4"; |
| 480 | #address-cells = <1>; |
| 481 | #size-cells = <0>; |
| 482 | status = "disabled"; |
| 483 | }; |
| 484 | |
| 485 | mac: ethernet@4a100000 { |
| 486 | compatible = "ti,am4372-cpsw","ti,cpsw"; |
| 487 | reg = <0x4a100000 0x800 |
| 488 | 0x4a101200 0x100>; |
| 489 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH |
| 490 | GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH |
| 491 | GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH |
| 492 | GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 493 | #address-cells = <1>; |
| 494 | #size-cells = <1>; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 495 | ti,hwmods = "cpgmac0"; |
George Cherian | de21b26 | 2014-05-02 12:02:04 +0530 | [diff] [blame] | 496 | clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; |
| 497 | clock-names = "fck", "cpts"; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 498 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 499 | cpdma_channels = <8>; |
| 500 | ale_entries = <1024>; |
| 501 | bd_ram_size = <0x2000>; |
| 502 | no_bd_ram = <0>; |
| 503 | rx_descs = <64>; |
| 504 | mac_control = <0x20>; |
| 505 | slaves = <2>; |
| 506 | active_slave = <0>; |
| 507 | cpts_clock_mult = <0x80000000>; |
| 508 | cpts_clock_shift = <29>; |
| 509 | ranges; |
| 510 | |
| 511 | davinci_mdio: mdio@4a101000 { |
| 512 | compatible = "ti,am4372-mdio","ti,davinci_mdio"; |
| 513 | reg = <0x4a101000 0x100>; |
| 514 | #address-cells = <1>; |
| 515 | #size-cells = <0>; |
| 516 | ti,hwmods = "davinci_mdio"; |
| 517 | bus_freq = <1000000>; |
| 518 | status = "disabled"; |
| 519 | }; |
| 520 | |
| 521 | cpsw_emac0: slave@4a100200 { |
| 522 | /* Filled in by U-Boot */ |
| 523 | mac-address = [ 00 00 00 00 00 00 ]; |
| 524 | }; |
| 525 | |
| 526 | cpsw_emac1: slave@4a100300 { |
| 527 | /* Filled in by U-Boot */ |
| 528 | mac-address = [ 00 00 00 00 00 00 ]; |
| 529 | }; |
Mugunthan V N | a9682cf | 2014-05-13 14:14:30 +0530 | [diff] [blame] | 530 | |
| 531 | phy_sel: cpsw-phy-sel@44e10650 { |
| 532 | compatible = "ti,am43xx-cpsw-phy-sel"; |
| 533 | reg= <0x44e10650 0x4>; |
| 534 | reg-names = "gmii-sel"; |
| 535 | }; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 536 | }; |
| 537 | |
| 538 | epwmss0: epwmss@48300000 { |
| 539 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| 540 | reg = <0x48300000 0x10>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 541 | #address-cells = <1>; |
| 542 | #size-cells = <1>; |
| 543 | ranges; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 544 | ti,hwmods = "epwmss0"; |
| 545 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 546 | |
| 547 | ecap0: ecap@48300100 { |
| 548 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 549 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 550 | reg = <0x48300100 0x80>; |
| 551 | ti,hwmods = "ecap0"; |
| 552 | status = "disabled"; |
| 553 | }; |
| 554 | |
| 555 | ehrpwm0: ehrpwm@48300200 { |
| 556 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 557 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 558 | reg = <0x48300200 0x80>; |
| 559 | ti,hwmods = "ehrpwm0"; |
| 560 | status = "disabled"; |
| 561 | }; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 562 | }; |
| 563 | |
| 564 | epwmss1: epwmss@48302000 { |
| 565 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| 566 | reg = <0x48302000 0x10>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 567 | #address-cells = <1>; |
| 568 | #size-cells = <1>; |
| 569 | ranges; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 570 | ti,hwmods = "epwmss1"; |
| 571 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 572 | |
| 573 | ecap1: ecap@48302100 { |
| 574 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 575 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 576 | reg = <0x48302100 0x80>; |
| 577 | ti,hwmods = "ecap1"; |
| 578 | status = "disabled"; |
| 579 | }; |
| 580 | |
| 581 | ehrpwm1: ehrpwm@48302200 { |
| 582 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 583 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 584 | reg = <0x48302200 0x80>; |
| 585 | ti,hwmods = "ehrpwm1"; |
| 586 | status = "disabled"; |
| 587 | }; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 588 | }; |
| 589 | |
| 590 | epwmss2: epwmss@48304000 { |
| 591 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| 592 | reg = <0x48304000 0x10>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 593 | #address-cells = <1>; |
| 594 | #size-cells = <1>; |
| 595 | ranges; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 596 | ti,hwmods = "epwmss2"; |
| 597 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 598 | |
| 599 | ecap2: ecap@48304100 { |
| 600 | compatible = "ti,am4372-ecap","ti,am33xx-ecap"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 601 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 602 | reg = <0x48304100 0x80>; |
| 603 | ti,hwmods = "ecap2"; |
| 604 | status = "disabled"; |
| 605 | }; |
| 606 | |
| 607 | ehrpwm2: ehrpwm@48304200 { |
| 608 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 609 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 610 | reg = <0x48304200 0x80>; |
| 611 | ti,hwmods = "ehrpwm2"; |
| 612 | status = "disabled"; |
| 613 | }; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 614 | }; |
| 615 | |
| 616 | epwmss3: epwmss@48306000 { |
| 617 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| 618 | reg = <0x48306000 0x10>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 619 | #address-cells = <1>; |
| 620 | #size-cells = <1>; |
| 621 | ranges; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 622 | ti,hwmods = "epwmss3"; |
| 623 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 624 | |
| 625 | ehrpwm3: ehrpwm@48306200 { |
| 626 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 627 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 628 | reg = <0x48306200 0x80>; |
| 629 | ti,hwmods = "ehrpwm3"; |
| 630 | status = "disabled"; |
| 631 | }; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 632 | }; |
| 633 | |
| 634 | epwmss4: epwmss@48308000 { |
| 635 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| 636 | reg = <0x48308000 0x10>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 637 | #address-cells = <1>; |
| 638 | #size-cells = <1>; |
| 639 | ranges; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 640 | ti,hwmods = "epwmss4"; |
| 641 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 642 | |
| 643 | ehrpwm4: ehrpwm@48308200 { |
| 644 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 645 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 646 | reg = <0x48308200 0x80>; |
| 647 | ti,hwmods = "ehrpwm4"; |
| 648 | status = "disabled"; |
| 649 | }; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 650 | }; |
| 651 | |
| 652 | epwmss5: epwmss@4830a000 { |
| 653 | compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; |
| 654 | reg = <0x4830a000 0x10>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 655 | #address-cells = <1>; |
| 656 | #size-cells = <1>; |
| 657 | ranges; |
Afzal Mohammed | 7345601 | 2013-08-02 19:16:35 +0530 | [diff] [blame] | 658 | ti,hwmods = "epwmss5"; |
| 659 | status = "disabled"; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 660 | |
| 661 | ehrpwm5: ehrpwm@4830a200 { |
| 662 | compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; |
Sourav Poddar | aa84230 | 2013-12-19 18:03:33 +0530 | [diff] [blame] | 663 | #pwm-cells = <3>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 664 | reg = <0x4830a200 0x80>; |
| 665 | ti,hwmods = "ehrpwm5"; |
| 666 | status = "disabled"; |
| 667 | }; |
| 668 | }; |
| 669 | |
| 670 | sham: sham@53100000 { |
| 671 | compatible = "ti,omap5-sham"; |
| 672 | ti,hwmods = "sham"; |
| 673 | reg = <0x53100000 0x300>; |
| 674 | dmas = <&edma 36>; |
| 675 | dma-names = "rx"; |
| 676 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 677 | }; |
Joel Fernandes | 6e70a51 | 2013-09-24 14:35:09 -0500 | [diff] [blame] | 678 | |
| 679 | aes: aes@53501000 { |
| 680 | compatible = "ti,omap4-aes"; |
| 681 | ti,hwmods = "aes"; |
| 682 | reg = <0x53501000 0xa0>; |
| 683 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 684 | dmas = <&edma 6 |
| 685 | &edma 5>; |
| 686 | dma-names = "tx", "rx"; |
Joel Fernandes | 6e70a51 | 2013-09-24 14:35:09 -0500 | [diff] [blame] | 687 | }; |
Joel Fernandes | 099f3a8 | 2013-09-24 14:37:33 -0500 | [diff] [blame] | 688 | |
| 689 | des: des@53701000 { |
| 690 | compatible = "ti,omap4-des"; |
| 691 | ti,hwmods = "des"; |
| 692 | reg = <0x53701000 0xa0>; |
| 693 | interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 694 | dmas = <&edma 34 |
| 695 | &edma 33>; |
| 696 | dma-names = "tx", "rx"; |
Joel Fernandes | 099f3a8 | 2013-09-24 14:37:33 -0500 | [diff] [blame] | 697 | }; |
Lokesh Vutla | 9e3269b | 2013-10-11 00:44:53 +0530 | [diff] [blame] | 698 | |
Peter Ujfalusi | b9c95bf | 2013-10-21 12:45:58 +0300 | [diff] [blame] | 699 | mcasp0: mcasp@48038000 { |
| 700 | compatible = "ti,am33xx-mcasp-audio"; |
| 701 | ti,hwmods = "mcasp0"; |
| 702 | reg = <0x48038000 0x2000>, |
| 703 | <0x46000000 0x400000>; |
| 704 | reg-names = "mpu", "dat"; |
| 705 | interrupts = <80>, <81>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 706 | interrupt-names = "tx", "rx"; |
Peter Ujfalusi | b9c95bf | 2013-10-21 12:45:58 +0300 | [diff] [blame] | 707 | status = "disabled"; |
| 708 | dmas = <&edma 8>, |
| 709 | <&edma 9>; |
| 710 | dma-names = "tx", "rx"; |
| 711 | }; |
| 712 | |
| 713 | mcasp1: mcasp@4803C000 { |
| 714 | compatible = "ti,am33xx-mcasp-audio"; |
| 715 | ti,hwmods = "mcasp1"; |
| 716 | reg = <0x4803C000 0x2000>, |
| 717 | <0x46400000 0x400000>; |
| 718 | reg-names = "mpu", "dat"; |
| 719 | interrupts = <82>, <83>; |
Geert Uytterhoeven | ae107d0 | 2014-04-22 20:40:25 +0200 | [diff] [blame] | 720 | interrupt-names = "tx", "rx"; |
Peter Ujfalusi | b9c95bf | 2013-10-21 12:45:58 +0300 | [diff] [blame] | 721 | status = "disabled"; |
| 722 | dmas = <&edma 10>, |
| 723 | <&edma 11>; |
| 724 | dma-names = "tx", "rx"; |
| 725 | }; |
Pekon Gupta | f68e355 | 2014-02-05 18:58:34 +0530 | [diff] [blame] | 726 | |
| 727 | elm: elm@48080000 { |
| 728 | compatible = "ti,am3352-elm"; |
| 729 | reg = <0x48080000 0x2000>; |
| 730 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| 731 | ti,hwmods = "elm"; |
| 732 | clocks = <&l4ls_gclk>; |
| 733 | clock-names = "fck"; |
| 734 | status = "disabled"; |
| 735 | }; |
| 736 | |
| 737 | gpmc: gpmc@50000000 { |
| 738 | compatible = "ti,am3352-gpmc"; |
| 739 | ti,hwmods = "gpmc"; |
| 740 | clocks = <&l3s_gclk>; |
| 741 | clock-names = "fck"; |
| 742 | reg = <0x50000000 0x2000>; |
| 743 | interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| 744 | gpmc,num-cs = <7>; |
| 745 | gpmc,num-waitpins = <2>; |
| 746 | #address-cells = <2>; |
| 747 | #size-cells = <1>; |
| 748 | status = "disabled"; |
| 749 | }; |
George Cherian | a0ae47e | 2014-03-19 15:40:01 +0530 | [diff] [blame] | 750 | |
| 751 | am43xx_control_usb2phy1: control-phy@44e10620 { |
| 752 | compatible = "ti,control-phy-usb2-am437"; |
| 753 | reg = <0x44e10620 0x4>; |
| 754 | reg-names = "power"; |
| 755 | }; |
| 756 | |
| 757 | am43xx_control_usb2phy2: control-phy@0x44e10628 { |
| 758 | compatible = "ti,control-phy-usb2-am437"; |
| 759 | reg = <0x44e10628 0x4>; |
| 760 | reg-names = "power"; |
| 761 | }; |
| 762 | |
| 763 | ocp2scp0: ocp2scp@483a8000 { |
| 764 | compatible = "ti,omap-ocp2scp"; |
| 765 | #address-cells = <1>; |
| 766 | #size-cells = <1>; |
| 767 | ranges; |
| 768 | ti,hwmods = "ocp2scp0"; |
| 769 | |
| 770 | usb2_phy1: phy@483a8000 { |
| 771 | compatible = "ti,am437x-usb2"; |
| 772 | reg = <0x483a8000 0x8000>; |
| 773 | ctrl-module = <&am43xx_control_usb2phy1>; |
| 774 | clocks = <&usb_phy0_always_on_clk32k>, |
| 775 | <&usb_otg_ss0_refclk960m>; |
| 776 | clock-names = "wkupclk", "refclk"; |
| 777 | #phy-cells = <0>; |
| 778 | status = "disabled"; |
| 779 | }; |
| 780 | }; |
| 781 | |
| 782 | ocp2scp1: ocp2scp@483e8000 { |
| 783 | compatible = "ti,omap-ocp2scp"; |
| 784 | #address-cells = <1>; |
| 785 | #size-cells = <1>; |
| 786 | ranges; |
| 787 | ti,hwmods = "ocp2scp1"; |
| 788 | |
| 789 | usb2_phy2: phy@483e8000 { |
| 790 | compatible = "ti,am437x-usb2"; |
| 791 | reg = <0x483e8000 0x8000>; |
| 792 | ctrl-module = <&am43xx_control_usb2phy2>; |
| 793 | clocks = <&usb_phy1_always_on_clk32k>, |
| 794 | <&usb_otg_ss1_refclk960m>; |
| 795 | clock-names = "wkupclk", "refclk"; |
| 796 | #phy-cells = <0>; |
| 797 | status = "disabled"; |
| 798 | }; |
| 799 | }; |
| 800 | |
| 801 | dwc3_1: omap_dwc3@48380000 { |
| 802 | compatible = "ti,am437x-dwc3"; |
| 803 | ti,hwmods = "usb_otg_ss0"; |
| 804 | reg = <0x48380000 0x10000>; |
| 805 | interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; |
| 806 | #address-cells = <1>; |
| 807 | #size-cells = <1>; |
| 808 | utmi-mode = <1>; |
| 809 | ranges; |
| 810 | |
| 811 | usb1: usb@48390000 { |
| 812 | compatible = "synopsys,dwc3"; |
Felipe Balbi | 4b143f0 | 2014-09-03 16:22:24 -0500 | [diff] [blame] | 813 | reg = <0x48390000 0x10000>; |
George Cherian | a0ae47e | 2014-03-19 15:40:01 +0530 | [diff] [blame] | 814 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 815 | phys = <&usb2_phy1>; |
| 816 | phy-names = "usb2-phy"; |
| 817 | maximum-speed = "high-speed"; |
| 818 | dr_mode = "otg"; |
| 819 | status = "disabled"; |
| 820 | }; |
| 821 | }; |
| 822 | |
| 823 | dwc3_2: omap_dwc3@483c0000 { |
| 824 | compatible = "ti,am437x-dwc3"; |
| 825 | ti,hwmods = "usb_otg_ss1"; |
| 826 | reg = <0x483c0000 0x10000>; |
| 827 | interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| 828 | #address-cells = <1>; |
| 829 | #size-cells = <1>; |
| 830 | utmi-mode = <1>; |
| 831 | ranges; |
| 832 | |
| 833 | usb2: usb@483d0000 { |
| 834 | compatible = "synopsys,dwc3"; |
Felipe Balbi | 4b143f0 | 2014-09-03 16:22:24 -0500 | [diff] [blame] | 835 | reg = <0x483d0000 0x10000>; |
George Cherian | a0ae47e | 2014-03-19 15:40:01 +0530 | [diff] [blame] | 836 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
| 837 | phys = <&usb2_phy2>; |
| 838 | phy-names = "usb2-phy"; |
| 839 | maximum-speed = "high-speed"; |
| 840 | dr_mode = "otg"; |
| 841 | status = "disabled"; |
| 842 | }; |
| 843 | }; |
Sourav Poddar | 2a1a504 | 2014-04-28 19:12:30 +0530 | [diff] [blame] | 844 | |
| 845 | qspi: qspi@47900000 { |
| 846 | compatible = "ti,am4372-qspi"; |
| 847 | reg = <0x47900000 0x100>; |
| 848 | #address-cells = <1>; |
| 849 | #size-cells = <0>; |
| 850 | ti,hwmods = "qspi"; |
| 851 | interrupts = <0 138 0x4>; |
| 852 | num-cs = <4>; |
| 853 | status = "disabled"; |
| 854 | }; |
Sourav Poddar | 741cac5 | 2014-05-08 11:30:07 +0530 | [diff] [blame] | 855 | |
| 856 | hdq: hdq@48347000 { |
| 857 | compatible = "ti,am43xx-hdq"; |
| 858 | reg = <0x48347000 0x1000>; |
| 859 | interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| 860 | clocks = <&func_12m_clk>; |
| 861 | clock-names = "fck"; |
| 862 | ti,hwmods = "hdq1w"; |
| 863 | status = "disabled"; |
| 864 | }; |
Sathya Prakash M R | 8c79336 | 2014-03-24 16:31:55 +0530 | [diff] [blame] | 865 | |
| 866 | dss: dss@4832a000 { |
| 867 | compatible = "ti,omap3-dss"; |
| 868 | reg = <0x4832a000 0x200>; |
| 869 | status = "disabled"; |
| 870 | ti,hwmods = "dss_core"; |
| 871 | clocks = <&disp_clk>; |
| 872 | clock-names = "fck"; |
| 873 | #address-cells = <1>; |
| 874 | #size-cells = <1>; |
| 875 | ranges; |
| 876 | |
Felipe Balbi | 08ecb28 | 2014-06-23 13:20:58 -0500 | [diff] [blame] | 877 | dispc: dispc@4832a400 { |
Sathya Prakash M R | 8c79336 | 2014-03-24 16:31:55 +0530 | [diff] [blame] | 878 | compatible = "ti,omap3-dispc"; |
| 879 | reg = <0x4832a400 0x400>; |
| 880 | interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| 881 | ti,hwmods = "dss_dispc"; |
| 882 | clocks = <&disp_clk>; |
| 883 | clock-names = "fck"; |
| 884 | }; |
| 885 | |
| 886 | rfbi: rfbi@4832a800 { |
| 887 | compatible = "ti,omap3-rfbi"; |
| 888 | reg = <0x4832a800 0x100>; |
| 889 | ti,hwmods = "dss_rfbi"; |
| 890 | clocks = <&disp_clk>; |
| 891 | clock-names = "fck"; |
| 892 | }; |
| 893 | }; |
Rajendra Nayak | 8b9a281 | 2014-09-10 11:04:03 -0500 | [diff] [blame] | 894 | |
| 895 | ocmcram: ocmcram@40300000 { |
| 896 | compatible = "mmio-sram"; |
| 897 | reg = <0x40300000 0x40000>; /* 256k */ |
| 898 | }; |
Afzal Mohammed | 6cfd811 | 2013-06-03 18:49:54 +0530 | [diff] [blame] | 899 | }; |
| 900 | }; |
Tero Kristo | 6a67920 | 2013-08-02 19:12:04 +0300 | [diff] [blame] | 901 | |
| 902 | /include/ "am43xx-clocks.dtsi" |