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Christian Daudt8ac49e02012-11-19 09:46:10 -08001/*
Markus Mayere3b62ff2013-08-02 13:12:21 -07002 * Copyright (C) 2012-2013 Broadcom Corporation
Christian Daudt8ac49e02012-11-19 09:46:10 -08003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
Matt Porter5401cc42013-06-06 01:41:35 -040014#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
Alex Elder2bb94532014-02-14 12:29:20 -060017#include "dt-bindings/clock/bcm281xx.h"
18
Matt Porter74375652013-06-06 01:41:34 -040019#include "skeleton.dtsi"
Christian Daudt8ac49e02012-11-19 09:46:10 -080020
21/ {
22 model = "BCM11351 SoC";
Christian Daudt15e22dd2013-07-30 16:27:10 -070023 compatible = "brcm,bcm11351";
Christian Daudt8ac49e02012-11-19 09:46:10 -080024 interrupt-parent = <&gic>;
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 };
29
Alex Eldera62451c2014-06-30 17:15:39 -050030 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "brcm,bcm11351-cpu-method";
34 secondary-boot-reg = <0x3500417c>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <1>;
46 };
47 };
48
Christian Daudt8ac49e02012-11-19 09:46:10 -080049 gic: interrupt-controller@3ff00100 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 #address-cells = <0>;
53 interrupt-controller;
54 reg = <0x3ff01000 0x1000>,
55 <0x3ff00100 0x100>;
56 };
57
Christian Daudt7f6c62e2013-03-13 15:05:37 -070058 smc@0x3404c000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -070059 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
Matt Porterd22dc5e2013-06-11 14:45:58 -040060 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
Christian Daudt7f6c62e2013-03-13 15:05:37 -070061 };
62
Christian Daudt8ac49e02012-11-19 09:46:10 -080063 uart@3e000000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -070064 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
Christian Daudt8ac49e02012-11-19 09:46:10 -080065 status = "disabled";
66 reg = <0x3e000000 0x1000>;
Alex Elder2bb94532014-02-14 12:29:20 -060067 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
Matt Porter5401cc42013-06-06 01:41:35 -040068 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
Christian Daudt8ac49e02012-11-19 09:46:10 -080069 reg-shift = <2>;
70 reg-io-width = <4>;
71 };
72
Tim Kryger84491c02013-09-23 10:49:57 -070073 uart@3e001000 {
74 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
75 status = "disabled";
76 reg = <0x3e001000 0x1000>;
Alex Elder2bb94532014-02-14 12:29:20 -060077 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
Tim Kryger84491c02013-09-23 10:49:57 -070078 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
79 reg-shift = <2>;
80 reg-io-width = <4>;
81 };
82
83 uart@3e002000 {
84 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
85 status = "disabled";
86 reg = <0x3e002000 0x1000>;
Alex Elder2bb94532014-02-14 12:29:20 -060087 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
Tim Kryger84491c02013-09-23 10:49:57 -070088 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
89 reg-shift = <2>;
90 reg-io-width = <4>;
91 };
92
93 uart@3e003000 {
94 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
95 status = "disabled";
96 reg = <0x3e003000 0x1000>;
Alex Elder2bb94532014-02-14 12:29:20 -060097 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
Tim Kryger84491c02013-09-23 10:49:57 -070098 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
99 reg-shift = <2>;
100 reg-io-width = <4>;
101 };
102
Christian Daudt8ac49e02012-11-19 09:46:10 -0800103 L2: l2-cache {
Christian Daudt15e22dd2013-07-30 16:27:10 -0700104 compatible = "brcm,bcm11351-a2-pl310-cache";
Christian Daudt3b656fe2013-05-09 22:21:01 +0100105 reg = <0x3ff20000 0x1000>;
106 cache-unified;
107 cache-level = <2>;
Christian Daudt8ac49e02012-11-19 09:46:10 -0800108 };
Christian Daudt5f03dc22013-03-13 14:27:28 -0700109
Markus Mayere3b62ff2013-08-02 13:12:21 -0700110 watchdog@35002f40 {
111 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
112 reg = <0x35002f40 0x6c>;
113 };
114
Christian Daudt5f03dc22013-03-13 14:27:28 -0700115 timer@35006000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -0700116 compatible = "brcm,kona-timer";
Christian Daudt5f03dc22013-03-13 14:27:28 -0700117 reg = <0x35006000 0x1000>;
Matt Porter5401cc42013-06-06 01:41:35 -0400118 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Alex Elder2bb94532014-02-14 12:29:20 -0600119 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
Christian Daudt5f03dc22013-03-13 14:27:28 -0700120 };
121
Markus Mayerd394c7b2013-09-10 11:07:03 -0700122 gpio: gpio@35003000 {
123 compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
124 reg = <0x35003000 0x800>;
125 interrupts =
126 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
127 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
128 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
129 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
130 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
131 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
132 #gpio-cells = <2>;
133 #interrupt-cells = <2>;
134 gpio-controller;
135 interrupt-controller;
136 };
137
Christian Daudtd7358f82013-08-07 22:37:47 -0700138 sdio1: sdio@3f180000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -0700139 compatible = "brcm,kona-sdhci";
Christian Daudt2dbfe742013-05-10 00:10:07 -0700140 reg = <0x3f180000 0x10000>;
Matt Porter9c0dae02013-09-19 13:18:26 -0400141 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
Alex Elder2bb94532014-02-14 12:29:20 -0600142 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
Christian Daudt2dbfe742013-05-10 00:10:07 -0700143 status = "disabled";
144 };
145
Christian Daudtd7358f82013-08-07 22:37:47 -0700146 sdio2: sdio@3f190000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -0700147 compatible = "brcm,kona-sdhci";
Christian Daudt2dbfe742013-05-10 00:10:07 -0700148 reg = <0x3f190000 0x10000>;
Matt Porter9c0dae02013-09-19 13:18:26 -0400149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
Alex Elder2bb94532014-02-14 12:29:20 -0600150 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
Christian Daudt2dbfe742013-05-10 00:10:07 -0700151 status = "disabled";
152 };
153
Christian Daudtd7358f82013-08-07 22:37:47 -0700154 sdio3: sdio@3f1a0000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -0700155 compatible = "brcm,kona-sdhci";
Christian Daudt2dbfe742013-05-10 00:10:07 -0700156 reg = <0x3f1a0000 0x10000>;
Matt Porter9c0dae02013-09-19 13:18:26 -0400157 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
Alex Elder2bb94532014-02-14 12:29:20 -0600158 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
Christian Daudt2dbfe742013-05-10 00:10:07 -0700159 status = "disabled";
160 };
161
Christian Daudtd7358f82013-08-07 22:37:47 -0700162 sdio4: sdio@3f1b0000 {
Christian Daudt15e22dd2013-07-30 16:27:10 -0700163 compatible = "brcm,kona-sdhci";
Christian Daudt2dbfe742013-05-10 00:10:07 -0700164 reg = <0x3f1b0000 0x10000>;
Matt Porter9c0dae02013-09-19 13:18:26 -0400165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
Alex Elder2bb94532014-02-14 12:29:20 -0600166 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
Christian Daudt2dbfe742013-05-10 00:10:07 -0700167 status = "disabled";
168 };
169
Sherman Yin67a57be2013-12-20 18:13:36 -0800170 pinctrl@35004800 {
Sherman Yina2530062014-01-23 12:44:47 -0800171 compatible = "brcm,bcm11351-pinctrl";
Sherman Yin67a57be2013-12-20 18:13:36 -0800172 reg = <0x35004800 0x430>;
173 };
Linus Torvaldsf8a504c2014-01-30 18:08:27 -0800174
Tim Krygerdfc4334b2013-12-06 15:45:27 -0800175 i2c@3e016000 {
176 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
177 reg = <0x3e016000 0x80>;
178 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600181 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
Tim Krygerdfc4334b2013-12-06 15:45:27 -0800182 status = "disabled";
183 };
184
185 i2c@3e017000 {
186 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
187 reg = <0x3e017000 0x80>;
188 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
189 #address-cells = <1>;
190 #size-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600191 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
Tim Krygerdfc4334b2013-12-06 15:45:27 -0800192 status = "disabled";
193 };
194
195 i2c@3e018000 {
196 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
197 reg = <0x3e018000 0x80>;
198 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
199 #address-cells = <1>;
200 #size-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600201 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
Tim Krygerdfc4334b2013-12-06 15:45:27 -0800202 status = "disabled";
203 };
204
205 i2c@3500d000 {
206 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
207 reg = <0x3500d000 0x80>;
208 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600211 clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
Tim Krygerdfc4334b2013-12-06 15:45:27 -0800212 status = "disabled";
213 };
214
Tim Krygercc33e422014-04-25 11:31:13 -0700215 pwm: pwm@3e01a000 {
216 compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
217 reg = <0x3e01a000 0xcc>;
218 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
219 #pwm-cells = <3>;
220 status = "disabled";
221 };
222
Tim Kryger0bd898b2013-12-05 11:20:37 -0800223 clocks {
Alex Elder2bb94532014-02-14 12:29:20 -0600224 #address-cells = <1>;
225 #size-cells = <1>;
226 ranges;
227
228 root_ccu: root_ccu {
229 compatible = "brcm,bcm11351-root-ccu";
230 reg = <0x35001000 0x0f00>;
231 #clock-cells = <1>;
232 clock-output-names = "frac_1m";
Tim Kryger0bd898b2013-12-05 11:20:37 -0800233 };
234
Alex Elder2bb94532014-02-14 12:29:20 -0600235 hub_ccu: hub_ccu {
236 compatible = "brcm,bcm11351-hub-ccu";
237 reg = <0x34000000 0x0f00>;
238 #clock-cells = <1>;
239 clock-output-names = "tmon_1m";
Tim Kryger0bd898b2013-12-05 11:20:37 -0800240 };
241
Alex Elder2bb94532014-02-14 12:29:20 -0600242 aon_ccu: aon_ccu {
243 compatible = "brcm,bcm11351-aon-ccu";
244 reg = <0x35002000 0x0f00>;
245 #clock-cells = <1>;
246 clock-output-names = "hub_timer",
247 "pmu_bsc",
248 "pmu_bsc_var";
Tim Kryger0bd898b2013-12-05 11:20:37 -0800249 };
250
Alex Elder2bb94532014-02-14 12:29:20 -0600251 master_ccu: master_ccu {
252 compatible = "brcm,bcm11351-master-ccu";
253 reg = <0x3f001000 0x0f00>;
254 #clock-cells = <1>;
255 clock-output-names = "sdio1",
256 "sdio2",
257 "sdio3",
258 "sdio4",
259 "usb_ic",
260 "hsic2_48m",
261 "hsic2_12m";
Tim Kryger0bd898b2013-12-05 11:20:37 -0800262 };
263
Alex Elder2bb94532014-02-14 12:29:20 -0600264 slave_ccu: slave_ccu {
265 compatible = "brcm,bcm11351-slave-ccu";
266 reg = <0x3e011000 0x0f00>;
267 #clock-cells = <1>;
268 clock-output-names = "uartb",
269 "uartb2",
270 "uartb3",
271 "uartb4",
272 "ssp0",
273 "ssp2",
274 "bsc1",
275 "bsc2",
276 "bsc3",
277 "pwm";
Tim Kryger0bd898b2013-12-05 11:20:37 -0800278 };
279
Alex Elder2bb94532014-02-14 12:29:20 -0600280 ref_1m_clk: ref_1m {
Tim Kryger0bd898b2013-12-05 11:20:37 -0800281 #clock-cells = <0>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800282 compatible = "fixed-clock";
283 clock-frequency = <1000000>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800284 };
285
Alex Elder2bb94532014-02-14 12:29:20 -0600286 ref_32k_clk: ref_32k {
Tim Kryger0bd898b2013-12-05 11:20:37 -0800287 #clock-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600288 compatible = "fixed-clock";
289 clock-frequency = <32768>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800290 };
291
Alex Elder2bb94532014-02-14 12:29:20 -0600292 bbl_32k_clk: bbl_32k {
Tim Kryger0bd898b2013-12-05 11:20:37 -0800293 #clock-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600294 compatible = "fixed-clock";
295 clock-frequency = <32768>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800296 };
297
Alex Elder2bb94532014-02-14 12:29:20 -0600298 ref_13m_clk: ref_13m {
299 #clock-cells = <0>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800300 compatible = "fixed-clock";
301 clock-frequency = <13000000>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800302 };
303
Alex Elder2bb94532014-02-14 12:29:20 -0600304 var_13m_clk: var_13m {
305 #clock-cells = <0>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800306 compatible = "fixed-clock";
307 clock-frequency = <13000000>;
Alex Elder2bb94532014-02-14 12:29:20 -0600308 };
309
310 dft_19_5m_clk: dft_19_5m {
Tim Kryger0bd898b2013-12-05 11:20:37 -0800311 #clock-cells = <0>;
Alex Elder2bb94532014-02-14 12:29:20 -0600312 compatible = "fixed-clock";
313 clock-frequency = <19500000>;
314 };
315
316 ref_crystal_clk: ref_crystal {
317 #clock-cells = <0>;
318 compatible = "fixed-clock";
319 clock-frequency = <26000000>;
320 };
321
322 ref_cx40_clk: ref_cx40 {
323 #clock-cells = <0>;
324 compatible = "fixed-clock";
325 clock-frequency = <40000000>;
326 };
327
328 ref_52m_clk: ref_52m {
329 #clock-cells = <0>;
330 compatible = "fixed-clock";
331 clock-frequency = <52000000>;
332 };
333
334 var_52m_clk: var_52m {
335 #clock-cells = <0>;
336 compatible = "fixed-clock";
337 clock-frequency = <52000000>;
Tim Kryger0bd898b2013-12-05 11:20:37 -0800338 };
339
340 usb_otg_ahb_clk: usb_otg_ahb {
341 compatible = "fixed-clock";
342 clock-frequency = <52000000>;
343 #clock-cells = <0>;
344 };
Alex Elder2bb94532014-02-14 12:29:20 -0600345
346 ref_96m_clk: ref_96m {
347 #clock-cells = <0>;
348 compatible = "fixed-clock";
349 clock-frequency = <96000000>;
350 };
351
352 var_96m_clk: var_96m {
353 #clock-cells = <0>;
354 compatible = "fixed-clock";
355 clock-frequency = <96000000>;
356 };
357
358 ref_104m_clk: ref_104m {
359 #clock-cells = <0>;
360 compatible = "fixed-clock";
361 clock-frequency = <104000000>;
362 };
363
364 var_104m_clk: var_104m {
365 #clock-cells = <0>;
366 compatible = "fixed-clock";
367 clock-frequency = <104000000>;
368 };
369
370 ref_156m_clk: ref_156m {
371 #clock-cells = <0>;
372 compatible = "fixed-clock";
373 clock-frequency = <156000000>;
374 };
375
376 var_156m_clk: var_156m {
377 #clock-cells = <0>;
378 compatible = "fixed-clock";
379 clock-frequency = <156000000>;
380 };
381
382 ref_208m_clk: ref_208m {
383 #clock-cells = <0>;
384 compatible = "fixed-clock";
385 clock-frequency = <208000000>;
386 };
387
388 var_208m_clk: var_208m {
389 #clock-cells = <0>;
390 compatible = "fixed-clock";
391 clock-frequency = <208000000>;
392 };
393
394 ref_312m_clk: ref_312m {
395 #clock-cells = <0>;
396 compatible = "fixed-clock";
397 clock-frequency = <312000000>;
398 };
399
400 var_312m_clk: var_312m {
401 #clock-cells = <0>;
402 compatible = "fixed-clock";
403 clock-frequency = <312000000>;
404 };
Tim Kryger0bd898b2013-12-05 11:20:37 -0800405 };
Matt Porterd97f7992013-12-19 09:23:10 -0500406
407 usbotg: usb@3f120000 {
408 compatible = "snps,dwc2";
409 reg = <0x3f120000 0x10000>;
410 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&usb_otg_ahb_clk>;
412 clock-names = "otg";
413 phys = <&usbphy>;
414 phy-names = "usb2-phy";
415 status = "disabled";
416 };
417
418 usbphy: usb-phy@3f130000 {
419 compatible = "brcm,kona-usb2-phy";
420 reg = <0x3f130000 0x28>;
421 #phy-cells = <0>;
422 status = "disabled";
423 };
Christian Daudt8ac49e02012-11-19 09:46:10 -0800424};