blob: 53c624f766b48525dc0da30f944b5b1ea5f7da80 [file] [log] [blame]
Hauke Mehrtensd27509f2014-02-04 00:01:45 +01001/*
2 * Broadcom BCM470X / BCM5301X ARM platform code.
3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
5 *
6 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include "skeleton.dtsi"
14
15/ {
16 interrupt-parent = <&gic>;
17
18 chipcommonA {
19 compatible = "simple-bus";
20 ranges = <0x00000000 0x18000000 0x00001000>;
21 #address-cells = <1>;
22 #size-cells = <1>;
23
24 uart0: serial@0300 {
25 compatible = "ns16550";
26 reg = <0x0300 0x100>;
27 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
28 clock-frequency = <100000000>;
29 status = "disabled";
30 };
31
32 uart1: serial@0400 {
33 compatible = "ns16550";
34 reg = <0x0400 0x100>;
35 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
36 clock-frequency = <100000000>;
37 status = "disabled";
38 };
39 };
40
41 mpcore {
42 compatible = "simple-bus";
43 ranges = <0x00000000 0x19020000 0x00003000>;
44 #address-cells = <1>;
45 #size-cells = <1>;
46
47 scu@0000 {
48 compatible = "arm,cortex-a9-scu";
49 reg = <0x0000 0x100>;
50 };
51
52 timer@0200 {
53 compatible = "arm,cortex-a9-global-timer";
54 reg = <0x0200 0x100>;
55 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&clk_periph>;
57 };
58
59 local-timer@0600 {
60 compatible = "arm,cortex-a9-twd-timer";
61 reg = <0x0600 0x100>;
62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
63 clocks = <&clk_periph>;
64 };
65
66 gic: interrupt-controller@1000 {
67 compatible = "arm,cortex-a9-gic";
68 #interrupt-cells = <3>;
69 #address-cells = <0>;
70 interrupt-controller;
71 reg = <0x1000 0x1000>,
72 <0x0100 0x100>;
73 };
74
75 L2: cache-controller@2000 {
76 compatible = "arm,pl310-cache";
77 reg = <0x2000 0x1000>;
78 cache-unified;
79 cache-level = <2>;
80 };
81 };
82
83 clocks {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 /* As long as we do not have a real clock driver us this
88 * fixed clock */
89 clk_periph: periph {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <400000000>;
93 };
94 };
95};