Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2012 Sascha Hauer, Pengutronix |
| 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License |
| 6 | * Version 2 or later at the following locations: |
| 7 | * |
| 8 | * http://www.opensource.org/licenses/gpl-license.html |
| 9 | * http://www.gnu.org/copyleft/gpl.html |
| 10 | */ |
| 11 | |
| 12 | /dts-v1/; |
Shawn Guo | 36dffd8 | 2013-04-07 10:49:34 +0800 | [diff] [blame] | 13 | #include "imx27.dtsi" |
Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 14 | |
| 15 | / { |
| 16 | model = "Phytec pcm038"; |
| 17 | compatible = "phytec,imx27-pcm038", "fsl,imx27"; |
| 18 | |
| 19 | memory { |
Alexander Shiyan | 999f681 | 2013-06-23 10:54:49 +0400 | [diff] [blame] | 20 | reg = <0xa0000000 0x08000000>; |
Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 21 | }; |
Alexander Shiyan | f64ba74 | 2013-11-30 10:18:03 +0400 | [diff] [blame] | 22 | |
| 23 | regulators { |
| 24 | compatible = "simple-bus"; |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | |
| 28 | reg_3v3: regulator@0 { |
| 29 | compatible = "regulator-fixed"; |
| 30 | reg = <0>; |
| 31 | regulator-name = "3V3"; |
| 32 | regulator-min-microvolt = <3300000>; |
| 33 | regulator-max-microvolt = <3300000>; |
| 34 | }; |
Alexander Shiyan | 9089ce5 | 2014-02-22 13:32:34 +0400 | [diff] [blame] | 35 | |
| 36 | reg_5v0: regulator@1 { |
| 37 | compatible = "regulator-fixed"; |
| 38 | reg = <1>; |
| 39 | regulator-name = "5V0"; |
| 40 | regulator-min-microvolt = <5000000>; |
| 41 | regulator-max-microvolt = <5000000>; |
| 42 | }; |
Alexander Shiyan | f64ba74 | 2013-11-30 10:18:03 +0400 | [diff] [blame] | 43 | }; |
Fabio Estevam | af38a00 | 2014-04-16 14:53:19 -0300 | [diff] [blame] | 44 | |
| 45 | usbphy { |
| 46 | compatible = "simple-bus"; |
| 47 | #address-cells = <1>; |
| 48 | #size-cells = <0>; |
| 49 | |
| 50 | usbphy0: usbphy@0 { |
| 51 | compatible = "usb-nop-xceiv"; |
| 52 | reg = <0>; |
| 53 | vcc-supply = <&sw3_reg>; |
Alexander Shiyan | ea336fa8 | 2014-07-05 09:36:07 +0400 | [diff] [blame] | 54 | clocks = <&clks IMX27_CLK_DUMMY>; |
Fabio Estevam | af38a00 | 2014-04-16 14:53:19 -0300 | [diff] [blame] | 55 | clock-names = "main_clk"; |
| 56 | }; |
| 57 | }; |
Sascha Hauer | 10a9ba0 | 2012-02-28 21:58:37 +0100 | [diff] [blame] | 58 | }; |
Alexander Shiyan | 1b45ace | 2013-04-07 19:29:12 +0400 | [diff] [blame] | 59 | |
Alexander Shiyan | a919c69 | 2013-08-10 12:51:51 +0400 | [diff] [blame] | 60 | &audmux { |
| 61 | status = "okay"; |
| 62 | |
| 63 | /* SSI0 <=> PINS_4 (MC13783 Audio) */ |
| 64 | ssi0 { |
| 65 | fsl,audmux-port = <0>; |
| 66 | fsl,port-config = <0xcb205000>; |
| 67 | }; |
| 68 | |
| 69 | pins4 { |
| 70 | fsl,audmux-port = <2>; |
| 71 | fsl,port-config = <0x00001000>; |
| 72 | }; |
| 73 | }; |
| 74 | |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 75 | &cspi1 { |
Alexander Shiyan | f4bdf21 | 2013-12-07 12:26:35 +0400 | [diff] [blame] | 76 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = <&pinctrl_cspi1>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 78 | fsl,spi-num-chipselects = <1>; |
Alexander Shiyan | 6ece55b | 2013-11-30 10:18:04 +0400 | [diff] [blame] | 79 | cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 80 | status = "okay"; |
| 81 | |
| 82 | pmic: mc13783@0 { |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 83 | compatible = "fsl,mc13783"; |
Fabio Estevam | 2286908 | 2014-04-16 08:25:56 -0300 | [diff] [blame] | 84 | pinctrl-names = "default"; |
| 85 | pinctrl-0 = <&pinctrl_pmic>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 86 | reg = <0>; |
Alexander Shiyan | 986cc49 | 2013-12-21 11:11:39 +0400 | [diff] [blame] | 87 | spi-cs-high; |
| 88 | spi-max-frequency = <20000000>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 89 | interrupt-parent = <&gpio2>; |
Alexander Shiyan | 6ece55b | 2013-11-30 10:18:04 +0400 | [diff] [blame] | 90 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 91 | fsl,mc13xxx-uses-adc; |
| 92 | fsl,mc13xxx-uses-rtc; |
| 93 | |
Alexander Shiyan | 5ee49a1 | 2014-02-15 15:35:18 +0400 | [diff] [blame] | 94 | pmicleds: leds { |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | led-control = <0x001 0x000 0x000 0x000 0x000 0x000>; |
| 98 | }; |
| 99 | |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 100 | regulators { |
Alexander Shiyan | e9c1786 | 2013-07-20 11:17:59 +0400 | [diff] [blame] | 101 | /* SW1A and SW1B joined operation */ |
| 102 | sw1_reg: sw1a { |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 103 | regulator-min-microvolt = <1200000>; |
Alexander Shiyan | e9c1786 | 2013-07-20 11:17:59 +0400 | [diff] [blame] | 104 | regulator-max-microvolt = <1520000>; |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 105 | regulator-always-on; |
| 106 | regulator-boot-on; |
| 107 | }; |
| 108 | |
Alexander Shiyan | e9c1786 | 2013-07-20 11:17:59 +0400 | [diff] [blame] | 109 | /* SW2A and SW2B joined operation */ |
| 110 | sw2_reg: sw2a { |
Alexander Shiyan | 5d3503c | 2013-05-03 12:08:21 +0400 | [diff] [blame] | 111 | regulator-min-microvolt = <1800000>; |
| 112 | regulator-max-microvolt = <1800000>; |
| 113 | regulator-always-on; |
| 114 | regulator-boot-on; |
| 115 | }; |
| 116 | |
| 117 | sw3_reg: sw3 { |
| 118 | regulator-min-microvolt = <5000000>; |
| 119 | regulator-max-microvolt = <5000000>; |
| 120 | regulator-always-on; |
| 121 | regulator-boot-on; |
| 122 | }; |
| 123 | |
| 124 | vaudio_reg: vaudio { |
| 125 | regulator-always-on; |
| 126 | regulator-boot-on; |
| 127 | }; |
| 128 | |
| 129 | violo_reg: violo { |
| 130 | regulator-min-microvolt = <1800000>; |
| 131 | regulator-max-microvolt = <1800000>; |
| 132 | regulator-always-on; |
| 133 | regulator-boot-on; |
| 134 | }; |
| 135 | |
| 136 | viohi_reg: viohi { |
| 137 | regulator-always-on; |
| 138 | regulator-boot-on; |
| 139 | }; |
| 140 | |
| 141 | vgen_reg: vgen { |
| 142 | regulator-min-microvolt = <1500000>; |
| 143 | regulator-max-microvolt = <1500000>; |
| 144 | regulator-always-on; |
| 145 | regulator-boot-on; |
| 146 | }; |
| 147 | |
| 148 | vcam_reg: vcam { |
| 149 | regulator-min-microvolt = <2800000>; |
| 150 | regulator-max-microvolt = <2800000>; |
| 151 | }; |
| 152 | |
| 153 | vrf1_reg: vrf1 { |
| 154 | regulator-min-microvolt = <2775000>; |
| 155 | regulator-max-microvolt = <2775000>; |
| 156 | regulator-always-on; |
| 157 | regulator-boot-on; |
| 158 | }; |
| 159 | |
| 160 | vrf2_reg: vrf2 { |
| 161 | regulator-min-microvolt = <2775000>; |
| 162 | regulator-max-microvolt = <2775000>; |
| 163 | regulator-always-on; |
| 164 | regulator-boot-on; |
| 165 | }; |
| 166 | |
| 167 | vmmc1_reg: vmmc1 { |
| 168 | regulator-min-microvolt = <1600000>; |
| 169 | regulator-max-microvolt = <3000000>; |
| 170 | }; |
| 171 | |
| 172 | gpo1_reg: gpo1 { }; |
| 173 | |
| 174 | pwgt1spi_reg: pwgt1spi { |
| 175 | regulator-always-on; |
| 176 | }; |
| 177 | }; |
| 178 | }; |
| 179 | }; |
| 180 | |
Alexander Shiyan | f0d8e3f | 2013-07-02 20:02:29 +0400 | [diff] [blame] | 181 | &fec { |
Alexander Shiyan | f64ba74 | 2013-11-30 10:18:03 +0400 | [diff] [blame] | 182 | phy-mode = "mii"; |
Alexander Shiyan | 198e31d | 2014-04-26 08:52:07 +0400 | [diff] [blame] | 183 | phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; |
Alexander Shiyan | f64ba74 | 2013-11-30 10:18:03 +0400 | [diff] [blame] | 184 | phy-supply = <®_3v3>; |
Markus Pargmann | 26508cb | 2014-02-08 14:15:37 +0800 | [diff] [blame] | 185 | pinctrl-names = "default"; |
| 186 | pinctrl-0 = <&pinctrl_fec1>; |
Alexander Shiyan | f0d8e3f | 2013-07-02 20:02:29 +0400 | [diff] [blame] | 187 | status = "okay"; |
| 188 | }; |
| 189 | |
| 190 | &i2c2 { |
| 191 | clock-frequency = <400000>; |
Markus Pargmann | 26508cb | 2014-02-08 14:15:37 +0800 | [diff] [blame] | 192 | pinctrl-names = "default"; |
| 193 | pinctrl-0 = <&pinctrl_i2c2>; |
Alexander Shiyan | f0d8e3f | 2013-07-02 20:02:29 +0400 | [diff] [blame] | 194 | status = "okay"; |
| 195 | |
| 196 | at24@52 { |
| 197 | compatible = "at,24c32"; |
| 198 | pagesize = <32>; |
| 199 | reg = <0x52>; |
| 200 | }; |
| 201 | |
| 202 | pcf8563@51 { |
| 203 | compatible = "nxp,pcf8563"; |
| 204 | reg = <0x51>; |
| 205 | }; |
| 206 | |
| 207 | lm75@4a { |
| 208 | compatible = "national,lm75"; |
| 209 | reg = <0x4a>; |
| 210 | }; |
| 211 | }; |
| 212 | |
Markus Pargmann | 26508cb | 2014-02-08 14:15:37 +0800 | [diff] [blame] | 213 | &iomuxc { |
| 214 | imx27_phycore_som { |
Alexander Shiyan | f4bdf21 | 2013-12-07 12:26:35 +0400 | [diff] [blame] | 215 | pinctrl_cspi1: cspi1grp { |
| 216 | fsl,pins = < |
| 217 | MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0 |
| 218 | MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0 |
| 219 | MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0 |
| 220 | MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* SPI1 CS0 */ |
Alexander Shiyan | f4bdf21 | 2013-12-07 12:26:35 +0400 | [diff] [blame] | 221 | >; |
| 222 | }; |
| 223 | |
Markus Pargmann | 26508cb | 2014-02-08 14:15:37 +0800 | [diff] [blame] | 224 | pinctrl_fec1: fec1grp { |
| 225 | fsl,pins = < |
| 226 | MX27_PAD_SD3_CMD__FEC_TXD0 0x0 |
| 227 | MX27_PAD_SD3_CLK__FEC_TXD1 0x0 |
| 228 | MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 |
| 229 | MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 |
| 230 | MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 |
| 231 | MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 |
| 232 | MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 |
| 233 | MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 |
| 234 | MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 |
| 235 | MX27_PAD_ATA_DATA7__FEC_MDC 0x0 |
| 236 | MX27_PAD_ATA_DATA8__FEC_CRS 0x0 |
| 237 | MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 |
| 238 | MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 |
| 239 | MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 |
| 240 | MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 |
| 241 | MX27_PAD_ATA_DATA13__FEC_COL 0x0 |
| 242 | MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 |
| 243 | MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 |
| 244 | MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */ |
| 245 | >; |
| 246 | }; |
| 247 | |
| 248 | pinctrl_i2c2: i2c2grp { |
| 249 | fsl,pins = < |
| 250 | MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 |
| 251 | MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 |
| 252 | >; |
| 253 | }; |
Alexander Shiyan | dde5697 | 2013-12-21 11:11:37 +0400 | [diff] [blame] | 254 | |
| 255 | pinctrl_nfc: nfcgrp { |
| 256 | fsl,pins = < |
| 257 | MX27_PAD_NFRB__NFRB 0x0 |
| 258 | MX27_PAD_NFCLE__NFCLE 0x0 |
| 259 | MX27_PAD_NFWP_B__NFWP_B 0x0 |
| 260 | MX27_PAD_NFCE_B__NFCE_B 0x0 |
| 261 | MX27_PAD_NFALE__NFALE 0x0 |
| 262 | MX27_PAD_NFRE_B__NFRE_B 0x0 |
| 263 | MX27_PAD_NFWE_B__NFWE_B 0x0 |
| 264 | >; |
| 265 | }; |
Alexander Shiyan | 74ded65 | 2014-02-22 13:32:35 +0400 | [diff] [blame] | 266 | |
Fabio Estevam | 2286908 | 2014-04-16 08:25:56 -0300 | [diff] [blame] | 267 | pinctrl_pmic: pmicgrp { |
| 268 | fsl,pins = < |
| 269 | MX27_PAD_USB_PWR__GPIO2_23 0x0 /* PMIC IRQ */ |
| 270 | >; |
| 271 | }; |
| 272 | |
Alexander Shiyan | 2c40568 | 2014-03-02 13:18:39 +0400 | [diff] [blame] | 273 | pinctrl_ssi1: ssi1grp { |
| 274 | fsl,pins = < |
| 275 | MX27_PAD_SSI1_FS__SSI1_FS 0x0 |
| 276 | MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0 |
| 277 | MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0 |
| 278 | MX27_PAD_SSI1_CLK__SSI1_CLK 0x0 |
| 279 | >; |
| 280 | }; |
| 281 | |
Alexander Shiyan | 74ded65 | 2014-02-22 13:32:35 +0400 | [diff] [blame] | 282 | pinctrl_usbotg: usbotggrp { |
| 283 | fsl,pins = < |
| 284 | MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 |
| 285 | MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 |
| 286 | MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 |
| 287 | MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 |
| 288 | MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 |
| 289 | MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 |
| 290 | MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 |
| 291 | MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 |
| 292 | MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 |
| 293 | MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 |
| 294 | MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 |
| 295 | MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 |
| 296 | >; |
| 297 | }; |
Markus Pargmann | 26508cb | 2014-02-08 14:15:37 +0800 | [diff] [blame] | 298 | }; |
| 299 | }; |
| 300 | |
Alexander Shiyan | 1b45ace | 2013-04-07 19:29:12 +0400 | [diff] [blame] | 301 | &nfc { |
Alexander Shiyan | dde5697 | 2013-12-21 11:11:37 +0400 | [diff] [blame] | 302 | pinctrl-names = "default"; |
| 303 | pinctrl-0 = <&pinctrl_nfc>; |
Alexander Shiyan | 1b45ace | 2013-04-07 19:29:12 +0400 | [diff] [blame] | 304 | nand-bus-width = <8>; |
| 305 | nand-ecc-mode = "hw"; |
Alexander Shiyan | d9a57aa | 2013-11-30 10:18:01 +0400 | [diff] [blame] | 306 | nand-on-flash-bbt; |
Alexander Shiyan | 1b45ace | 2013-04-07 19:29:12 +0400 | [diff] [blame] | 307 | status = "okay"; |
| 308 | }; |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 309 | |
Alexander Shiyan | 2c40568 | 2014-03-02 13:18:39 +0400 | [diff] [blame] | 310 | &ssi1 { |
| 311 | pinctrl-names = "default"; |
| 312 | pinctrl-0 = <&pinctrl_ssi1>; |
Alexander Shiyan | 2c40568 | 2014-03-02 13:18:39 +0400 | [diff] [blame] | 313 | status = "okay"; |
| 314 | }; |
| 315 | |
Alexander Shiyan | 74ded65 | 2014-02-22 13:32:35 +0400 | [diff] [blame] | 316 | &usbotg { |
| 317 | pinctrl-names = "default"; |
| 318 | pinctrl-0 = <&pinctrl_usbotg>; |
| 319 | dr_mode = "otg"; |
| 320 | phy_type = "ulpi"; |
Fabio Estevam | af38a00 | 2014-04-16 14:53:19 -0300 | [diff] [blame] | 321 | fsl,usbphy = <&usbphy0>; |
Alexander Shiyan | 74ded65 | 2014-02-22 13:32:35 +0400 | [diff] [blame] | 322 | vbus-supply = <&sw3_reg>; |
Alexander Shiyan | 4ee927e | 2014-04-26 08:52:08 +0400 | [diff] [blame] | 323 | disable-over-current; |
Alexander Shiyan | 74ded65 | 2014-02-22 13:32:35 +0400 | [diff] [blame] | 324 | status = "okay"; |
| 325 | }; |
| 326 | |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 327 | &weim { |
| 328 | status = "okay"; |
| 329 | |
Alexander Shiyan | 3c3ea29 | 2014-04-09 19:08:16 +0400 | [diff] [blame] | 330 | nor: nor@0,0 { |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 331 | compatible = "cfi-flash"; |
| 332 | reg = <0 0x00000000 0x02000000>; |
| 333 | bank-width = <2>; |
| 334 | linux,mtd-name = "physmap-flash.0"; |
| 335 | fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>; |
| 336 | #address-cells = <1>; |
| 337 | #size-cells = <1>; |
| 338 | }; |
Alexander Shiyan | cff2a713 | 2013-07-02 20:02:27 +0400 | [diff] [blame] | 339 | |
Alexander Shiyan | 3c3ea29 | 2014-04-09 19:08:16 +0400 | [diff] [blame] | 340 | sram: sram@1,0 { |
Alexander Shiyan | cff2a713 | 2013-07-02 20:02:27 +0400 | [diff] [blame] | 341 | compatible = "mtd-ram"; |
| 342 | reg = <1 0x00000000 0x00800000>; |
| 343 | bank-width = <2>; |
| 344 | linux,mtd-name = "mtd-ram.0"; |
| 345 | fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>; |
| 346 | #address-cells = <1>; |
| 347 | #size-cells = <1>; |
| 348 | }; |
Alexander Shiyan | 984d6fc | 2013-07-02 20:02:26 +0400 | [diff] [blame] | 349 | }; |